1ea8ad1d9SLokesh Vutla// SPDX-License-Identifier: GPL-2.0 2ea8ad1d9SLokesh Vutla/* 3ea8ad1d9SLokesh Vutla * Device Tree Source for AM6 SoC Family 4ea8ad1d9SLokesh Vutla * 5ea8ad1d9SLokesh Vutla * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ 6ea8ad1d9SLokesh Vutla */ 7ea8ad1d9SLokesh Vutla 8ea8ad1d9SLokesh Vutla#include <dt-bindings/gpio/gpio.h> 9ea8ad1d9SLokesh Vutla#include <dt-bindings/interrupt-controller/irq.h> 10ea8ad1d9SLokesh Vutla#include <dt-bindings/interrupt-controller/arm-gic.h> 11ea8ad1d9SLokesh Vutla 12ea8ad1d9SLokesh Vutla/ { 13ea8ad1d9SLokesh Vutla model = "Texas Instruments K3 AM654 SoC"; 14ea8ad1d9SLokesh Vutla compatible = "ti,am654"; 15ea8ad1d9SLokesh Vutla interrupt-parent = <&gic500>; 16ea8ad1d9SLokesh Vutla #address-cells = <2>; 17ea8ad1d9SLokesh Vutla #size-cells = <2>; 18ea8ad1d9SLokesh Vutla 19*2d0eba3aSLokesh Vutla aliases { 20*2d0eba3aSLokesh Vutla serial0 = &wkup_uart0; 21*2d0eba3aSLokesh Vutla serial1 = &mcu_uart0; 22*2d0eba3aSLokesh Vutla serial2 = &main_uart0; 23*2d0eba3aSLokesh Vutla serial3 = &main_uart1; 24*2d0eba3aSLokesh Vutla serial4 = &main_uart2; 25*2d0eba3aSLokesh Vutla }; 26*2d0eba3aSLokesh Vutla 27ea8ad1d9SLokesh Vutla chosen { }; 28ea8ad1d9SLokesh Vutla 29ea8ad1d9SLokesh Vutla firmware { 30ea8ad1d9SLokesh Vutla optee { 31ea8ad1d9SLokesh Vutla compatible = "linaro,optee-tz"; 32ea8ad1d9SLokesh Vutla method = "smc"; 33ea8ad1d9SLokesh Vutla }; 34ea8ad1d9SLokesh Vutla 35ea8ad1d9SLokesh Vutla psci: psci { 36ea8ad1d9SLokesh Vutla compatible = "arm,psci-1.0"; 37ea8ad1d9SLokesh Vutla method = "smc"; 38ea8ad1d9SLokesh Vutla }; 39ea8ad1d9SLokesh Vutla }; 40ea8ad1d9SLokesh Vutla 41ea8ad1d9SLokesh Vutla a53_timer0: timer-cl0-cpu0 { 42ea8ad1d9SLokesh Vutla compatible = "arm,armv8-timer"; 43ea8ad1d9SLokesh Vutla interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 44ea8ad1d9SLokesh Vutla <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 45ea8ad1d9SLokesh Vutla <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 46ea8ad1d9SLokesh Vutla <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 47ea8ad1d9SLokesh Vutla }; 48ea8ad1d9SLokesh Vutla 49ea8ad1d9SLokesh Vutla pmu: pmu { 50ea8ad1d9SLokesh Vutla compatible = "arm,armv8-pmuv3"; 51ea8ad1d9SLokesh Vutla /* Recommendation from GIC500 TRM Table A.3 */ 52ea8ad1d9SLokesh Vutla interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 53ea8ad1d9SLokesh Vutla }; 54ea8ad1d9SLokesh Vutla 55ea8ad1d9SLokesh Vutla cbass_main: interconnect@100000 { 56ea8ad1d9SLokesh Vutla compatible = "simple-bus"; 57*2d0eba3aSLokesh Vutla #address-cells = <2>; 58*2d0eba3aSLokesh Vutla #size-cells = <2>; 59*2d0eba3aSLokesh Vutla ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 60*2d0eba3aSLokesh Vutla <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 61*2d0eba3aSLokesh Vutla <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ 62*2d0eba3aSLokesh Vutla <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ 63*2d0eba3aSLokesh Vutla <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ 64ea8ad1d9SLokesh Vutla /* MCUSS Range */ 65*2d0eba3aSLokesh Vutla <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 66*2d0eba3aSLokesh Vutla <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, 67*2d0eba3aSLokesh Vutla <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 68*2d0eba3aSLokesh Vutla <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 69*2d0eba3aSLokesh Vutla <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 70*2d0eba3aSLokesh Vutla <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; 71ea8ad1d9SLokesh Vutla 72ea8ad1d9SLokesh Vutla cbass_mcu: interconnect@28380000 { 73ea8ad1d9SLokesh Vutla compatible = "simple-bus"; 74*2d0eba3aSLokesh Vutla #address-cells = <2>; 75*2d0eba3aSLokesh Vutla #size-cells = <2>; 76*2d0eba3aSLokesh Vutla ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 77*2d0eba3aSLokesh Vutla <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */ 78*2d0eba3aSLokesh Vutla <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */ 79*2d0eba3aSLokesh Vutla <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 80*2d0eba3aSLokesh Vutla <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 81*2d0eba3aSLokesh Vutla <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */ 82ea8ad1d9SLokesh Vutla 83ea8ad1d9SLokesh Vutla cbass_wakeup: interconnect@42040000 { 84ea8ad1d9SLokesh Vutla compatible = "simple-bus"; 85ea8ad1d9SLokesh Vutla #address-cells = <1>; 86ea8ad1d9SLokesh Vutla #size-cells = <1>; 87ea8ad1d9SLokesh Vutla /* WKUP Basic peripherals */ 88*2d0eba3aSLokesh Vutla ranges = <0x42040000 0x00 0x42040000 0x03ac2400>; 89ea8ad1d9SLokesh Vutla }; 90ea8ad1d9SLokesh Vutla }; 91ea8ad1d9SLokesh Vutla }; 92ea8ad1d9SLokesh Vutla}; 93ea8ad1d9SLokesh Vutla 94ea8ad1d9SLokesh Vutla/* Now include the peripherals for each bus segments */ 95ea8ad1d9SLokesh Vutla#include "k3-am65-main.dtsi" 96*2d0eba3aSLokesh Vutla#include "k3-am65-mcu.dtsi" 97*2d0eba3aSLokesh Vutla#include "k3-am65-wakeup.dtsi" 98