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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14 |
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d1db5c5b |
| 25-Jan-2024 |
Bjorn Andersson <quic_bjorande@quicinc.com> |
arm64: dts: qcom: sa8540p: Drop gfx.lvl as power-domain for gpucc
[ Upstream commit fd5821a1a83c969ed2dcc72fef885f3a82c1d978 ]
The SA8295P and SA8540P uses an external regulator (max20411), and
gfx
arm64: dts: qcom: sa8540p: Drop gfx.lvl as power-domain for gpucc
[ Upstream commit fd5821a1a83c969ed2dcc72fef885f3a82c1d978 ]
The SA8295P and SA8540P uses an external regulator (max20411), and
gfx.lvl is not provided by rpmh. Drop the power-domains property of the
gpucc node to reflect this.
Fixes: eec51ab2fd6f ("arm64: dts: qcom: sc8280xp: Add GPU related nodes")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-5-7011c2a63037@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38 |
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934a3b4d |
| 02-Jul-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: qcom: minor whitespace cleanup around '='
The DTS code coding style expects exactly one space before and after '='
sign.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.o
arm64: dts: qcom: minor whitespace cleanup around '='
The DTS code coding style expects exactly one space before and after '='
sign.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230702185051.43867-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Revision tags: v6.1.37, v6.1.36, v6.4, v6.1.35 |
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eec51ab2 |
| 14-Jun-2023 |
Bjorn Andersson <bjorn.andersson@linaro.org> |
arm64: dts: qcom: sc8280xp: Add GPU related nodes
Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
SC8280XP.
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Bjorn Ande
arm64: dts: qcom: sc8280xp: Add GPU related nodes
Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
SC8280XP.
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230614142204.2675653-2-quic_bjorande@quicinc.com
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Revision tags: v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19 |
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8a220a62 |
| 09-Jan-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: qcom: align OPP table node name with DT schema
Bindings expect OPP tables to start with "opp-table".
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Kon
arm64: dts: qcom: align OPP table node name with DT schema
Bindings expect OPP tables to start with "opp-table".
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230109112221.102473-2-krzysztof.kozlowski@linaro.org
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Revision tags: v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79 |
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| #
33ba07ff |
| 10-Nov-2022 |
Bjorn Andersson <quic_bjorande@quicinc.com> |
arm64: dts: qcom: sc8280xp: Set up L3 scaling
Add the L3 interconnect path to all CPUs and define the bandwidth
requirements for all opp entries across sc8280xp and sa8540p.
The values are based on
arm64: dts: qcom: sc8280xp: Set up L3 scaling
Add the L3 interconnect path to all CPUs and define the bandwidth
requirements for all opp entries across sc8280xp and sa8540p.
The values are based on the tables reported by the hardware, distributed
such that each value is the largest value, lower than the cluster
frequency.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111032515.3460-9-quic_bjorande@quicinc.com
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Revision tags: v6.0.8, v5.15.78 |
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813e8315 |
| 10-Nov-2022 |
Johan Hovold <johan+linaro@kernel.org> |
arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes
The SC8280XP platform has seven PCIe controllers:
PCIe0 USB4
PCIe1 USB4
PCIe2A 4-lane
PCIe2B 2-lane
PCIe3A 4-lane
PCIe3B 2-lane
PCIe4 1-
arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes
The SC8280XP platform has seven PCIe controllers:
PCIe0 USB4
PCIe1 USB4
PCIe2A 4-lane
PCIe2B 2-lane
PCIe3A 4-lane
PCIe3B 2-lane
PCIe4 1-lane
while SA8540P only has five (PCIe2-4).
Add devicetree nodes for the PCIe2-4 controllers and their PHYs.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110103558.12690-2-johan+linaro@kernel.org
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Revision tags: v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51 |
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| #
519183af |
| 28-Jun-2022 |
Bjorn Andersson <bjorn.andersson@linaro.org> |
arm64: dts: qcom: add SA8540P and ADP
Introduce the Qualcomm SA8540P automotive platform and the SA8295P ADP
development board.
The SA8540P and SC8280XP are fairly similar, so the SA8540P is built
arm64: dts: qcom: add SA8540P and ADP
Introduce the Qualcomm SA8540P automotive platform and the SA8295P ADP
development board.
The SA8540P and SC8280XP are fairly similar, so the SA8540P is built
ontop of the SC8280XP dtsi to reduce duplication. As more advanced
features are integrated this might be re-evaluated.
This initial contribution supports SMP, CPUFreq, cluster idle, UFS, RPMh
regulators, debug UART, PMICs, remoteprocs (NSPs crashes shortly after
booting) and USB.
The SA8295P ADP contains four PM8450 PMICs, which according to their
revid are compatible with PM8150. They are defined within the ADP for
now, to avoid creating additional .dtsi files for PM8150 with just
addresses changed - and to allow using the labels from the schematics.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20220629041438.1352536-6-bjorn.andersson@linaro.org
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