1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2bf027ca1STony Lindgren /*
3bf027ca1STony Lindgren * Interface for functions that need to be run in internal SRAM
4bf027ca1STony Lindgren */
5bf027ca1STony Lindgren
6bf027ca1STony Lindgren #ifndef __ASSEMBLY__
7bf027ca1STony Lindgren
8bf027ca1STony Lindgren extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9bf027ca1STony Lindgren u32 base_cs, u32 force_unlock);
10bf027ca1STony Lindgren extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
11bf027ca1STony Lindgren u32 mem_type);
12bf027ca1STony Lindgren extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
13bf027ca1STony Lindgren
14bf027ca1STony Lindgren extern void omap3_sram_restore_context(void);
15bf027ca1STony Lindgren
16*11237651SArnd Bergmann extern int __init omap_sram_init(void);
17*11237651SArnd Bergmann
18*11237651SArnd Bergmann extern void *omap_sram_push(void *funcp, unsigned long size);
19*11237651SArnd Bergmann
20bf027ca1STony Lindgren extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
21bf027ca1STony Lindgren u32 base_cs, u32 force_unlock);
22bf027ca1STony Lindgren extern unsigned long omap242x_sram_ddr_init_sz;
23bf027ca1STony Lindgren
24bf027ca1STony Lindgren extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
25bf027ca1STony Lindgren int bypass);
26bf027ca1STony Lindgren extern unsigned long omap242x_sram_set_prcm_sz;
27bf027ca1STony Lindgren
28bf027ca1STony Lindgren extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
29bf027ca1STony Lindgren u32 mem_type);
30bf027ca1STony Lindgren extern unsigned long omap242x_sram_reprogram_sdrc_sz;
31bf027ca1STony Lindgren
32bf027ca1STony Lindgren
33bf027ca1STony Lindgren extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
34bf027ca1STony Lindgren u32 base_cs, u32 force_unlock);
35bf027ca1STony Lindgren extern unsigned long omap243x_sram_ddr_init_sz;
36bf027ca1STony Lindgren
37bf027ca1STony Lindgren extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
38bf027ca1STony Lindgren int bypass);
39bf027ca1STony Lindgren extern unsigned long omap243x_sram_set_prcm_sz;
40bf027ca1STony Lindgren
41bf027ca1STony Lindgren extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
42bf027ca1STony Lindgren u32 mem_type);
43bf027ca1STony Lindgren extern unsigned long omap243x_sram_reprogram_sdrc_sz;
44bf027ca1STony Lindgren
45bf027ca1STony Lindgren #ifdef CONFIG_PM
46bf027ca1STony Lindgren extern void omap_push_sram_idle(void);
47bf027ca1STony Lindgren #else
omap_push_sram_idle(void)48bf027ca1STony Lindgren static inline void omap_push_sram_idle(void) {}
49bf027ca1STony Lindgren #endif /* CONFIG_PM */
50bf027ca1STony Lindgren
51bf027ca1STony Lindgren #endif /* __ASSEMBLY__ */
52bf027ca1STony Lindgren
53bf027ca1STony Lindgren /*
54bf027ca1STony Lindgren * OMAP2+: define the SRAM PA addresses.
55bf027ca1STony Lindgren * Used by the SRAM management code and the idle sleep code.
56bf027ca1STony Lindgren */
57bf027ca1STony Lindgren #define OMAP2_SRAM_PA 0x40200000
58bf027ca1STony Lindgren #define OMAP3_SRAM_PA 0x40200000
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