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/openbmc/openbmc/meta-hpe/meta-gxp/conf/machine/include/
H A Dgxp.inc19 UBOOT_ENTRYPOINT ?= "0x40100000"
20 UBOOT_LOADADDRESS ?= "0x40100000"
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Dcorstone1000-mps3.dts18 reg = <0x40100000 0x10000>;
27 reg = <0x40200000 0x100000>;
H A Dcorstone1000-fvp.dts18 reg = <0x40100000 0x10000>;
34 reg = <0x40300000 0x1000>;
44 reg = <0x50000000 0x10000>;
/openbmc/u-boot/configs/
H A Dls1012a2g5rdb_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x40100000
17 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250…
H A Dls1012afrwy_qspi_SECURE_BOOT_defconfig3 CONFIG_SYS_TEXT_BASE=0x40100000
17 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250…
H A Dls1012afrdm_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x40100000
16 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250…
H A Dls1012afrwy_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x40100000
16 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250…
H A Dls1012ardb_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x40100000
17 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250…
H A Dls1012ardb_qspi_SECURE_BOOT_defconfig3 CONFIG_SYS_TEXT_BASE=0x40100000
18 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250…
H A Dls1043aqds_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x40100000
14 …RGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=spi0.0:1m(uboot…
28 CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
H A Dls1046aqds_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x40100000
13 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550…
H A Dls1012aqds_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x40100000
17 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250…
40 CONFIG_ENV_SPI_BUS=0
44 CONFIG_ENV_SPI_MODE=0x03
54 CONFIG_SF_DEFAULT_MODE=0
H A Dls1021aqds_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x40100000
H A Dls1021atwr_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x40100000
H A Dls1046ardb_qspi_SECURE_BOOT_defconfig3 CONFIG_SYS_TEXT_BASE=0x40100000
15 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550…
H A Dls1046ardb_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x40100000
14 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550…
/openbmc/qemu/tests/migration/
H A Dmigration-test.h25 #define PPC_H_PUT_TERM_CHAR 0x58
28 #define ARM_TEST_MEM_START (0x40000000 + 1 * 1024 * 1024)
29 #define ARM_TEST_MEM_END (0x40000000 + 100 * 1024 * 1024)
30 #define ARM_MACH_VIRT_UART 0x09000000
31 /* AArch64 kernel load address is 0x40080000, and the test memory starts at
32 * 0x40100000. So the maximum allowable kernel size is 512KB.
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dsmsc,lan91c111.yaml57 reg = <0x40100000 0x10000>;
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
H A Domap4-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dxlnx,xps-timebase-wdt.yaml47 enum: [0, 1]
62 reg = <0x40100000 0x1000>;
65 xlnx,wdt-enable-once = <0x0>;
66 xlnx,wdt-interval = <0x1b>;
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dregs-uart.h9 #define FFUART_BASE 0x40100000
10 #define BTUART_BASE 0x40200000
11 #define STUART_BASE 0x40700000
12 #define HWUART_BASE 0x41600000
43 #define IER_RAVIE (1 << 0)
50 #define IIR_IP (1 << 0)
56 #define FCR_TRFIFOE (1 << 0)
57 #define FCR_ITL_1 0
69 #define LCR_WLS0 (1 << 0)
78 #define LSR_DR (1 << 0)
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa2xx.dtsi64 reg = <0x40d00000 0xd0>;
69 #address-cells = <0x1>;
70 #size-cells = <0x1>;
71 reg = <0x40e00000 0x10000>;
73 #gpio-cells = <0x2>;
77 #interrupt-cells = <0x2>;
81 reg = <0x40e00000 0x4>;
85 reg = <0x40e00004 0x4>;
89 reg = <0x40e00008 0x4>;
92 reg = <0x40e0000c 0x4>;
[all …]
/openbmc/u-boot/include/configs/
H A Dls1046ardb.h21 #define SPD_EEPROM_ADDRESS 0x51
22 #define CONFIG_SYS_SPD_BUS_NUM 0
26 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
41 #define CONFIG_SYS_UBOOT_BASE 0x40100000
42 #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
54 #define CONFIG_SYS_NAND_BASE 0x7e800000
57 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
73 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
74 FTIM0_NAND_TWP(0x18) | \
75 FTIM0_NAND_TWCHT(0x7) | \
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p.dtsi184 linux,pci-domain = <0>;
201 reg = <0x0 0x01c10000 0x0 0x3000>,
202 <0x0 0x40000000 0x0 0xf1d>,
203 <0x0 0x40000f20 0x0 0xa8>,
204 <0x0 0x40001000 0x0 0x1000>,
205 <0x0 0x40100000 0x0 0x100000>;
208 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
209 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1d00000>;
216 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
217 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
[all …]

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