183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2dd02936fSMingkai Hu /* 3dd02936fSMingkai Hu * Copyright 2016 Freescale Semiconductor 4dd02936fSMingkai Hu */ 5dd02936fSMingkai Hu 6dd02936fSMingkai Hu #ifndef __LS1046ARDB_H__ 7dd02936fSMingkai Hu #define __LS1046ARDB_H__ 8dd02936fSMingkai Hu 9dd02936fSMingkai Hu #include "ls1046a_common.h" 10dd02936fSMingkai Hu 11dd02936fSMingkai Hu #define CONFIG_SYS_CLK_FREQ 100000000 12dd02936fSMingkai Hu #define CONFIG_DDR_CLK_FREQ 100000000 13dd02936fSMingkai Hu 14dd02936fSMingkai Hu #define CONFIG_LAYERSCAPE_NS_ACCESS 15dd02936fSMingkai Hu 16dd02936fSMingkai Hu #define CONFIG_DIMM_SLOTS_PER_CTLR 1 17dd02936fSMingkai Hu /* Physical Memory Map */ 18dd02936fSMingkai Hu #define CONFIG_CHIP_SELECTS_PER_CTRL 4 19dd02936fSMingkai Hu 20dd02936fSMingkai Hu #define CONFIG_DDR_SPD 21dd02936fSMingkai Hu #define SPD_EEPROM_ADDRESS 0x51 22dd02936fSMingkai Hu #define CONFIG_SYS_SPD_BUS_NUM 0 23dd02936fSMingkai Hu 24dd02936fSMingkai Hu #define CONFIG_DDR_ECC 25dd02936fSMingkai Hu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 26dd02936fSMingkai Hu #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 27dd02936fSMingkai Hu 28dd02936fSMingkai Hu #ifdef CONFIG_SD_BOOT 29038b965cSYork Sun #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg 30dd02936fSMingkai Hu #ifdef CONFIG_EMMC_BOOT 31dd02936fSMingkai Hu #define CONFIG_SYS_FSL_PBL_RCW \ 32dd02936fSMingkai Hu board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg 33dd02936fSMingkai Hu #else 34dd02936fSMingkai Hu #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg 35dd02936fSMingkai Hu #endif 36038b965cSYork Sun #elif defined(CONFIG_QSPI_BOOT) 37038b965cSYork Sun #define CONFIG_SYS_FSL_PBL_RCW \ 38038b965cSYork Sun board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg 39038b965cSYork Sun #define CONFIG_SYS_FSL_PBL_PBI \ 40038b965cSYork Sun board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg 41038b965cSYork Sun #define CONFIG_SYS_UBOOT_BASE 0x40100000 42038b965cSYork Sun #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 43dd02936fSMingkai Hu #endif 44dd02936fSMingkai Hu 45a52ff334SSumit Garg #ifndef SPL_NO_IFC 46dd02936fSMingkai Hu /* IFC */ 47dd02936fSMingkai Hu #define CONFIG_FSL_IFC 48dd02936fSMingkai Hu /* 49dd02936fSMingkai Hu * NAND Flash Definitions 50dd02936fSMingkai Hu */ 51dd02936fSMingkai Hu #define CONFIG_NAND_FSL_IFC 52a52ff334SSumit Garg #endif 53dd02936fSMingkai Hu 54dd02936fSMingkai Hu #define CONFIG_SYS_NAND_BASE 0x7e800000 55dd02936fSMingkai Hu #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 56dd02936fSMingkai Hu 57dd02936fSMingkai Hu #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 58dd02936fSMingkai Hu #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 59dd02936fSMingkai Hu | CSPR_PORT_SIZE_8 \ 60dd02936fSMingkai Hu | CSPR_MSEL_NAND \ 61dd02936fSMingkai Hu | CSPR_V) 62dd02936fSMingkai Hu #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 63dd02936fSMingkai Hu #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 64dd02936fSMingkai Hu | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 65dd02936fSMingkai Hu | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 66dd02936fSMingkai Hu | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 67dd02936fSMingkai Hu | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 68dd02936fSMingkai Hu | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 69dd02936fSMingkai Hu | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 70dd02936fSMingkai Hu 71dd02936fSMingkai Hu #define CONFIG_SYS_NAND_ONFI_DETECTION 72dd02936fSMingkai Hu 73dd02936fSMingkai Hu #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 74dd02936fSMingkai Hu FTIM0_NAND_TWP(0x18) | \ 75dd02936fSMingkai Hu FTIM0_NAND_TWCHT(0x7) | \ 76dd02936fSMingkai Hu FTIM0_NAND_TWH(0xa)) 77dd02936fSMingkai Hu #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 78dd02936fSMingkai Hu FTIM1_NAND_TWBE(0x39) | \ 79dd02936fSMingkai Hu FTIM1_NAND_TRR(0xe) | \ 80dd02936fSMingkai Hu FTIM1_NAND_TRP(0x18)) 81dd02936fSMingkai Hu #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 82dd02936fSMingkai Hu FTIM2_NAND_TREH(0xa) | \ 83dd02936fSMingkai Hu FTIM2_NAND_TWHRE(0x1e)) 84dd02936fSMingkai Hu #define CONFIG_SYS_NAND_FTIM3 0x0 85dd02936fSMingkai Hu 86dd02936fSMingkai Hu #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 87dd02936fSMingkai Hu #define CONFIG_SYS_MAX_NAND_DEVICE 1 88dd02936fSMingkai Hu #define CONFIG_MTD_NAND_VERIFY_WRITE 89dd02936fSMingkai Hu 90dd02936fSMingkai Hu #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 91dd02936fSMingkai Hu 92dd02936fSMingkai Hu /* 93dd02936fSMingkai Hu * CPLD 94dd02936fSMingkai Hu */ 95dd02936fSMingkai Hu #define CONFIG_SYS_CPLD_BASE 0x7fb00000 96dd02936fSMingkai Hu #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 97dd02936fSMingkai Hu 98dd02936fSMingkai Hu #define CONFIG_SYS_CPLD_CSPR_EXT (0x0) 99dd02936fSMingkai Hu #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 100dd02936fSMingkai Hu CSPR_PORT_SIZE_8 | \ 101dd02936fSMingkai Hu CSPR_MSEL_GPCM | \ 102dd02936fSMingkai Hu CSPR_V) 103dd02936fSMingkai Hu #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 104dd02936fSMingkai Hu #define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) 105dd02936fSMingkai Hu 106dd02936fSMingkai Hu /* CPLD Timing parameters for IFC GPCM */ 107dd02936fSMingkai Hu #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 108dd02936fSMingkai Hu FTIM0_GPCM_TEADC(0x0e) | \ 109dd02936fSMingkai Hu FTIM0_GPCM_TEAHC(0x0e)) 110dd02936fSMingkai Hu #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 111dd02936fSMingkai Hu FTIM1_GPCM_TRAD(0x3f)) 112dd02936fSMingkai Hu #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 113dd02936fSMingkai Hu FTIM2_GPCM_TCH(0xf) | \ 114dd02936fSMingkai Hu FTIM2_GPCM_TWP(0x3E)) 115dd02936fSMingkai Hu #define CONFIG_SYS_CPLD_FTIM3 0x0 116dd02936fSMingkai Hu 117dd02936fSMingkai Hu /* IFC Timing Params */ 118dd02936fSMingkai Hu #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 119dd02936fSMingkai Hu #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 120dd02936fSMingkai Hu #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 121dd02936fSMingkai Hu #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 122dd02936fSMingkai Hu #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 123dd02936fSMingkai Hu #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 124dd02936fSMingkai Hu #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 125dd02936fSMingkai Hu #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 126dd02936fSMingkai Hu 127dd02936fSMingkai Hu #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT 128dd02936fSMingkai Hu #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR 129dd02936fSMingkai Hu #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK 130dd02936fSMingkai Hu #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR 131dd02936fSMingkai Hu #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 132dd02936fSMingkai Hu #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 133dd02936fSMingkai Hu #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 134dd02936fSMingkai Hu #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 135dd02936fSMingkai Hu 136dd02936fSMingkai Hu /* EEPROM */ 137dd02936fSMingkai Hu #define CONFIG_ID_EEPROM 138dd02936fSMingkai Hu #define CONFIG_SYS_I2C_EEPROM_NXID 139dd02936fSMingkai Hu #define CONFIG_SYS_EEPROM_BUS_NUM 0 140dd02936fSMingkai Hu #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 141dd02936fSMingkai Hu #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 142dd02936fSMingkai Hu #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 143dd02936fSMingkai Hu #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 144dd02936fSMingkai Hu #define I2C_RETIMER_ADDR 0x18 145dd02936fSMingkai Hu 146dccef2ecSHou Zhiqiang /* PMIC */ 147dccef2ecSHou Zhiqiang #define CONFIG_POWER 148dccef2ecSHou Zhiqiang #ifdef CONFIG_POWER 149dccef2ecSHou Zhiqiang #define CONFIG_POWER_I2C 150dccef2ecSHou Zhiqiang #endif 151dccef2ecSHou Zhiqiang 152dd02936fSMingkai Hu /* 153dd02936fSMingkai Hu * Environment 154dd02936fSMingkai Hu */ 155a52ff334SSumit Garg #ifndef SPL_NO_ENV 156dd02936fSMingkai Hu #define CONFIG_ENV_OVERWRITE 157a52ff334SSumit Garg #endif 158dd02936fSMingkai Hu 159*8e156bb1SRajesh Bhagat #ifdef CONFIG_TFABOOT 160*8e156bb1SRajesh Bhagat #define CONFIG_SYS_MMC_ENV_DEV 0 161*8e156bb1SRajesh Bhagat 162*8e156bb1SRajesh Bhagat #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 163*8e156bb1SRajesh Bhagat #define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ 164*8e156bb1SRajesh Bhagat #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ 165*8e156bb1SRajesh Bhagat #else 166dd02936fSMingkai Hu #if defined(CONFIG_SD_BOOT) 167dd02936fSMingkai Hu #define CONFIG_SYS_MMC_ENV_DEV 0 1688104deb2SAlison Wang #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 169dd02936fSMingkai Hu #define CONFIG_ENV_SIZE 0x2000 170dd02936fSMingkai Hu #else 171dd02936fSMingkai Hu #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 1728104deb2SAlison Wang #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 173dd02936fSMingkai Hu #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ 174dd02936fSMingkai Hu #endif 175*8e156bb1SRajesh Bhagat #endif 176dd02936fSMingkai Hu 17799b47c25SYork Sun #define AQR105_IRQ_MASK 0x80000000 178dd02936fSMingkai Hu /* FMan */ 179a52ff334SSumit Garg #ifndef SPL_NO_FMAN 18099b47c25SYork Sun 18199b47c25SYork Sun #ifdef CONFIG_NET 18299b47c25SYork Sun #define CONFIG_PHY_REALTEK 18399b47c25SYork Sun #endif 18499b47c25SYork Sun 185dd02936fSMingkai Hu #ifdef CONFIG_SYS_DPAA_FMAN 186dd02936fSMingkai Hu #define CONFIG_FMAN_ENET 187dd02936fSMingkai Hu #define RGMII_PHY1_ADDR 0x1 188dd02936fSMingkai Hu #define RGMII_PHY2_ADDR 0x2 189dd02936fSMingkai Hu 190dd02936fSMingkai Hu #define SGMII_PHY1_ADDR 0x3 191dd02936fSMingkai Hu #define SGMII_PHY2_ADDR 0x4 192dd02936fSMingkai Hu 193dd02936fSMingkai Hu #define FM1_10GEC1_PHY_ADDR 0x0 194dd02936fSMingkai Hu 1954ace3040SPrabhakar Kushwaha #define FDT_SEQ_MACADDR_FROM_ENV 1964ace3040SPrabhakar Kushwaha 197dd02936fSMingkai Hu #define CONFIG_ETHPRIME "FM1@DTSEC3" 198dd02936fSMingkai Hu #endif 19999b47c25SYork Sun 200a52ff334SSumit Garg #endif 201dd02936fSMingkai Hu 202dd02936fSMingkai Hu /* QSPI device */ 203a52ff334SSumit Garg #ifndef SPL_NO_QSPI 204dd02936fSMingkai Hu #ifdef CONFIG_FSL_QSPI 205dd02936fSMingkai Hu #define CONFIG_SPI_FLASH_SPANSION 206dd02936fSMingkai Hu #define FSL_QSPI_FLASH_SIZE (1 << 26) 207dd02936fSMingkai Hu #define FSL_QSPI_FLASH_NUM 2 208dd02936fSMingkai Hu #endif 209a52ff334SSumit Garg #endif 210dd02936fSMingkai Hu 211a52ff334SSumit Garg #ifndef SPL_NO_MISC 2128de227eeSQianyu Gong #undef CONFIG_BOOTCOMMAND 213*8e156bb1SRajesh Bhagat #ifdef CONFIG_TFABOOT 214*8e156bb1SRajesh Bhagat #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 215*8e156bb1SRajesh Bhagat "env exists secureboot && esbc_halt;;" 216*8e156bb1SRajesh Bhagat #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ 217*8e156bb1SRajesh Bhagat "env exists secureboot && esbc_halt;" 218*8e156bb1SRajesh Bhagat #else 219aab2ef9aSShengzhou Liu #if defined(CONFIG_QSPI_BOOT) 2209b457cc6SVinitha Pillai-B57223 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 2219b457cc6SVinitha Pillai-B57223 "env exists secureboot && esbc_halt;;" 222aab2ef9aSShengzhou Liu #elif defined(CONFIG_SD_BOOT) 2239b457cc6SVinitha Pillai-B57223 #define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ 2249b457cc6SVinitha Pillai-B57223 "env exists secureboot && esbc_halt;" 225aab2ef9aSShengzhou Liu #endif 226a52ff334SSumit Garg #endif 227*8e156bb1SRajesh Bhagat #endif 228dd02936fSMingkai Hu 229f7244f2cSVinitha Pillai-B57223 #include <asm/fsl_secure_boot.h> 230f7244f2cSVinitha Pillai-B57223 231dd02936fSMingkai Hu #endif /* __LS1046ARDB_H__ */ 232