Lines Matching +full:0 +full:x40100000
21 #define SPD_EEPROM_ADDRESS 0x51
22 #define CONFIG_SYS_SPD_BUS_NUM 0
26 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
41 #define CONFIG_SYS_UBOOT_BASE 0x40100000
42 #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
54 #define CONFIG_SYS_NAND_BASE 0x7e800000
57 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
73 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
74 FTIM0_NAND_TWP(0x18) | \
75 FTIM0_NAND_TWCHT(0x7) | \
76 FTIM0_NAND_TWH(0xa))
77 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
78 FTIM1_NAND_TWBE(0x39) | \
79 FTIM1_NAND_TRR(0xe) | \
80 FTIM1_NAND_TRP(0x18))
81 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
82 FTIM2_NAND_TREH(0xa) | \
83 FTIM2_NAND_TWHRE(0x1e))
84 #define CONFIG_SYS_NAND_FTIM3 0x0
95 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
98 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
107 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
108 FTIM0_GPCM_TEADC(0x0e) | \
109 FTIM0_GPCM_TEAHC(0x0e))
110 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
111 FTIM1_GPCM_TRAD(0x3f))
112 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
113 FTIM2_GPCM_TCH(0xf) | \
114 FTIM2_GPCM_TWP(0x3E))
115 #define CONFIG_SYS_CPLD_FTIM3 0x0
139 #define CONFIG_SYS_EEPROM_BUS_NUM 0
140 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
144 #define I2C_RETIMER_ADDR 0x18
160 #define CONFIG_SYS_MMC_ENV_DEV 0
162 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
163 #define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
164 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
167 #define CONFIG_SYS_MMC_ENV_DEV 0
169 #define CONFIG_ENV_SIZE 0x2000
171 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
172 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
173 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
177 #define AQR105_IRQ_MASK 0x80000000
187 #define RGMII_PHY1_ADDR 0x1
188 #define RGMII_PHY2_ADDR 0x2
190 #define SGMII_PHY1_ADDR 0x3
191 #define SGMII_PHY2_ADDR 0x4
193 #define FM1_10GEC1_PHY_ADDR 0x0