/openbmc/u-boot/arch/arm/mach-stm32mp/include/mach/ |
H A D | stm32.h | 13 #define STM32_RCC_BASE 0x50000000 14 #define STM32_PWR_BASE 0x50001000 15 #define STM32_DBGMCU_BASE 0x50081000 16 #define STM32_BSEC_BASE 0x5C005000 17 #define STM32_TZC_BASE 0x5C006000 18 #define STM32_ETZPC_BASE 0x5C007000 19 #define STM32_TAMP_BASE 0x5C00A000 23 #define STM32_USART1_BASE 0x5C000000 24 #define STM32_USART2_BASE 0x4000E000 25 #define STM32_USART3_BASE 0x4000F000 [all …]
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/openbmc/linux/Documentation/devicetree/bindings/serial/ |
H A D | st,stm32-uart.yaml | 115 reg = <0x40011000 0x400>; 117 clocks = <&rcc 0 164>; 118 dmas = <&dma2 2 4 0x414 0x0>, 119 <&dma2 7 4 0x414 0x0>;
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/openbmc/u-boot/arch/arm/dts/ |
H A D | stm32h743.dtsi | 51 #clock-cells = <0>; 57 #clock-cells = <0>; 63 #clock-cells = <0>; 65 clock-frequency = <0>; 74 reg = <0x58024400 0x400>; 81 reg = <0x40011000 0x400>; 89 reg = <0x40004400 0x400>; 97 reg = <0x40000c00 0x400>; 104 reg = <0x58024800 0x400>; 109 reg = <0x52004000 0x1000>; [all …]
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H A D | stm32f746.dtsi | 56 #clock-cells = <0>; 58 clock-frequency = <0>; 66 reg = <0x40028000 0x8000>; 68 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>, 69 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>, 70 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>; 81 reg = <0xA0000000 0x1000>; 82 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>; 89 #size-cells = <0>; 90 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; [all …]
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H A D | stm32f429.dtsi | 52 #clock-cells = <0>; 54 clock-frequency = <0>; 58 #clock-cells = <0>; 64 #clock-cells = <0>; 70 #clock-cells = <0>; 72 clock-frequency = <0>; 79 reg = <0x40000000 0x400>; 81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; 87 #size-cells = <0>; 89 reg = <0x40000000 0x400>; [all …]
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H A D | stm32mp157c.dtsi | 16 #size-cells = <0>; 18 cpu0: cpu@0 { 21 reg = <0>; 34 cpu_off = <0x84000002>; 35 cpu_on = <0x84000003>; 64 reg = <0xa0021000 0x1000>, 65 <0xa0022000 0x2000>; 79 #clock-cells = <0>; 85 #clock-cells = <0>; 91 #clock-cells = <0>; [all …]
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/openbmc/qemu/hw/arm/ |
H A D | stm32f100_soc.c | 39 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400, 40 0x40004800 }; 41 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 }; 53 for (i = 0; i < STM_NUM_USARTS; i++) { in stm32f100_soc_initfn() 58 for (i = 0; i < STM_NUM_SPIS; i++) { in stm32f100_soc_initfn() 62 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in stm32f100_soc_initfn() 63 s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); in stm32f100_soc_initfn() 101 * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 in stm32f100_soc_realize() 106 "STM32F100.flash.alias", &s->flash, 0, FLASH_SIZE); in stm32f100_soc_realize() 108 memory_region_add_subregion(system_memory, 0, &s->flash_alias); in stm32f100_soc_realize() [all …]
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H A D | stm32f205_soc.c | 36 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400, 37 0x40000800, 0x40000C00 }; 38 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, 39 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; 40 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100, 41 0x40012200 }; 42 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800, 43 0x40003C00 }; 59 for (i = 0; i < STM_NUM_USARTS; i++) { in stm32f205_soc_initfn() 64 for (i = 0; i < STM_NUM_TIMERS; i++) { in stm32f205_soc_initfn() [all …]
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H A D | msf2-soc.c | 35 #define MSF2_TIMER_BASE 0x40004000 36 #define MSF2_SYSREG_BASE 0x40038000 37 #define MSF2_EMAC_BASE 0x40041000 39 #define ENVM_BASE_ADDRESS 0x60000000 41 #define SRAM_BASE_ADDRESS 0x20000000 54 static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 }; 55 static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 }; 72 for (i = 0; i < MSF2_NUM_SPIS; i++) { in m2sxxx_soc_initfn() 78 s->m3clk = qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0); in m2sxxx_soc_initfn() 79 s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); in m2sxxx_soc_initfn() [all …]
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H A D | stm32f405_soc.c | 33 #define RCC_ADDR 0x40023800 34 #define SYSCFG_ADD 0x40013800 35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, 36 0x40004C00, 0x40005000, 0x40011400, 37 0x40007800, 0x40007C00 }; 39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, 40 0x40000800, 0x40000C00 }; 41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200, 42 0x40012300, 0x40012400, 0x40012500 }; 43 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, [all …]
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H A D | mps2.c | 130 memory_region_init_alias(mr, NULL, name, orig, 0, in make_ram_alias() 166 * 0x21000000 .. 0x21ffffff : PSRAM (16MB) in mps2_common_init() 168 * 0x00000000 .. 0x003fffff : ZBT SSRAM1 in mps2_common_init() 169 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 in mps2_common_init() 170 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 in mps2_common_init() 171 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 in mps2_common_init() 173 * 0x01000000 .. 0x01003fff : block RAM (16K) in mps2_common_init() 174 * 0x01004000 .. 0x01007fff : mirror of above in mps2_common_init() 175 * 0x01008000 .. 0x0100bfff : mirror of above in mps2_common_init() 176 * 0x0100c000 .. 0x0100ffff : mirror of above in mps2_common_init() [all …]
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/openbmc/linux/arch/arm/boot/dts/st/ |
H A D | stm32f746.dtsi | 53 #clock-cells = <0>; 55 clock-frequency = <0>; 59 #clock-cells = <0>; 65 #clock-cells = <0>; 71 #clock-cells = <0>; 80 #size-cells = <0>; 82 reg = <0x40000000 0x400>; 83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; 102 #size-cells = <0>; 104 reg = <0x40000400 0x400>; [all …]
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H A D | stm32f429.dtsi | 58 #clock-cells = <0>; 60 clock-frequency = <0>; 64 #clock-cells = <0>; 70 #clock-cells = <0>; 76 #clock-cells = <0>; 78 clock-frequency = <0>; 85 reg = <0x1fff7800 0x400>; 89 reg = <0x22c 0x2>; 92 reg = <0x22e 0x2>; 98 #size-cells = <0>; [all …]
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H A D | stm32h743.dtsi | 54 #clock-cells = <0>; 56 clock-frequency = <0>; 60 #clock-cells = <0>; 66 #clock-cells = <0>; 68 clock-frequency = <0>; 75 reg = <0x40000c00 0x400>; 82 #size-cells = <0>; 84 reg = <0x40002400 0x400>; 95 trigger@0 { 97 reg = <0>; [all …]
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H A D | stm32mp131.dtsi | 16 #size-cells = <0>; 18 cpu0: cpu@0 { 21 reg = <0>; 43 #size-cells = <0>; 44 linaro,optee-channel-id = <0>; 47 reg = <0x14>; 52 reg = <0x16>; 57 reg = <0x17>; 61 #size-cells = <0>; 63 scmi_reg11: regulator@0 { [all …]
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H A D | stm32mp151.dtsi | 16 #size-cells = <0>; 18 cpu0: cpu@0 { 22 reg = <0>; 42 reg = <0xa0021000 0x1000>, 43 <0xa0022000 0x2000>; 58 #clock-cells = <0>; 64 #clock-cells = <0>; 70 #clock-cells = <0>; 76 #clock-cells = <0>; 82 #clock-cells = <0>; [all …]
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/openbmc/u-boot/test/lib/ |
H A D | lmb.c | 20 ut_asserteq(lmb->memory.region[0].base, ram_base); in check_lmb() 21 ut_asserteq(lmb->memory.region[0].size, ram_size); in check_lmb() 25 if (num_reserved > 0) { in check_lmb() 26 ut_asserteq(lmb->reserved.region[0].base, base1); in check_lmb() 27 ut_asserteq(lmb->reserved.region[0].size, size1); in check_lmb() 37 return 0; in check_lmb() 56 const phys_addr_t alloc_64k_end = alloc_64k_addr + 0x10000; in test_multi_alloc() 63 ut_assert(ram_end == 0 || ram_end > ram); in test_multi_alloc() 73 ut_asserteq(ret, 0); in test_multi_alloc() 77 ut_asserteq(ret, 0); in test_multi_alloc() [all …]
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/openbmc/linux/arch/arm/ |
H A D | Kconfig.debug | 149 0x80000000 | 0xf0000000 | UART0 150 0x80004000 | 0xf0004000 | UART1 151 0x80008000 | 0xf0008000 | UART2 152 0x8000c000 | 0xf000c000 | UART3 153 0x80010000 | 0xf0010000 | UART4 154 0x80014000 | 0xf0014000 | UART5 155 0x80018000 | 0xf0018000 | UART6 156 0x8001c000 | 0xf001c000 | UART7 157 0x80020000 | 0xf0020000 | UART8 158 0x80024000 | 0xf0024000 | UART9 [all …]
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