14549e789STom Rini /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 22514c2d0SPatrick Delaunay /* 32514c2d0SPatrick Delaunay * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 42514c2d0SPatrick Delaunay */ 52514c2d0SPatrick Delaunay 62514c2d0SPatrick Delaunay #ifndef _MACH_STM32_H_ 72514c2d0SPatrick Delaunay #define _MACH_STM32_H_ 82514c2d0SPatrick Delaunay 92514c2d0SPatrick Delaunay /* 102514c2d0SPatrick Delaunay * Peripheral memory map 112514c2d0SPatrick Delaunay * only address used before device tree parsing 122514c2d0SPatrick Delaunay */ 132514c2d0SPatrick Delaunay #define STM32_RCC_BASE 0x50000000 142514c2d0SPatrick Delaunay #define STM32_PWR_BASE 0x50001000 152514c2d0SPatrick Delaunay #define STM32_DBGMCU_BASE 0x50081000 16*19f58992SPatrick Delaunay #define STM32_BSEC_BASE 0x5C005000 172514c2d0SPatrick Delaunay #define STM32_TZC_BASE 0x5C006000 182514c2d0SPatrick Delaunay #define STM32_ETZPC_BASE 0x5C007000 192514c2d0SPatrick Delaunay #define STM32_TAMP_BASE 0x5C00A000 202514c2d0SPatrick Delaunay 21320d2663SPatrick Delaunay #ifdef CONFIG_DEBUG_UART_BASE 22320d2663SPatrick Delaunay /* hardcoded value can be only used for DEBUG UART */ 23320d2663SPatrick Delaunay #define STM32_USART1_BASE 0x5C000000 24320d2663SPatrick Delaunay #define STM32_USART2_BASE 0x4000E000 25320d2663SPatrick Delaunay #define STM32_USART3_BASE 0x4000F000 26320d2663SPatrick Delaunay #define STM32_UART4_BASE 0x40010000 27320d2663SPatrick Delaunay #define STM32_UART5_BASE 0x40011000 28320d2663SPatrick Delaunay #define STM32_USART6_BASE 0x44003000 29320d2663SPatrick Delaunay #define STM32_UART7_BASE 0x40018000 30320d2663SPatrick Delaunay #define STM32_UART8_BASE 0x40019000 31320d2663SPatrick Delaunay #endif 32320d2663SPatrick Delaunay 332514c2d0SPatrick Delaunay #define STM32_SYSRAM_BASE 0x2FFC0000 342514c2d0SPatrick Delaunay #define STM32_SYSRAM_SIZE SZ_256K 352514c2d0SPatrick Delaunay 362514c2d0SPatrick Delaunay #define STM32_DDR_BASE 0xC0000000 372514c2d0SPatrick Delaunay #define STM32_DDR_SIZE SZ_1G 382514c2d0SPatrick Delaunay 3908772f6eSPatrick Delaunay #ifndef __ASSEMBLY__ 40e16750ffSPatrick Delaunay /* enumerated used to identify the SYSCON driver instance */ 41e16750ffSPatrick Delaunay enum { 42e16750ffSPatrick Delaunay STM32MP_SYSCON_UNKNOWN, 43e16750ffSPatrick Delaunay STM32MP_SYSCON_STGEN, 44e8b85e81SPatrick Delaunay STM32MP_SYSCON_PWR, 45e16750ffSPatrick Delaunay }; 4608772f6eSPatrick Delaunay 4708772f6eSPatrick Delaunay /* 4808772f6eSPatrick Delaunay * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT 4908772f6eSPatrick Delaunay * - boot device = bit 8:4 5008772f6eSPatrick Delaunay * - boot instance = bit 3:0 5108772f6eSPatrick Delaunay */ 5208772f6eSPatrick Delaunay #define BOOT_TYPE_MASK 0xF0 5308772f6eSPatrick Delaunay #define BOOT_TYPE_SHIFT 4 5408772f6eSPatrick Delaunay #define BOOT_INSTANCE_MASK 0x0F 5508772f6eSPatrick Delaunay #define BOOT_INSTANCE_SHIFT 0 5608772f6eSPatrick Delaunay 5708772f6eSPatrick Delaunay enum boot_device { 5808772f6eSPatrick Delaunay BOOT_FLASH_SD = 0x10, 5908772f6eSPatrick Delaunay BOOT_FLASH_SD_1 = 0x11, 6008772f6eSPatrick Delaunay BOOT_FLASH_SD_2 = 0x12, 6108772f6eSPatrick Delaunay BOOT_FLASH_SD_3 = 0x13, 6208772f6eSPatrick Delaunay 6308772f6eSPatrick Delaunay BOOT_FLASH_EMMC = 0x20, 6408772f6eSPatrick Delaunay BOOT_FLASH_EMMC_1 = 0x21, 6508772f6eSPatrick Delaunay BOOT_FLASH_EMMC_2 = 0x22, 6608772f6eSPatrick Delaunay BOOT_FLASH_EMMC_3 = 0x23, 6708772f6eSPatrick Delaunay 6808772f6eSPatrick Delaunay BOOT_FLASH_NAND = 0x30, 6908772f6eSPatrick Delaunay BOOT_FLASH_NAND_FMC = 0x31, 7008772f6eSPatrick Delaunay 7108772f6eSPatrick Delaunay BOOT_FLASH_NOR = 0x40, 7208772f6eSPatrick Delaunay BOOT_FLASH_NOR_QSPI = 0x41, 7308772f6eSPatrick Delaunay 7408772f6eSPatrick Delaunay BOOT_SERIAL_UART = 0x50, 7508772f6eSPatrick Delaunay BOOT_SERIAL_UART_1 = 0x51, 7608772f6eSPatrick Delaunay BOOT_SERIAL_UART_2 = 0x52, 7708772f6eSPatrick Delaunay BOOT_SERIAL_UART_3 = 0x53, 7808772f6eSPatrick Delaunay BOOT_SERIAL_UART_4 = 0x54, 7908772f6eSPatrick Delaunay BOOT_SERIAL_UART_5 = 0x55, 8008772f6eSPatrick Delaunay BOOT_SERIAL_UART_6 = 0x56, 8108772f6eSPatrick Delaunay BOOT_SERIAL_UART_7 = 0x57, 8208772f6eSPatrick Delaunay BOOT_SERIAL_UART_8 = 0x58, 8308772f6eSPatrick Delaunay 8408772f6eSPatrick Delaunay BOOT_SERIAL_USB = 0x60, 8508772f6eSPatrick Delaunay BOOT_SERIAL_USB_OTG = 0x62, 8608772f6eSPatrick Delaunay }; 8708772f6eSPatrick Delaunay 8808772f6eSPatrick Delaunay /* TAMP registers */ 8908772f6eSPatrick Delaunay #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) 9041c79775SPatrick Delaunay #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) 9141c79775SPatrick Delaunay #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) 9208772f6eSPatrick Delaunay #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) 9308772f6eSPatrick Delaunay 9408772f6eSPatrick Delaunay #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) 9508772f6eSPatrick Delaunay #define TAMP_BOOT_MODE_SHIFT 8 9608772f6eSPatrick Delaunay #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) 9708772f6eSPatrick Delaunay #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) 9808772f6eSPatrick Delaunay 99*19f58992SPatrick Delaunay /* offset used for BSEC driver: misc_read and misc_write */ 100*19f58992SPatrick Delaunay #define STM32_BSEC_SHADOW_OFFSET 0x0 101*19f58992SPatrick Delaunay #define STM32_BSEC_OTP_OFFSET 0x80000000 102*19f58992SPatrick Delaunay 10308772f6eSPatrick Delaunay #endif /* __ASSEMBLY__*/ 1042514c2d0SPatrick Delaunay #endif /* _MACH_STM32_H_ */ 105