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12

/openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dmxsimage-signed.cfg2 SECTION 0x0 BOOTABLE
4 LOAD 0x1000 spl/u-boot-spl.bin
5 LOAD 0x8000 spl/u-boot-spl.ivt
6 LOAD 0x8040 spl/u-boot-spl.sig
7 CALL HAB 0x8000 0x0
8 LOAD 0x40002000 u-boot.bin
9 LOAD 0x40001000 u-boot.ivt
10 LOAD 0x40001040 u-boot.sig
11 CALL HAB 0x40001000 0x0
H A DMakefile30 echo -n "0x402000d1 $2 0 0 0 $3 $4 0 $$sz 0 0 0 0 0 0 0" | \
48 echo " Blocks = $2 0x0 `stat -c '%s' $$bin` \"$$bin\" , \\" >> $@ ; \
49 echo " $3 0x0 0x40 \"$$ivt\"" >> $@
59 0x00008000,0x00008040)
64 0x40001000,0x40001040)
67 $(call if_changed,mkcsfreq_mxs,$(CONFIG_SPL_TEXT_BASE),0x8000)
70 $(call if_changed,mkcsfreq_mxs,$(CONFIG_SYS_TEXT_BASE),0x40001000)
/openbmc/openbmc/meta-aspeed/conf/machine/include/
H A Dast2400.inc7 UBOOT_ENTRYPOINT ?= "0x40001000"
8 UBOOT_LOADADDRESS ?= "0x40001000"
/openbmc/linux/Documentation/devicetree/bindings/arm/freescale/
H A Dfsl,vf610-mscm-cpucfg.txt13 reg = <0x40001000 0x800>;
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,mps2-timer.txt18 reg = <0x40000000 0x1000>;
25 reg = <0x40001000 0x1000>;
/openbmc/linux/arch/m68k/configs/
H A Dstmark2_defconfig20 CONFIG_RAMBASE=0x40000000
21 CONFIG_RAMSIZE=0x8000000
22 CONFIG_VECTORBASE=0x40000000
23 CONFIG_KERNELBASE=0x40001000
/openbmc/u-boot/include/configs/
H A Dstmark2.h14 #define CONFIG_SYS_UART_PORT 0
29 "sf probe 0:1 50000000; " \
30 "sf read ${loadaddr} 0x100000 ${kern_size}; " \
34 "kern_size=0x700000\0" \
35 "loadaddr=0x40001000\0" \
36 "-(rootfs)\0" \
38 "sf probe 0:1 50000000; " \
39 "sf erase 0 0x80000; " \
40 "sf write ${loadaddr} 0 ${filesize}\0" \
43 "sf probe 0:1 50000000; " \
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-ep.yaml187 reg = <0x01c00000 0x3000>,
188 <0x40000000 0xf1d>,
189 <0x40000f20 0xc8>,
190 <0x40001000 0x1000>,
191 <0x40002000 0x1000>,
192 <0x01c03000 0x3000>;
206 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p.dtsi184 linux,pci-domain = <0>;
201 reg = <0x0 0x01c10000 0x0 0x3000>,
202 <0x0 0x40000000 0x0 0xf1d>,
203 <0x0 0x40000f20 0x0 0xa8>,
204 <0x0 0x40001000 0x0 0x1000>,
205 <0x0 0x40100000 0x0 0x100000>;
208 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
209 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1d00000>;
216 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
217 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dstm32f429.dtsi52 #clock-cells = <0>;
54 clock-frequency = <0>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
72 clock-frequency = <0>;
79 reg = <0x40000000 0x400>;
81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
87 #size-cells = <0>;
89 reg = <0x40000000 0x400>;
[all …]
H A Dstm32mp157c.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
64 reg = <0xa0021000 0x1000>,
65 <0xa0022000 0x2000>;
79 #clock-cells = <0>;
85 #clock-cells = <0>;
91 #clock-cells = <0>;
[all …]
/openbmc/qemu/hw/arm/
H A Dstm32f100_soc.c39 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
40 0x40004800 };
41 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
53 for (i = 0; i < STM_NUM_USARTS; i++) { in stm32f100_soc_initfn()
58 for (i = 0; i < STM_NUM_SPIS; i++) { in stm32f100_soc_initfn()
62 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in stm32f100_soc_initfn()
63 s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); in stm32f100_soc_initfn()
101 * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 in stm32f100_soc_realize()
106 "STM32F100.flash.alias", &s->flash, 0, FLASH_SIZE); in stm32f100_soc_realize()
108 memory_region_add_subregion(system_memory, 0, &s->flash_alias); in stm32f100_soc_realize()
[all …]
H A Dmsf2-soc.c35 #define MSF2_TIMER_BASE 0x40004000
36 #define MSF2_SYSREG_BASE 0x40038000
37 #define MSF2_EMAC_BASE 0x40041000
39 #define ENVM_BASE_ADDRESS 0x60000000
41 #define SRAM_BASE_ADDRESS 0x20000000
54 static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
55 static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
72 for (i = 0; i < MSF2_NUM_SPIS; i++) { in m2sxxx_soc_initfn()
78 s->m3clk = qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0); in m2sxxx_soc_initfn()
79 s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); in m2sxxx_soc_initfn()
[all …]
H A Dstm32f405_soc.c33 #define RCC_ADDR 0x40023800
34 #define SYSCFG_ADD 0x40013800
35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
36 0x40004C00, 0x40005000, 0x40011400,
37 0x40007800, 0x40007C00 };
39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
40 0x40000800, 0x40000C00 };
41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
42 0x40012300, 0x40012400, 0x40012500 };
43 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
[all …]
H A Darmsse.c54 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */
85 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
86 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
87 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
88 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
89 DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
98 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
99 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
100 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
103 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
[all …]
H A Dstm32l4x5_soc.c36 #define FLASH_BASE_ADDRESS 0x08000000
37 #define SRAM1_BASE_ADDRESS 0x20000000
39 #define SRAM2_BASE_ADDRESS 0x10000000
42 #define EXTI_ADDR 0x40010400
43 #define SYSCFG_ADDR 0x40010000
53 6, /* GPIO[0] */
81 #define RCC_BASE_ADDRESS 0x40021000
114 { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
115 { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
116 { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
[all …]
/openbmc/linux/drivers/input/touchscreen/
H A Dimagis.c15 #define IST3038C_HIB_ACCESS (0x800B << 16)
17 #define IST3038C_REG_CHIPID 0x40001000
18 #define IST3038C_REG_HIB_BASE 0x30000100
20 #define IST3038C_REG_TOUCH_COORD (IST3038C_REG_HIB_BASE | IST3038C_HIB_ACCESS | 0x8)
21 #define IST3038C_REG_INTR_MESSAGE (IST3038C_REG_HIB_BASE | IST3038C_HIB_ACCESS | 0x4)
22 #define IST3038C_WHOAMI 0x38c
27 #define IST3038C_Y_MASK GENMASK(11, 0)
30 #define IST3038C_FINGER_STATUS_MASK GENMASK(9, 0)
47 .flags = 0, in imagis_i2c_read_reg()
65 return 0; in imagis_i2c_read_reg()
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx55.dtsi20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
25 reg = <0 0>;
31 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
108 reg = <0x8fc00000 0x80000>;
113 reg = <0x8fc80000 0x40000>;
[all …]
H A Dqcom-sdx65.dtsi20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
25 reg = <0 0>;
33 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0>;
115 reg = <0x8fcad000 0x40000>;
120 reg = <0x8fcfd000 0x1000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32f746.dtsi53 #clock-cells = <0>;
55 clock-frequency = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
80 #size-cells = <0>;
82 reg = <0x40000000 0x400>;
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
102 #size-cells = <0>;
104 reg = <0x40000400 0x400>;
[all …]
H A Dstm32f429.dtsi58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 #size-cells = <0>;
[all …]
H A Dstm32mp131.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
43 #size-cells = <0>;
44 linaro,optee-channel-id = <0>;
47 reg = <0x14>;
52 reg = <0x16>;
57 reg = <0x17>;
61 #size-cells = <0>;
63 scmi_reg11: regulator@0 {
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvfxxx.dtsi33 #clock-cells = <0>;
39 #clock-cells = <0>;
46 offset = <0x0>;
47 mask = <0x1000>;
66 reg = <0x40000000 0x00070000>;
71 reg = <0x40001000 0x800>;
76 reg = <0x40001800 0x400>;
85 reg = <0x40018000 0x2000>,
86 <0x40024000 0x1000>,
87 <0x40025000 0x1000>;
[all …]
/openbmc/u-boot/board/ti/am43xx/
H A Dboard.c121 0x00500050,
122 0x00350035,
123 0x00350035,
124 0x00350035,
125 0x00350035,
126 0x00350035,
127 0x00000000,
128 0x00000000,
129 0x00000000,
130 0x00000000,
[all …]
/openbmc/linux/lib/crypto/
H A Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]

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