Home
last modified time | relevance | path

Searched +full:0 +full:x40000c00 (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dst,stm32-timer.yaml43 reg = <0x40000c00 0x400>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dst,stm32h7-rcc.txt33 reg = <0x58024400 0x400>;
48 reg = <0x40000c00 0x400>;
65 crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
/openbmc/u-boot/arch/arm/dts/
H A Dstm32h743.dtsi51 #clock-cells = <0>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
74 reg = <0x58024400 0x400>;
81 reg = <0x40011000 0x400>;
89 reg = <0x40004400 0x400>;
97 reg = <0x40000c00 0x400>;
104 reg = <0x58024800 0x400>;
109 reg = <0x52004000 0x1000>;
[all …]
H A Dstm32f429.dtsi52 #clock-cells = <0>;
54 clock-frequency = <0>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
72 clock-frequency = <0>;
79 reg = <0x40000000 0x400>;
81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
87 #size-cells = <0>;
89 reg = <0x40000000 0x400>;
[all …]
H A Dstm32f746.dtsi56 #clock-cells = <0>;
58 clock-frequency = <0>;
66 reg = <0x40028000 0x8000>;
68 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
69 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
70 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
81 reg = <0xA0000000 0x1000>;
82 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
89 #size-cells = <0>;
90 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32h7-rcc.txt37 reg = <0x58024400 0x400>;
43 #size-cells = <0>;
46 #clock-cells = <0>;
48 reg = <0>;
52 #clock-cells = <0>;
57 st,frac-status = <0>;
58 st,frac = <0>;
90 - #clock-cells: from common clock binding; shall be set to 0
98 - 0 Pll is configured in integer mode
101 - st,frac: Fractional part of the multiplication factor : <0..8191>
[all …]
/openbmc/qemu/hw/arm/
H A Dstm32f205_soc.c36 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
37 0x40000800, 0x40000C00 };
38 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
39 0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
40 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
41 0x40012200 };
42 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
43 0x40003C00 };
59 for (i = 0; i < STM_NUM_USARTS; i++) { in stm32f205_soc_initfn()
64 for (i = 0; i < STM_NUM_TIMERS; i++) { in stm32f205_soc_initfn()
[all …]
H A Dstm32f405_soc.c33 #define RCC_ADDR 0x40023800
34 #define SYSCFG_ADD 0x40013800
35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
36 0x40004C00, 0x40005000, 0x40011400,
37 0x40007800, 0x40007C00 };
39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
40 0x40000800, 0x40000C00 };
41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
42 0x40012300, 0x40012400, 0x40012500 };
43 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
[all …]
H A Dstm32l4x5_soc.c36 #define FLASH_BASE_ADDRESS 0x08000000
37 #define SRAM1_BASE_ADDRESS 0x20000000
39 #define SRAM2_BASE_ADDRESS 0x10000000
42 #define EXTI_ADDR 0x40010400
43 #define SYSCFG_ADDR 0x40010000
53 6, /* GPIO[0] */
81 #define RCC_BASE_ADDRESS 0x40021000
114 { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
115 { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
116 { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dtaishan.dts20 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
38 timebase-frequency = <0>; // Filled in by zImage
50 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
58 dcr-reg = <0x200 0x009>;
59 #address-cells = <0>;
60 #size-cells = <0>;
68 cell-index = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32f746.dtsi53 #clock-cells = <0>;
55 clock-frequency = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
80 #size-cells = <0>;
82 reg = <0x40000000 0x400>;
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
102 #size-cells = <0>;
104 reg = <0x40000400 0x400>;
[all …]
H A Dstm32f429.dtsi58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 #size-cells = <0>;
[all …]
H A Dstm32h743.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
68 clock-frequency = <0>;
75 reg = <0x40000c00 0x400>;
82 #size-cells = <0>;
84 reg = <0x40002400 0x400>;
95 trigger@0 {
97 reg = <0>;
[all …]