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/openbmc/u-boot/arch/arm/include/asm/arch-bcm281xx/
H A Dsysmap.h8 #define BSC1_BASE_ADDR 0x3e016000
9 #define BSC2_BASE_ADDR 0x3e017000
10 #define BSC3_BASE_ADDR 0x3e018000
11 #define DWDMA_AHB_BASE_ADDR 0x38100000
12 #define ESUB_CLK_BASE_ADDR 0x38000000
13 #define ESW_CONTRL_BASE_ADDR 0x38200000
14 #define GPIO2_BASE_ADDR 0x35003000
15 #define HSOTG_BASE_ADDR 0x3f120000
16 #define HSOTG_CTRL_BASE_ADDR 0x3f130000
17 #define KONA_MST_CLK_BASE_ADDR 0x3f001000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dfsl,imx8mq-dwc3.yaml40 reg = <0x38200000 0x10000>;
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dapple,admac.yaml51 an empty phandle reference <0>.
84 reg = <0x38200000 0x34000>;
86 interrupts-extended = <0>,
88 <0>,
89 <0>;
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra194-pcie.yaml85 - const: p2u-0
123 0: C0
132 0 : C0
260 bus@0 {
263 ranges = <0x0 0x0 0x0 0x8 0x0>;
268 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
269 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
270 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
271 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
278 linux,pci-domain = <0>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dimx-regs.h11 #define ROM_VERSION_A0 0x800
12 #define ROM_VERSION_B0 0x83C
14 #define M4_BOOTROM_BASE_ADDR 0x007E0000
16 #define SAI1_BASE_ADDR 0x30010000
17 #define SAI6_BASE_ADDR 0x30030000
18 #define SAI5_BASE_ADDR 0x30040000
19 #define SAI4_BASE_ADDR 0x30050000
20 #define SPBA2_BASE_ADDR 0x300F0000
21 #define AIPS1_BASE_ADDR 0x301F0000
22 #define GPIO1_BASE_ADDR 0X30200000
[all …]
/openbmc/qemu/contrib/plugins/
H A Dhowvec.c25 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
62 * 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0
66 { " UDEF", "udef", 0xffff0000, 0x00000000, COUNT_NONE},
67 { " SVE", "sve", 0x1e000000, 0x04000000, COUNT_CLASS},
68 { "Reserved", "res", 0x1e000000, 0x00000000, COUNT_CLASS},
70 { " PCrel addr", "pcrel", 0x1f000000, 0x10000000, COUNT_CLASS},
71 { " Add/Sub (imm,tags)", "asit", 0x1f800000, 0x11800000, COUNT_CLASS},
72 { " Add/Sub (imm)", "asi", 0x1f000000, 0x11000000, COUNT_CLASS},
73 { " Logical (imm)", "logi", 0x1f800000, 0x12000000, COUNT_CLASS},
74 { " Move Wide (imm)", "movwi", 0x1f800000, 0x12800000, COUNT_CLASS},
[all …]
/openbmc/linux/arch/arm64/include/asm/
H A Dinsn.h18 AARCH64_INSN_HINT_NOP = 0x0 << 5,
19 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
20 AARCH64_INSN_HINT_WFE = 0x2 << 5,
21 AARCH64_INSN_HINT_WFI = 0x3 << 5,
22 AARCH64_INSN_HINT_SEV = 0x4 << 5,
23 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
25 AARCH64_INSN_HINT_XPACLRI = 0x07 << 5,
26 AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
27 AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
28 AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
[all …]
/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi15 #size-cells = <0>;
17 cpu0: cpu@0 {
23 reg = <0>;
173 #clock-cells = <0>;
178 mboxes = <&mbox 0>;
189 reg = <0x0 0x2010000 0x0 0x1000>;
201 reg = <0x0 0x2000000 0x0 0xC000>;
210 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
211 reg = <0x0 0xc000000 0x0 0x4000000>;
212 #address-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/apple/
H A Dt8103.dtsi23 #size-cells = <0>;
57 cpu_e0: cpu@0 {
60 reg = <0x0 0x0>;
62 cpu-release-addr = <0 0>; /* To be filled by loader */
67 i-cache-size = <0x20000>;
68 d-cache-size = <0x10000>;
74 reg = <0x0 0x1>;
76 cpu-release-addr = <0 0>; /* To be filled by loader */
81 i-cache-size = <0x20000>;
82 d-cache-size = <0x10000>;
[all …]
H A Dt8112.dtsi24 #size-cells = <0>;
58 cpu_e0: cpu@0 {
61 reg = <0x0 0x0>;
63 cpu-release-addr = <0 0>; /* To be filled by loader */
68 i-cache-size = <0x20000>;
69 d-cache-size = <0x10000>;
75 reg = <0x0 0x1>;
77 cpu-release-addr = <0 0>; /* To be filled by loader */
82 i-cache-size = <0x20000>;
83 d-cache-size = <0x10000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq.dtsi47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
[all …]
H A Dimx8mp.dtsi48 #size-cells = <0>;
50 A53_0: cpu@0 {
53 reg = <0x0>;
57 i-cache-size = <0x8000>;
60 d-cache-size = <0x8000>;
73 reg = <0x1>;
77 i-cache-size = <0x8000>;
80 d-cache-size = <0x8000>;
91 reg = <0x2>;
95 i-cache-size = <0x8000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc8280xp.dtsi32 #clock-cells = <0>;
37 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x100>;
77 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc12 OPC_MOVGR2SCR = 0x00000800,
13 OPC_MOVSCR2GR = 0x00000c00,
14 OPC_CLZ_W = 0x00001400,
15 OPC_CTZ_W = 0x00001c00,
16 OPC_CLZ_D = 0x00002400,
17 OPC_CTZ_D = 0x00002c00,
18 OPC_REVB_2H = 0x00003000,
19 OPC_REVB_2W = 0x00003800,
20 OPC_REVB_D = 0x00003c00,
21 OPC_SEXT_H = 0x00005800,
[all …]