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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Drealtek,otto-wdt.yaml78 reg = <0x3150 0xc>;
/openbmc/linux/drivers/video/fbdev/aty/
H A Dati_ids.h8 #define PCI_CHIP_RV380_3150 0x3150
9 #define PCI_CHIP_RV380_3151 0x3151
10 #define PCI_CHIP_RV380_3152 0x3152
11 #define PCI_CHIP_RV380_3153 0x3153
12 #define PCI_CHIP_RV380_3154 0x3154
13 #define PCI_CHIP_RV380_3156 0x3156
14 #define PCI_CHIP_RV380_3E50 0x3E50
15 #define PCI_CHIP_RV380_3E51 0x3E51
16 #define PCI_CHIP_RV380_3E52 0x3E52
17 #define PCI_CHIP_RV380_3E53 0x3E53
[all …]
/openbmc/u-boot/drivers/video/
H A Dati_ids.h7 #define PCI_CHIP_RV380_3150 0x3150
8 #define PCI_CHIP_RV380_3151 0x3151
9 #define PCI_CHIP_RV380_3152 0x3152
10 #define PCI_CHIP_RV380_3153 0x3153
11 #define PCI_CHIP_RV380_3154 0x3154
12 #define PCI_CHIP_RV380_3156 0x3156
13 #define PCI_CHIP_RV380_3E50 0x3E50
14 #define PCI_CHIP_RV380_3E51 0x3E51
15 #define PCI_CHIP_RV380_3E52 0x3E52
16 #define PCI_CHIP_RV380_3E53 0x3E53
[all …]
/openbmc/qemu/include/hw/southbridge/
H A Dich9.h80 #define ICH9_CC_D28IP 0x310C
82 #define ICH9_CC_D28IP_MASK 0xf
83 #define ICH9_CC_D28IP_DEFAULT 0x00214321
84 #define ICH9_CC_D31IR 0x3140
85 #define ICH9_CC_D30IR 0x3142
86 #define ICH9_CC_D29IR 0x3144
87 #define ICH9_CC_D28IR 0x3146
88 #define ICH9_CC_D27IR 0x3148
89 #define ICH9_CC_D26IR 0x314C
90 #define ICH9_CC_D25IR 0x3150
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23-pinfunc.h13 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
14 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
15 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
16 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
17 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
18 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
19 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
20 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
21 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
22 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
[all …]
H A Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-ivybridge/
H A Dpch.h17 #define PCH_TYPE_CPT 0x1c /* CougarPoint */
18 #define PCH_TYPE_PPT 0x1e /* IvyBridge */
21 #define PCH_STEP_A0 0
27 #define DEFAULT_GPIOBASE 0x0480
28 #define DEFAULT_PMBASE 0x0500
30 #define SMBUS_IO_BASE 0x0400
32 #define MAINBOARD_POWER_OFF 0
37 #define PSTS 0x06
38 #define SMLT 0x1b
39 #define SECSTS 0x1e
[all …]
/openbmc/qemu/hw/net/
H A De1000e.c87 #define E1000E_MMIO_IDX 0
97 #define E1000E_MSIX_TABLE (0x0000)
98 #define E1000E_MSIX_PBA (0x2000)
118 if (s->ioaddr < 0x1FFFF) { in e1000e_io_get_reg_index()
123 if (s->ioaddr < 0x7FFFF) { in e1000e_io_get_reg_index()
128 if (s->ioaddr < 0xFFFFF) { in e1000e_io_get_reg_index()
141 uint32_t idx = 0; in e1000e_io_read()
154 return 0; in e1000e_io_read()
157 return 0; in e1000e_io_read()
166 uint32_t idx = 0; in e1000e_io_write()
[all …]
H A De1000.c62 } while (0)
64 #define DBGOUT(what, fmt, ...) do {} while (0)
67 #define IOPORT_SIZE 0x40
68 #define PNPMMIO_SIZE 0x20000
90 uint32_t mac_reg[0x8000];
91 uint16_t phy_reg[0x20];
101 unsigned char data[0x10000];
129 /* Compatibility flags for migration to/from qemu 1.3.0 and older */
185 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ in set_phy_ctrl()
186 s->phy_reg[MII_BMCR] = val & ~(0x3f | in set_phy_ctrl()
[all …]
/openbmc/linux/scripts/
H A Dget_dvb_firmware23 $cid = $ARGV[0];
26 for ($i=0; $i < scalar(@components); $i++) {
35 exit(0);
97 extract("$tmpdir/software/OEM/PCI/App/ttlcdacc.dll", 0x37ef9, 30555, "$tmpdir/fwtmp");
115 …extract("$tmpdir/TT_PCI_2.19h_28_11_2006/software/OEM/PCI/App/ttlcdacc.dll", 0x65389, 24478, "$tmp…
133 extract("$tmpdir/LVHybrid.sys", 0x8b088, 24602, "$tmpdir/fwtmp");
206 my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 0);
211 extract("2830SCap2.sys", 0x62e8, 55024, "$tmpdir/opera1-fpga.fw");
212 extract("2830SLoad2.sys",0x3178,0x3685-0x3178,"$tmpdir/fw1part1");
213 extract("2830SLoad2.sys",0x0980,0x3150-0x0980,"$tmpdir/fw1part2");
[all …]
/openbmc/linux/drivers/crypto/hisilicon/sec2/
H A Dsec_main.c22 #define PCI_DEVICE_ID_HUAWEI_SEC_PF 0xa255
24 #define SEC_BD_ERR_CHK_EN0 0xEFFFFFFF
25 #define SEC_BD_ERR_CHK_EN1 0x7ffff7fd
26 #define SEC_BD_ERR_CHK_EN3 0xffffbfff
30 #define SEC_PF_DEF_Q_BASE 0
34 #define SEC_CTRL_CNT_CLR_CE 0x301120
35 #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0)
36 #define SEC_CORE_INT_SOURCE 0x301010
37 #define SEC_CORE_INT_MASK 0x301000
38 #define SEC_CORE_INT_STATUS 0x301008
[all …]
/openbmc/linux/drivers/crypto/hisilicon/zip/
H A Dzip_main.c17 #define PCI_DEVICE_ID_HUAWEI_ZIP_PF 0xa250
21 #define HZIP_CLOCK_GATE_CTRL 0x301004
23 #define HZIP_FSM_MAX_CNT 0x301008
25 #define HZIP_PORT_ARCA_CHE_0 0x301040
26 #define HZIP_PORT_ARCA_CHE_1 0x301044
27 #define HZIP_PORT_AWCA_CHE_0 0x301060
28 #define HZIP_PORT_AWCA_CHE_1 0x301064
29 #define HZIP_CACHE_ALL_EN 0xffffffff
31 #define HZIP_BD_RUSER_32_63 0x301110
32 #define HZIP_SGL_RUSER_32_63 0x30111c
[all …]
/openbmc/linux/drivers/crypto/hisilicon/hpre/
H A Dhpre_main.c16 #define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0)
17 #define HPRE_CTRL_CNT_CLR_CE 0x301000
18 #define HPRE_FSM_MAX_CNT 0x301008
19 #define HPRE_VFG_AXQOS 0x30100c
20 #define HPRE_VFG_AXCACHE 0x301010
21 #define HPRE_RDCHN_INI_CFG 0x301014
22 #define HPRE_AWUSR_FP_CFG 0x301018
23 #define HPRE_BD_ENDIAN 0x301020
24 #define HPRE_ECC_BYPASS 0x301024
25 #define HPRE_RAS_WIDTH_CFG 0x301028
[all …]
/openbmc/linux/include/video/
H A Dpm3fb.h19 #define PM3ResetStatus 0x0000
20 #define PM3IntEnable 0x0008
21 #define PM3IntFlags 0x0010
22 #define PM3InFIFOSpace 0x0018
23 #define PM3OutFIFOWords 0x0020
24 #define PM3DMAAddress 0x0028
25 #define PM3DMACount 0x0030
26 #define PM3ErrorFlags 0x0038
27 #define PM3VClkCtl 0x0040
28 #define PM3TestRegister 0x0048
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dimx290.c31 #define IMX290_STANDBY CCI_REG8(0x3000)
32 #define IMX290_REGHOLD CCI_REG8(0x3001)
33 #define IMX290_XMSTA CCI_REG8(0x3002)
34 #define IMX290_ADBIT CCI_REG8(0x3005)
35 #define IMX290_ADBIT_10BIT (0 << 0)
36 #define IMX290_ADBIT_12BIT (1 << 0)
37 #define IMX290_CTRL_07 CCI_REG8(0x3007)
38 #define IMX290_VREVERSE BIT(0)
40 #define IMX290_WINMODE_1080P (0 << 4)
43 #define IMX290_FR_FDG_SEL CCI_REG8(0x3009)
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008
[all …]
H A Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
H A Ddpcs_4_2_2_offset.h14 // base address: 0x0
15 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
17 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
22 // base address: 0x360
23 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
30 // base address: 0x6c0
31 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
33 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
38 // base address: 0xa20
[all …]
H A Ddpcs_4_2_3_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
34 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
39 // base address: 0x360
40 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
47 // base address: 0x6c0
48 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
50 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
55 // base address: 0xa20
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwm5102.c41 static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0);
42 static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
43 static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
44 static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0);
45 static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
48 { .type = WMFW_ADSP2_PM, .base = 0x100000 },
49 { .type = WMFW_ADSP2_ZM, .base = 0x180000 },
50 { .type = WMFW_ADSP2_XM, .base = 0x190000 },
51 { .type = WMFW_ADSP2_YM, .base = 0x1a8000 },
55 { 0x3000, 0x2225 },
[all …]
/openbmc/linux/include/drm/
H A Ddrm_pciids.h3 …{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RA…
4 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
5 …{0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RA…
6 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
7 …{0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RA…
8 …{0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RA…
9 …{0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RA…
10 …{0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RA…
11 …{0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RA…
12 …{0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RA…
[all …]
/openbmc/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra210.c22 #define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0)
182 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
1266 #define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */
1267 #define PINGROUP_REG_A 0x3000 /* bank 1 */
1290 .mux_bit = 0, \
1306 .drv_bank = 0, \
1335 .drv_bank = 0, \
1354 …PINGROUP(sdmmc1_clk_pm0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3000, Y, Y, N, N,…
1355 …PINGROUP(sdmmc1_cmd_pm1, SDMMC1, SPI3, RSVD2, RSVD3, 0x3004, Y, Y, N, N,…
1356 …PINGROUP(sdmmc1_dat3_pm2, SDMMC1, SPI3, RSVD2, RSVD3, 0x3008, Y, Y, N, N,…
[all …]
H A Dpinctrl-tegra30.c24 #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
278 #define TEGRA_PIN_CLK_32K_IN _PIN(0)
2099 #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
2100 #define PINGROUP_REG_A 0x3000 /* bank 1 */
2121 .mux_bit = 0, \
2134 .parked_bitmask = 0, \
2153 .drv_bank = 0, \
2166 .parked_bitmask = 0, \
2171 …PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, 0x331c, N, …
2172 …PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, 0x317c, N, …
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dmmcc-apq8084.c44 .l_reg = 0x0004,
45 .m_reg = 0x0008,
46 .n_reg = 0x000c,
47 .config_reg = 0x0014,
48 .mode_reg = 0x0000,
49 .status_reg = 0x001c,
62 .enable_reg = 0x0100,
63 .enable_mask = BIT(0),
75 .l_reg = 0x0044,
76 .m_reg = 0x0048,
[all …]
H A Dmmcc-msm8974.c45 .l_reg = 0x0004,
46 .m_reg = 0x0008,
47 .n_reg = 0x000c,
48 .config_reg = 0x0014,
49 .mode_reg = 0x0000,
50 .status_reg = 0x001c,
63 .enable_reg = 0x0100,
64 .enable_mask = BIT(0),
76 .l_reg = 0x0044,
77 .m_reg = 0x0048,
[all …]

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