11da9bf73SSander Vanheule# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
21da9bf73SSander Vanheule%YAML 1.2
31da9bf73SSander Vanheule---
41da9bf73SSander Vanheule$id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml#
51da9bf73SSander Vanheule$schema: http://devicetree.org/meta-schemas/core.yaml#
61da9bf73SSander Vanheule
71da9bf73SSander Vanheuletitle: Realtek Otto watchdog timer
81da9bf73SSander Vanheule
91da9bf73SSander Vanheulemaintainers:
101da9bf73SSander Vanheule  - Sander Vanheule <sander@svanheule.net>
111da9bf73SSander Vanheule
121da9bf73SSander Vanheuledescription: |
131da9bf73SSander Vanheule  The timer has two timeout phases. Both phases have a maximum duration of 32
141da9bf73SSander Vanheule  prescaled clock ticks, which is ca. 43s with a bus clock of 200MHz. The
151da9bf73SSander Vanheule  minimum duration of each phase is one tick. Each phase can trigger an
161da9bf73SSander Vanheule  interrupt, although the phase 2 interrupt will occur with the system reset.
171da9bf73SSander Vanheule  - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
181da9bf73SSander Vanheule  - Phase 2: Starts after phase 1 has timed out, and only serves to give the
191da9bf73SSander Vanheule    system some time to clean up, or notify others that it's going to reset.
201da9bf73SSander Vanheule    During this phase, pinging the WDT has no effect, and a reset is
211da9bf73SSander Vanheule    unavoidable, unless the WDT is disabled.
221da9bf73SSander Vanheule
231da9bf73SSander VanheuleallOf:
241da9bf73SSander Vanheule  - $ref: watchdog.yaml#
251da9bf73SSander Vanheule
261da9bf73SSander Vanheuleproperties:
271da9bf73SSander Vanheule  compatible:
281da9bf73SSander Vanheule    enum:
291da9bf73SSander Vanheule      - realtek,rtl8380-wdt
301da9bf73SSander Vanheule      - realtek,rtl8390-wdt
311da9bf73SSander Vanheule      - realtek,rtl9300-wdt
32595d9a69SSander Vanheule      - realtek,rtl9310-wdt
331da9bf73SSander Vanheule
341da9bf73SSander Vanheule  reg:
351da9bf73SSander Vanheule    maxItems: 1
361da9bf73SSander Vanheule
371da9bf73SSander Vanheule  clocks:
381da9bf73SSander Vanheule    maxItems: 1
391da9bf73SSander Vanheule
401da9bf73SSander Vanheule  interrupts:
411da9bf73SSander Vanheule    items:
421da9bf73SSander Vanheule      - description: interrupt specifier for pretimeout
431da9bf73SSander Vanheule      - description: interrupt specifier for timeout
441da9bf73SSander Vanheule
451da9bf73SSander Vanheule  interrupt-names:
461da9bf73SSander Vanheule    items:
471da9bf73SSander Vanheule      - const: phase1
481da9bf73SSander Vanheule      - const: phase2
491da9bf73SSander Vanheule
501da9bf73SSander Vanheule  realtek,reset-mode:
511da9bf73SSander Vanheule    $ref: /schemas/types.yaml#/definitions/string
521da9bf73SSander Vanheule    description: |
531da9bf73SSander Vanheule      Specify how the system is reset after a timeout. Defaults to "cpu" if
541da9bf73SSander Vanheule      left unspecified.
551da9bf73SSander Vanheule    oneOf:
561da9bf73SSander Vanheule      - description: Reset the entire chip
571da9bf73SSander Vanheule        const: soc
581da9bf73SSander Vanheule      - description: |
591da9bf73SSander Vanheule          Reset the CPU and IPsec engine, but leave other peripherals untouched
601da9bf73SSander Vanheule        const: cpu
611da9bf73SSander Vanheule      - description: |
621da9bf73SSander Vanheule          Reset the execution pointer, but don't actually reset any hardware
631da9bf73SSander Vanheule        const: software
641da9bf73SSander Vanheule
651da9bf73SSander Vanheulerequired:
661da9bf73SSander Vanheule  - compatible
671da9bf73SSander Vanheule  - reg
681da9bf73SSander Vanheule  - clocks
691da9bf73SSander Vanheule  - interrupts
70*495cbe36SKrzysztof Kozlowski  - interrupt-names
711da9bf73SSander Vanheule
721da9bf73SSander VanheuleunevaluatedProperties: false
731da9bf73SSander Vanheule
741da9bf73SSander Vanheuleexamples:
751da9bf73SSander Vanheule  - |
761da9bf73SSander Vanheule    watchdog: watchdog@3150 {
771da9bf73SSander Vanheule        compatible = "realtek,rtl8380-wdt";
781da9bf73SSander Vanheule        reg = <0x3150 0xc>;
791da9bf73SSander Vanheule
801da9bf73SSander Vanheule        realtek,reset-mode = "soc";
811da9bf73SSander Vanheule
821da9bf73SSander Vanheule        clocks = <&lxbus_clock>;
831da9bf73SSander Vanheule        timeout-sec = <20>;
841da9bf73SSander Vanheule
851da9bf73SSander Vanheule        interrupt-parent = <&rtlintc>;
861da9bf73SSander Vanheule        interrupt-names = "phase1", "phase2";
871da9bf73SSander Vanheule        interrupts = <19>, <18>;
881da9bf73SSander Vanheule    };
891da9bf73SSander Vanheule
901da9bf73SSander Vanheule...
91