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/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dcpu_ca53_cfg_masks.h23 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0
24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3
26 #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30
28 #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300
30 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000
33 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0
34 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF
37 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0
38 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF
41 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbtc8822bwifionly.c9 halwifionly_phy_set_bb_reg(wifionlycfg, 0x4c, 0x01800000, 0x2); in ex_hal8822b_wifi_only_hw_config()
11 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcb4, 0xff, 0x77); in ex_hal8822b_wifi_only_hw_config()
13 halwifionly_phy_set_bb_reg(wifionlycfg, 0x974, 0x300, 0x3); in ex_hal8822b_wifi_only_hw_config()
15 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1990, 0x300, 0x0); in ex_hal8822b_wifi_only_hw_config()
17 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x80000, 0x0); in ex_hal8822b_wifi_only_hw_config()
19 halwifionly_phy_set_bb_reg(wifionlycfg, 0x70, 0xff000000, 0x0e); in ex_hal8822b_wifi_only_hw_config()
20 /*gnt_wl=1 , gnt_bt=0*/ in ex_hal8822b_wifi_only_hw_config()
21 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1704, 0xffffffff, 0x7700); in ex_hal8822b_wifi_only_hw_config()
22 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1700, 0xffffffff, 0xc00f0038); in ex_hal8822b_wifi_only_hw_config()
41 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x300, 0x1); in hal8822b_wifi_only_switch_antenna()
[all …]
/openbmc/linux/drivers/media/pci/bt8xx/
H A Dbttv-audio-hook.c30 for (loops = 17; loops >= 0 ; loops--) { in winview_volume()
70 gpio_inout(0x300, 0x300); in gvbctv3pci_audio()
74 con = 0x000; in gvbctv3pci_audio()
77 con = 0x300; in gvbctv3pci_audio()
80 con = 0x200; in gvbctv3pci_audio()
83 gpio_bits(0x300, con); in gvbctv3pci_audio()
97 con = 0x300; in gvbctv5pci_audio()
100 con = 0x100; in gvbctv5pci_audio()
103 con = 0x000; in gvbctv5pci_audio()
106 if (con != (val & 0x300)) { in gvbctv5pci_audio()
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Ddib0090.c25 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
31 } while (0)
40 #define EN_LNA0 0x8000
41 #define EN_LNA1 0x4000
42 #define EN_LNA2 0x2000
43 #define EN_LNA3 0x1000
44 #define EN_MIX0 0x0800
45 #define EN_MIX1 0x0400
46 #define EN_MIX2 0x0200
47 #define EN_MIX3 0x0100
[all …]
/openbmc/qemu/hw/pci-host/
H A Dastro.c94 case 0x0008: in elroy_chip_read_with_attrs()
95 val = 0x6000005; /* func_class */ in elroy_chip_read_with_attrs()
97 case 0x0058: in elroy_chip_read_with_attrs()
106 case 0x0080: in elroy_chip_read_with_attrs()
109 case 0x0108: in elroy_chip_read_with_attrs()
112 case 0x200 ... 0x250 - 1: /* LMMIO, GMMIO, WLMMIO, WGMMIO, ... */ in elroy_chip_read_with_attrs()
113 index = (addr - 0x200) / 8; in elroy_chip_read_with_attrs()
116 case 0x0680: in elroy_chip_read_with_attrs()
119 case 0x0688: in elroy_chip_read_with_attrs()
120 val = 0; /* ERROR_STATUS */ in elroy_chip_read_with_attrs()
[all …]
/openbmc/linux/arch/arm/mach-orion5x/
H A Dbridge-regs.h9 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
11 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
13 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
14 #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
16 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
18 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
20 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
22 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
24 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
26 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
[all …]
/openbmc/linux/drivers/clk/rockchip/
H A Dclk.h29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
30 #define BOOST_CLK_CON 0x0008
31 #define BOOST_BOOST_CON 0x000c
32 #define BOOST_SWITCH_CNT 0x0010
33 #define BOOST_HIGH_PERF_CNT0 0x0014
34 #define BOOST_HIGH_PERF_CNT1 0x0018
35 #define BOOST_STATIS_THRESHOLD 0x001c
36 #define BOOST_SHORT_SWITCH_CNT 0x0020
37 #define BOOST_SWITCH_THRESHOLD 0x0024
38 #define BOOST_FSM_STATUS 0x0028
[all …]
/openbmc/linux/arch/sh/drivers/pci/
H A Dfixups-snapgear.c26 case 11: irq = evt2irq(0x300); break; /* USB */ in pcibios_map_platform_irq()
27 case 12: irq = evt2irq(0x360); break; /* PCMCIA */ in pcibios_map_platform_irq()
28 case 13: irq = evt2irq(0x2a0); break; /* eth0 */ in pcibios_map_platform_irq()
29 case 14: irq = evt2irq(0x300); break; /* eth1 */ in pcibios_map_platform_irq()
30 case 15: irq = evt2irq(0x360); break; /* safenet (unused) */ in pcibios_map_platform_irq()
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x5_can.dtsi17 reg = <0xf8000000 0x300>;
20 pinctrl-0 = <&pinctrl_can0_rx_tx>;
28 reg = <0xf8004000 0x300>;
31 pinctrl-0 = <&pinctrl_can1_rx_tx>;
H A Dsama5d3_can.dtsi36 reg = <0xf000c000 0x300>;
39 pinctrl-0 = <&pinctrl_can0_rx_tx>;
47 reg = <0xf8010000 0x300>;
50 pinctrl-0 = <&pinctrl_can1_rx_tx>;
/openbmc/u-boot/arch/arm/dts/
H A Dat91sam9x5_can.dtsi19 #clock-cells = <0>;
24 #clock-cells = <0>;
32 reg = <0xf8000000 0x300>;
35 pinctrl-0 = <&pinctrl_can0_rx_tx>;
43 reg = <0xf8004000 0x300>;
46 pinctrl-0 = <&pinctrl_can1_rx_tx>;
H A Dsama5d3_can.dtsi38 #clock-cells = <0>;
40 atmel,clk-output-range = <0 66000000>;
44 #clock-cells = <0>;
46 atmel,clk-output-range = <0 66000000>;
53 reg = <0xf000c000 0x300>;
56 pinctrl-0 = <&pinctrl_can0_rx_tx>;
64 reg = <0xf8010000 0x300>;
67 pinctrl-0 = <&pinctrl_can1_rx_tx>;
H A Dimx7ulp-evk.dts18 bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
22 bcmdhd_wlan_0: bcmdhd_wlan@0 {
31 reg = <0x60000000 0x40000000>;
37 pinctrl-0 = <&pinctrl_backlight>;
47 #reset-cells = <0>;
53 #size-cells = <0>;
65 reg_usb_otg1_vbus: regulator@0 {
67 reg = <0>;
69 pinctrl-0 = <&pinctrl_usb_otg1>;
73 gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
[all …]
/openbmc/linux/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/openbmc/linux/drivers/regulator/
H A Dmt6357-regulator.c53 .enable_mask = BIT(0), \
75 .enable_mask = BIT(0), \
96 .enable_mask = BIT(0), \
99 .da_vsel_mask = 0x7f00, \
114 .enable_mask = BIT(0), \
134 if (ret != 0) { in mt6357_get_buck_voltage_sel()
178 0,
186 0,
188 0,
189 0,
[all …]
/openbmc/linux/arch/sh/boards/mach-se/7206/
H A Dsetup.c20 [0] = {
22 .start = PA_SMSC + 0x300,
23 .end = PA_SMSC + 0x300 + 0x020 - 1,
42 .coherent_dma_mask = 0xffffffff,
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/openbmc/u-boot/include/environment/ti/
H A Ddfu.h13 "boot part 0 1;" \
14 "rootfs part 0 2;" \
15 "MLO fat 0 1;" \
16 "MLO.raw raw 0x100 0x100;" \
17 "u-boot.img.raw raw 0x300 0x1000;" \
18 "u-env.raw raw 0x1300 0x200;" \
19 "spl-os-args.raw raw 0x1500 0x200;" \
20 "spl-os-image.raw raw 0x1700 0x6900;" \
21 "spl-os-args fat 0 1;" \
22 "spl-os-image fat 0 1;" \
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dcevt-ds1287.c17 return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0; in ds1287_timer_state()
26 rate = 0x9; in ds1287_set_base_clock()
29 rate = 0x8; in ds1287_set_base_clock()
32 rate = 0x6; in ds1287_set_base_clock()
40 return 0; in ds1287_set_base_clock()
60 return 0; in ds1287_shutdown()
74 return 0; in ds1287_set_periodic()
112 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); in ds1287_clockevent_init()
113 cd->max_delta_ticks = 0x7fffffff; in ds1287_clockevent_init()
114 cd->min_delta_ns = clockevent_delta2ns(0x300, cd); in ds1287_clockevent_init()
[all …]
/openbmc/linux/arch/sh/boards/mach-sdk7780/
H A Dsetup.c18 #define GPIO_PECR 0xFFEA0008
36 [0] = {
38 .start = PA_LAN + 0x300,
39 .end = PA_LAN + 0x300 + 0x10 ,
51 .id = 0,
54 .coherent_dma_mask = 0xffffffff,
80 (ver >> 12) & 0xf, (ver >> 8) & 0xf, in sdk7780_setup()
81 (ver >> 4) & 0xf, ver & 0xf, in sdk7780_setup()
85 __raw_writew(0x0000, GPIO_PECR); in sdk7780_setup()
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml137 enum: [0, 1]
158 enum: [0, 1, 2]
159 default: 0
185 reg = <0xe0100000 0x1000>;
189 interrupts = <0 24 4>;
195 reg = <0xe2800000 0x1000>;
199 interrupts = <0 24 4>;
210 reg = <0xfe330000 0x10000>;
220 #clock-cells = <0>;
227 interrupts = <0 48 4>;
[all …]
/openbmc/u-boot/drivers/adc/
H A Dstm32-adc-core.h17 * | 0x000 | Master ADC1 |
19 * | 0x100 | Slave ADC2 |
21 * | 0x200 | Slave ADC3 |
23 * | 0x300 | Master & Slave common regs |
27 #define STM32_ADCX_COMN_OFFSET 0x300
/openbmc/linux/drivers/net/phy/
H A Dmediatek-ge.c6 #define MTK_EXT_PAGE_ACCESS 0x1f
7 #define MTK_PHY_PAGE_STANDARD 0x0000
8 #define MTK_PHY_PAGE_EXTENDED 0x0001
9 #define MTK_PHY_PAGE_EXTENDED_2 0x0002
10 #define MTK_PHY_PAGE_EXTENDED_3 0x0003
11 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
12 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
27 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); in mtk_gephy_config_init()
30 phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); in mtk_gephy_config_init()
34 __phy_write(phydev, 0x10, 0xafae); in mtk_gephy_config_init()
[all …]

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