1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_CPU_CA53_CFG_MASKS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_CPU_CA53_CFG_MASKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * CPU_CA53_CFG (Prototype: CA53_CFG) 19*e65e175bSOded Gabbay ***************************************** 20*e65e175bSOded Gabbay */ 21*e65e175bSOded Gabbay 22*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_CFG */ 23*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0 24*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3 25*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_CFG_END_SHIFT 4 26*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30 27*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_CFG_TE_SHIFT 8 28*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300 29*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_CFG_VINITHI_SHIFT 12 30*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000 31*e65e175bSOded Gabbay 32*e65e175bSOded Gabbay /* CPU_CA53_CFG_RST_ADDR_LSB */ 33*e65e175bSOded Gabbay #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0 34*e65e175bSOded Gabbay #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF 35*e65e175bSOded Gabbay 36*e65e175bSOded Gabbay /* CPU_CA53_CFG_RST_ADDR_MSB */ 37*e65e175bSOded Gabbay #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0 38*e65e175bSOded Gabbay #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF 39*e65e175bSOded Gabbay 40*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_RST_CONTROL */ 41*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0 42*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3 43*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4 44*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30 45*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8 46*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100 47*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12 48*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000 49*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16 50*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000 51*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20 52*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000 53*e65e175bSOded Gabbay 54*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_AFFINITY */ 55*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_SHIFT 0 56*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_MASK 0xFF 57*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_SHIFT 8 58*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_MASK 0xFF00 59*e65e175bSOded Gabbay 60*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_DISABLE */ 61*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DISABLE_CP15S_SHIFT 0 62*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DISABLE_CP15S_MASK 0x3 63*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_SHIFT 4 64*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_MASK 0x30 65*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DISABLE_L2_RST_SHIFT 8 66*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DISABLE_L2_RST_MASK 0x100 67*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_SHIFT 9 68*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_MASK 0x200 69*e65e175bSOded Gabbay 70*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_GIC_PERIPHBASE */ 71*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_SHIFT 0 72*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_MASK 0x3FFFFF 73*e65e175bSOded Gabbay 74*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_GIC_IRQ_CFG */ 75*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_SHIFT 0 76*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_MASK 0x3 77*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_SHIFT 4 78*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_MASK 0x30 79*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_SHIFT 8 80*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_MASK 0x300 81*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_SHIFT 12 82*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_MASK 0x3000 83*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_SHIFT 16 84*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_MASK 0x30000 85*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_SHIFT 20 86*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_MASK 0x300000 87*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_SHIFT 24 88*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_MASK 0x3000000 89*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_SHIFT 31 90*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_MASK 0x80000000 91*e65e175bSOded Gabbay 92*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_PWR_MNG */ 93*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_SHIFT 0 94*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_MASK 0x1 95*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_SHIFT 1 96*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_MASK 0x2 97*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_SHIFT 2 98*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_MASK 0x4 99*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_SHIFT 3 100*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_MASK 0x8 101*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_SHIFT 4 102*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_MASK 0x30 103*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_SHIFT 8 104*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_MASK 0x300 105*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_SHIFT 12 106*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_MASK 0x3000 107*e65e175bSOded Gabbay 108*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARB_DBG_ROM_ADDR */ 109*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_SHIFT 0 110*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_MASK 0xFFFFFFF 111*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_SHIFT 31 112*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_MASK 0x80000000 113*e65e175bSOded Gabbay 114*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_DBG_MODES */ 115*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_SHIFT 0 116*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_MASK 0x3 117*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_SHIFT 4 118*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_MASK 0x30 119*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_SHIFT 8 120*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_MASK 0x300 121*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_SHIFT 12 122*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_MASK 0x3000 123*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_SHIFT 16 124*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_MASK 0x30000 125*e65e175bSOded Gabbay 126*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_PWR_STAT_0 */ 127*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_SHIFT 0 128*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_MASK 0x1 129*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_SHIFT 1 130*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_MASK 0x2 131*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_SHIFT 4 132*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_MASK 0x30 133*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_SHIFT 8 134*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_MASK 0x300 135*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_SHIFT 12 136*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_MASK 0x1000 137*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_SHIFT 13 138*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_MASK 0x2000 139*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_SHIFT 16 140*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_MASK 0x30000 141*e65e175bSOded Gabbay 142*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_PWR_STAT_1 */ 143*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_SHIFT 0 144*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_MASK 0x3 145*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_SHIFT 4 146*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_MASK 0x30 147*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_SHIFT 8 148*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_MASK 0x300 149*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_SHIFT 12 150*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_MASK 0x3000 151*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_SHIFT 16 152*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_MASK 0x30000 153*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_SHIFT 20 154*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_MASK 0x300000 155*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_SHIFT 24 156*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_MASK 0x1000000 157*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_SHIFT 25 158*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_MASK 0x2000000 159*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_SHIFT 26 160*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_MASK 0x4000000 161*e65e175bSOded Gabbay 162*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_DBG_STATUS */ 163*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_SHIFT 0 164*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_MASK 0x3 165*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_SHIFT 4 166*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_MASK 0x30 167*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_SHIFT 8 168*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_MASK 0x300 169*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_SHIFT 12 170*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_MASK 0x3000 171*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_SHIFT 16 172*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_MASK 0x30000 173*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_SHIFT 20 174*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_MASK 0x300000 175*e65e175bSOded Gabbay 176*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_MEM_ATTR */ 177*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_SHIFT 0 178*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_MASK 0xFF 179*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_SHIFT 8 180*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_MASK 0xFF00 181*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_SHIFT 16 182*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_MASK 0x10000 183*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_SHIFT 20 184*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_MASK 0x100000 185*e65e175bSOded Gabbay 186*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_PMU */ 187*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PMU_EVENT_SHIFT 0 188*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_PMU_EVENT_MASK 0x3FFFFFFF 189*e65e175bSOded Gabbay 190*e65e175bSOded Gabbay #endif /* ASIC_REG_CPU_CA53_CFG_MASKS_H_ */ 191