1*0fdebc5eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2*0fdebc5eSThomas Gleixner /* Orion CPU Bridge Registers */ 3c22c2c60SArnd Bergmann 4c22c2c60SArnd Bergmann #ifndef __ASM_ARCH_BRIDGE_REGS_H 5c22c2c60SArnd Bergmann #define __ASM_ARCH_BRIDGE_REGS_H 6c22c2c60SArnd Bergmann 7c22c2c60SArnd Bergmann #include "orion5x.h" 8c22c2c60SArnd Bergmann 9c22c2c60SArnd Bergmann #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) 10c22c2c60SArnd Bergmann 11c22c2c60SArnd Bergmann #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) 12c22c2c60SArnd Bergmann 13c22c2c60SArnd Bergmann #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) 14c22c2c60SArnd Bergmann #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108) 15c22c2c60SArnd Bergmann 16c22c2c60SArnd Bergmann #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) 17c22c2c60SArnd Bergmann 18c22c2c60SArnd Bergmann #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) 19c22c2c60SArnd Bergmann 20c22c2c60SArnd Bergmann #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) 21c22c2c60SArnd Bergmann 22c22c2c60SArnd Bergmann #define BRIDGE_INT_TIMER1_CLR (~0x0004) 23c22c2c60SArnd Bergmann 24c22c2c60SArnd Bergmann #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) 25c22c2c60SArnd Bergmann 26c22c2c60SArnd Bergmann #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) 27c22c2c60SArnd Bergmann 28c22c2c60SArnd Bergmann #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) 29c22c2c60SArnd Bergmann #define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) 30c22c2c60SArnd Bergmann #endif 31