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/openbmc/u-boot/arch/powerpc/include/asm/
H A Dconfig_mpc85xx.h32 #define QE_MURAM_SIZE 0x10000UL
42 #define QE_MURAM_SIZE 0x20000UL
77 #define QE_MURAM_SIZE 0x6000UL
92 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
106 #define QE_MURAM_SIZE 0x6000UL
125 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
134 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
142 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
152 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
163 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
[all …]
/openbmc/u-boot/configs/
H A Domapl138_lcdk_defconfig3 CONFIG_SYS_TEXT_BASE=0xc1080000
5 CONFIG_SYS_DA850_PLL0_POSTDIV=0
6 CONFIG_SYS_DA850_PLL1_PLLDIV3=0x8003
21 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
46 CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000
H A Dda850evm_nand_defconfig3 CONFIG_SYS_TEXT_BASE=0xc1080000
8 CONFIG_SYS_MALLOC_F_LEN=0x800
50 CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000
/openbmc/qemu/tests/qemu-iotests/
H A D04625 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
60 local pattern=0
61 local cur_sec=0
63 for ((i=0;i<=$((sectors - 1));i++)); do
71 backing_io 0 32 write | $QEMU_IO "$TEST_IMG" | _filter_qemu_io
84 aio_write -P 10 0x18000 0x2000
87 aio_write -P 11 0x12000 0x2000
88 aio_write -P 12 0x1c000 0x2000
98 aio_write -P 20 0x28000 0x2000
[all …]
/openbmc/linux/sound/soc/intel/atom/sst/
H A Dsst_acpi.c38 #define SST_BYT_IRAM_PHY_START 0xff2c0000
39 #define SST_BYT_IRAM_PHY_END 0xff2d4000
40 #define SST_BYT_DRAM_PHY_START 0xff300000
41 #define SST_BYT_DRAM_PHY_END 0xff320000
42 #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
43 #define SST_BYT_IMR_VIRT_END 0xc01fffff
44 #define SST_BYT_SHIM_PHY_ADDR 0xff340000
45 #define SST_BYT_MBOX_PHY_ADDR 0xff344000
46 #define SST_BYT_DMA0_PHY_ADDR 0xff298000
47 #define SST_BYT_DMA1_PHY_ADDR 0xff29c000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,sm6350-rpmh.yaml66 reg = <0x01500000 0x28000>;
73 reg = <0x01620000 0x17080>;
/openbmc/linux/arch/powerpc/include/asm/
H A Dhydra.h30 char Pad1[0x30];
34 char Pad2[0x7fc4];
36 char SCSI_DMA[0x100];
37 char Pad3[0x300];
38 char SCCA_Tx_DMA[0x100];
39 char SCCA_Rx_DMA[0x100];
40 char SCCB_Tx_DMA[0x100];
41 char SCCB_Rx_DMA[0x100];
42 char Pad4[0x7800];
44 char SCSI[0x1000];
[all …]
/openbmc/linux/arch/mips/dec/prom/
H A Dmemory.c28 #define CHUNK_SIZE 0x400000
33 char old_handler[0x80]; in pmax_setup_memory_region()
37 memcpy(&old_handler, (void *)(CKSEG0 + 0x80), 0x80); in pmax_setup_memory_region()
38 memcpy((void *)(CKSEG0 + 0x80), &genexcept_early, 0x80); in pmax_setup_memory_region()
46 mem_err == 0 && memory_page < (unsigned char *)CKSEG1 + 0x1e00000; in pmax_setup_memory_region()
50 memcpy((void *)(CKSEG0 + 0x80), &old_handler, 0x80); in pmax_setup_memory_region()
52 memblock_add(0, (unsigned long)memory_page - CKSEG1 - CHUNK_SIZE); in pmax_setup_memory_region()
62 unsigned long mem_start = 0, mem_size = 0; in rex_setup_memory_region()
66 bm = (memmap *)CKSEG0ADDR(0x28000); in rex_setup_memory_region()
70 for (i = 0; i < bitmap_size; i++) { in rex_setup_memory_region()
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman-0.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x40 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
[all …]
H A Dqoriq-fman-1.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x60 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
56 reg = <0x81000 0x1000>;
60 cell-index = <0x2>;
[all …]
H A Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h11 #define ROMCP_ARB_BASE_ADDR 0x00000000
12 #define ROMCP_ARB_END_ADDR 0x000FFFFF
15 #define GPU_2D_ARB_BASE_ADDR 0x02200000
16 #define GPU_2D_ARB_END_ADDR 0x02203FFF
17 #define OPENVG_ARB_BASE_ADDR 0x02204000
18 #define OPENVG_ARB_END_ADDR 0x02207FFF
20 #define CAAM_ARB_BASE_ADDR 0x00100000
21 #define CAAM_ARB_END_ADDR 0x00107FFF
22 #define GPU_ARB_BASE_ADDR 0x01800000
23 #define GPU_ARB_END_ADDR 0x01803FFF
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sc7280-adsp-pil.yaml153 reg = <0x03000000 0x5000>,
154 <0x0355b000 0x10>;
157 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
176 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
180 qcom,smem-states = <&adsp_smp2p_out 0>;
H A Dqcom,sc7280-mss-pil.yaml216 reg = <0x04080000 0x10000>, <0x04180000 0x48>;
219 iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
221 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
224 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
248 qcom,smem-states = <&modem_smp2p_out 0>;
255 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
256 qcom,ext-regs = <&tcsr 0x10000 0x10004>, <&tcsr_mutex 0x26004 0x26008>;
257 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_6_2_sc7180.h12 .max_mixer_blendstages = 0x9,
22 .base = 0x0, .len = 0x494,
24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
26 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
28 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
35 .base = 0x1000, .len = 0x1dc,
40 .base = 0x1200, .len = 0x1dc,
45 .base = 0x1400, .len = 0x1dc,
[all …]
H A Ddpu_6_4_sm6350.h13 .max_mixer_blendstages = 0x7,
24 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
28 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
30 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
37 .base = 0x1000, .len = 0x1dc,
42 .base = 0x1200, .len = 0x1dc,
47 .base = 0x1400, .len = 0x1dc,
[all …]
/openbmc/linux/drivers/net/ethernet/hisilicon/hns3/hns3vf/
H A Dhclgevf_main.h20 #define HCLGEVF_MISC_VECTOR_NUM 0
22 #define HCLGEVF_INVALID_VPORT 0xffff
32 #define HCLGEVF_VECTOR_REG_BASE 0x20000
33 #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400
34 #define HCLGEVF_VECTOR_REG_OFFSET 0x4
35 #define HCLGEVF_VECTOR_VF_OFFSET 0x100000
38 #define HCLGEVF_GRO_EN_REG 0x28000
39 #define HCLGEVF_RXD_ADV_LAYOUT_EN_REG 0x28008
42 #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000
43 #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun50i-a64.dtsi84 #size-cells = <0>;
86 cpu0: cpu@0 {
89 reg = <0>;
132 #clock-cells = <0>;
139 #clock-cells = <0>;
146 #clock-cells = <0>;
172 #sound-dai-cells = <0>;
196 reg = <0x1000000 0x400000>;
200 ranges = <0 0x1000000 0x400000>;
202 display_clocks: clock@0 {
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9261.dtsi38 #size-cells = <0>;
40 cpu@0 {
43 reg = <0>;
49 reg = <0x20000000 0x08000000>;
55 #clock-cells = <0>;
56 clock-frequency = <0>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
68 reg = <0x00300000 0x28000>;
71 ranges = <0 0x00300000 0x28000>;
[all …]
/openbmc/linux/sound/pci/au88x0/
H A Dau8810.h11 #define NR_ADB 0x10
12 #define NR_WT 0x00
13 #define NR_SRC 0x10
14 #define NR_A3D 0x10
15 #define NR_MIXIN 0x20
16 #define NR_MIXOUT 0x10
20 #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
21 #define POS_MASK 0x00000fff
22 #define POS_SHIFT 0x0
23 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc885ads.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xff000100 0x40>;
48 0x0 0x0 0xfe000000 0x800000
49 0x1 0x0 0xff080000 0x8000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dfsl-fman.txt28 FMan block. The offset is 0xc4 from the beginning of the
29 Frame Processing Manager memory map (0xc3000 from the
44 DEVDISR[1] 1 0
49 DCFG_DEVDISR2[6] 1 0
56 DCFG_CCSR_DEVDISR2[24] 1 0
148 muram@0 {
150 ranges = <0 0x000000 0x28000>;
215 cell-index = <0x28>;
217 reg = <0xa8000 0x1000>;
221 cell-index = <0x8>;
[all …]
/openbmc/linux/Documentation/sound/hd-audio/
H A Dintel-multi-link.rst16 External HDAudio codecs are handled with link #0, while iDISP codec
20 LCAP.ALT=0x0 - since the ALT bit was previously reserved, this is a
33 | ML cap #0 |
38 +--> 0x0 +---------------+ LCAP
39 | ALT=0 |
54 0x4 +---------------+ LCTL
64 0x8 +---------------+ LOSIDV
72 0xC +---------------+ LSDIID
84 LEPTR.ID=0.
98 ML address, with a default value of 0x30000.
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmmio.c15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap4-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]

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