1e2cb1decSSalil Mehta /* SPDX-License-Identifier: GPL-2.0+ */
2e2cb1decSSalil Mehta /* Copyright (c) 2016-2017 Hisilicon Limited. */
3e2cb1decSSalil Mehta
4e2cb1decSSalil Mehta #ifndef __HCLGEVF_MAIN_H
5e2cb1decSSalil Mehta #define __HCLGEVF_MAIN_H
6e2cb1decSSalil Mehta #include <linux/fs.h>
7fe4144d4SJian Shen #include <linux/if_vlan.h>
8e2cb1decSSalil Mehta #include <linux/types.h>
9cd624299SYufeng Mo #include <net/devlink.h>
10e2cb1decSSalil Mehta #include "hclge_mbx.h"
11e2cb1decSSalil Mehta #include "hclgevf_cmd.h"
12e2cb1decSSalil Mehta #include "hnae3.h"
13027733b1SJie Wang #include "hclge_comm_rss.h"
144afc310cSJie Wang #include "hclge_comm_tqp_stats.h"
15e2cb1decSSalil Mehta
163c7624d8SXi Wang #define HCLGEVF_MOD_VERSION "1.0"
17e2cb1decSSalil Mehta #define HCLGEVF_DRIVER_NAME "hclgevf"
18e2cb1decSSalil Mehta
19b37ce587SYufeng Mo #define HCLGEVF_MAX_VLAN_ID 4095
20e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_NUM 0
21e2cb1decSSalil Mehta
22e2cb1decSSalil Mehta #define HCLGEVF_INVALID_VPORT 0xffff
23b37ce587SYufeng Mo #define HCLGEVF_GENERAL_TASK_INTERVAL 5
24b37ce587SYufeng Mo #define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL 2
25e2cb1decSSalil Mehta
26e2cb1decSSalil Mehta /* This number in actual depends upon the total number of VFs
27e2cb1decSSalil Mehta * created by physical function. But the maximum number of
28e2cb1decSSalil Mehta * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}.
29e2cb1decSSalil Mehta */
30e2cb1decSSalil Mehta #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1)
31e2cb1decSSalil Mehta
32e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_BASE 0x20000
33e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400
34e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_OFFSET 0x4
35e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_VF_OFFSET 0x100000
36e2cb1decSSalil Mehta
371600c3e5SJian Shen /* bar registers for common func */
381600c3e5SJian Shen #define HCLGEVF_GRO_EN_REG 0x28000
3979664077SHuazhong Tan #define HCLGEVF_RXD_ADV_LAYOUT_EN_REG 0x28008
401600c3e5SJian Shen
411600c3e5SJian Shen /* bar registers for rcb */
421600c3e5SJian Shen #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000
431600c3e5SJian Shen #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004
441600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_NUM_REG 0x80008
451600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C
461600c3e5SJian Shen #define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014
471600c3e5SJian Shen #define HCLGEVF_RING_RX_TAIL_REG 0x80018
481600c3e5SJian Shen #define HCLGEVF_RING_RX_HEAD_REG 0x8001C
491600c3e5SJian Shen #define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020
501600c3e5SJian Shen #define HCLGEVF_RING_RX_OFFSET_REG 0x80024
511600c3e5SJian Shen #define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028
521600c3e5SJian Shen #define HCLGEVF_RING_RX_STASH_REG 0x80030
531600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_ERR_REG 0x80034
541600c3e5SJian Shen #define HCLGEVF_RING_TX_ADDR_L_REG 0x80040
551600c3e5SJian Shen #define HCLGEVF_RING_TX_ADDR_H_REG 0x80044
561600c3e5SJian Shen #define HCLGEVF_RING_TX_BD_NUM_REG 0x80048
571600c3e5SJian Shen #define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C
581600c3e5SJian Shen #define HCLGEVF_RING_TX_TC_REG 0x80050
591600c3e5SJian Shen #define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054
601600c3e5SJian Shen #define HCLGEVF_RING_TX_TAIL_REG 0x80058
611600c3e5SJian Shen #define HCLGEVF_RING_TX_HEAD_REG 0x8005C
621600c3e5SJian Shen #define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060
631600c3e5SJian Shen #define HCLGEVF_RING_TX_OFFSET_REG 0x80064
641600c3e5SJian Shen #define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068
651600c3e5SJian Shen #define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070
661600c3e5SJian Shen #define HCLGEVF_RING_TX_BD_ERR_REG 0x80074
671600c3e5SJian Shen #define HCLGEVF_RING_EN_REG 0x80090
681600c3e5SJian Shen
691600c3e5SJian Shen /* bar registers for tqp interrupt */
701600c3e5SJian Shen #define HCLGEVF_TQP_INTR_CTRL_REG 0x20000
711600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL0_REG 0x20100
721600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL1_REG 0x20200
731600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL2_REG 0x20300
741600c3e5SJian Shen #define HCLGEVF_TQP_INTR_RL_REG 0x20900
751600c3e5SJian Shen
76e2cb1decSSalil Mehta /* CMDQ register bits for RX event(=MBX event) */
77e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1
78b90fcc5bSHuazhong Tan /* RST register bits for RESET event */
79b90fcc5bSHuazhong Tan #define HCLGEVF_VECTOR0_RST_INT_B 2
80e2cb1decSSalil Mehta
81e2cb1decSSalil Mehta #define HCLGEVF_TQP_RESET_TRY_TIMES 10
826988eb2aSSalil Mehta /* Reset related Registers */
83aa5c4f17SHuazhong Tan #define HCLGEVF_RST_ING 0x20C00
84aa5c4f17SHuazhong Tan #define HCLGEVF_FUN_RST_ING_BIT BIT(0)
85aa5c4f17SHuazhong Tan #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5)
86aa5c4f17SHuazhong Tan #define HCLGEVF_CORE_RST_ING_BIT BIT(6)
87aa5c4f17SHuazhong Tan #define HCLGEVF_IMP_RST_ING_BIT BIT(7)
88aa5c4f17SHuazhong Tan #define HCLGEVF_RST_ING_BITS \
89aa5c4f17SHuazhong Tan (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \
90aa5c4f17SHuazhong Tan HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT)
91e2cb1decSSalil Mehta
9272e2fb07SHuazhong Tan #define HCLGEVF_VF_RST_ING 0x07008
9372e2fb07SHuazhong Tan #define HCLGEVF_VF_RST_ING_BIT BIT(16)
9472e2fb07SHuazhong Tan
95e140c798SYufeng Mo #define HCLGEVF_WAIT_RESET_DONE 100
96e140c798SYufeng Mo
97e2cb1decSSalil Mehta #define HCLGEVF_RSS_IND_TBL_SIZE 512
98e2cb1decSSalil Mehta
9987a9b2fdSYufeng Mo #define HCLGEVF_TQP_MEM_SIZE 0x10000
10087a9b2fdSYufeng Mo #define HCLGEVF_MEM_BAR 4
10187a9b2fdSYufeng Mo /* in the bar4, the first half is for roce, and the second half is for nic */
10287a9b2fdSYufeng Mo #define HCLGEVF_NIC_MEM_OFFSET(hdev) \
10387a9b2fdSYufeng Mo (pci_resource_len((hdev)->pdev, HCLGEVF_MEM_BAR) >> 1)
10487a9b2fdSYufeng Mo #define HCLGEVF_TQP_MEM_OFFSET(hdev, i) \
10587a9b2fdSYufeng Mo (HCLGEVF_NIC_MEM_OFFSET(hdev) + HCLGEVF_TQP_MEM_SIZE * (i))
10687a9b2fdSYufeng Mo
107e070c8b9SYufeng Mo #define HCLGEVF_MAC_MAX_FRAME 9728
108e070c8b9SYufeng Mo
109eddd9860SGuojia Liao #define HCLGEVF_STATS_TIMER_INTERVAL 36U
110db01afebSliuzhongzhu
111076bb537SJie Wang #define hclgevf_read_dev(a, reg) \
112076bb537SJie Wang hclge_comm_read_reg((a)->hw.io_base, reg)
113076bb537SJie Wang #define hclgevf_write_dev(a, reg, value) \
114076bb537SJie Wang hclge_comm_write_reg((a)->hw.io_base, reg, value)
115076bb537SJie Wang
116b90fcc5bSHuazhong Tan enum hclgevf_evt_cause {
117b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_RST,
118b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_MBX,
119b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_OTHER,
120b90fcc5bSHuazhong Tan };
121b90fcc5bSHuazhong Tan
122e2cb1decSSalil Mehta /* states of hclgevf device & tasks */
123e2cb1decSSalil Mehta enum hclgevf_states {
124e2cb1decSSalil Mehta /* device states */
125e2cb1decSSalil Mehta HCLGEVF_STATE_DOWN,
126e2cb1decSSalil Mehta HCLGEVF_STATE_DISABLED,
127862d969aSHuazhong Tan HCLGEVF_STATE_IRQ_INITED,
128acfc3d55SHuazhong Tan HCLGEVF_STATE_REMOVING,
12925d1817cSHuazhong Tan HCLGEVF_STATE_NIC_REGISTERED,
130fe735c84SHuazhong Tan HCLGEVF_STATE_ROCE_REGISTERED,
1310251d196SGuangbin Huang HCLGEVF_STATE_SERVICE_INITED,
132e2cb1decSSalil Mehta /* task states */
13335a1e503SSalil Mehta HCLGEVF_STATE_RST_SERVICE_SCHED,
13435a1e503SSalil Mehta HCLGEVF_STATE_RST_HANDLING,
135e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_SERVICE_SCHED,
136e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_HANDLING,
137ff200099SYunsheng Lin HCLGEVF_STATE_LINK_UPDATING,
138c631c696SJian Shen HCLGEVF_STATE_PROMISC_CHANGED,
139d5432455SGuojia Liao HCLGEVF_STATE_RST_FAIL,
14001305e16SGuangbin Huang HCLGEVF_STATE_PF_PUSH_LINK_STATUS,
141e2cb1decSSalil Mehta };
142e2cb1decSSalil Mehta
143e2cb1decSSalil Mehta struct hclgevf_mac {
144c136b884SPeng Li u8 media_type;
14588d10bd6SJian Shen u8 module_type;
146e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN];
147e2cb1decSSalil Mehta int link;
1484a152de9SFuyun Liang u8 duplex;
1494a152de9SFuyun Liang u32 speed;
1509194d18bSliuzhongzhu u64 supported;
1519194d18bSliuzhongzhu u64 advertising;
152e2cb1decSSalil Mehta };
153e2cb1decSSalil Mehta
154e2cb1decSSalil Mehta struct hclgevf_hw {
155076bb537SJie Wang struct hclge_comm_hw hw;
156e2cb1decSSalil Mehta int num_vec;
157e2cb1decSSalil Mehta struct hclgevf_mac mac;
158e2cb1decSSalil Mehta };
159e2cb1decSSalil Mehta
160e2cb1decSSalil Mehta struct hclgevf_cfg {
161e2cb1decSSalil Mehta u8 tc_num;
162e2cb1decSSalil Mehta u16 tqp_desc_num;
163e2cb1decSSalil Mehta u16 rx_buf_len;
164e2cb1decSSalil Mehta u8 phy_addr;
165e2cb1decSSalil Mehta u8 media_type;
166e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN];
167e2cb1decSSalil Mehta u32 numa_node_map;
168e2cb1decSSalil Mehta };
169e2cb1decSSalil Mehta
170e2cb1decSSalil Mehta struct hclgevf_misc_vector {
171e2cb1decSSalil Mehta u8 __iomem *addr;
172e2cb1decSSalil Mehta int vector_irq;
173f97c4d82SYonglong Liu char name[HNAE3_INT_NAME_LEN];
174e2cb1decSSalil Mehta };
175e2cb1decSSalil Mehta
176c88a6e7dSHuazhong Tan struct hclgevf_rst_stats {
177c88a6e7dSHuazhong Tan u32 rst_cnt; /* the number of reset */
178c88a6e7dSHuazhong Tan u32 vf_func_rst_cnt; /* the number of VF function reset */
179c88a6e7dSHuazhong Tan u32 flr_rst_cnt; /* the number of FLR */
180c88a6e7dSHuazhong Tan u32 vf_rst_cnt; /* the number of VF reset */
181c88a6e7dSHuazhong Tan u32 rst_done_cnt; /* the number of reset completed */
182c88a6e7dSHuazhong Tan u32 hw_rst_done_cnt; /* the number of HW reset completed */
183bbe6540eSHuazhong Tan u32 rst_fail_cnt; /* the number of VF reset fail */
184c88a6e7dSHuazhong Tan };
185c88a6e7dSHuazhong Tan
186ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE {
187ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC,
188ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC
189ee4bcd3bSJian Shen };
190ee4bcd3bSJian Shen
191ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE {
192ee4bcd3bSJian Shen HCLGEVF_MAC_TO_ADD,
193ee4bcd3bSJian Shen HCLGEVF_MAC_TO_DEL,
194ee4bcd3bSJian Shen HCLGEVF_MAC_ACTIVE
195ee4bcd3bSJian Shen };
196ee4bcd3bSJian Shen
197ee4bcd3bSJian Shen struct hclgevf_mac_addr_node {
198ee4bcd3bSJian Shen struct list_head node;
199ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state;
200ee4bcd3bSJian Shen u8 mac_addr[ETH_ALEN];
201ee4bcd3bSJian Shen };
202ee4bcd3bSJian Shen
203ee4bcd3bSJian Shen struct hclgevf_mac_table_cfg {
204ee4bcd3bSJian Shen spinlock_t mac_list_lock; /* protect mac address need to add/detele */
205ee4bcd3bSJian Shen struct list_head uc_mac_list;
206ee4bcd3bSJian Shen struct list_head mc_mac_list;
207ee4bcd3bSJian Shen };
208ee4bcd3bSJian Shen
209e2cb1decSSalil Mehta struct hclgevf_dev {
210e2cb1decSSalil Mehta struct pci_dev *pdev;
211e2cb1decSSalil Mehta struct hnae3_ae_dev *ae_dev;
212e2cb1decSSalil Mehta struct hclgevf_hw hw;
213e2cb1decSSalil Mehta struct hclgevf_misc_vector misc_vector;
214027733b1SJie Wang struct hclge_comm_rss_cfg rss_cfg;
215e2cb1decSSalil Mehta unsigned long state;
2166ff3cf07SHuazhong Tan unsigned long flr_state;
217720bd583SHuazhong Tan unsigned long default_reset_request;
2180742ed7cSHuazhong Tan unsigned long last_reset_time;
2190742ed7cSHuazhong Tan enum hnae3_reset_type reset_level;
220dea846e8SHuazhong Tan unsigned long reset_pending;
221dea846e8SHuazhong Tan enum hnae3_reset_type reset_type;
222fbcad948SJijie Shao struct timer_list reset_timer;
223e2cb1decSSalil Mehta
224436667d2SSalil Mehta #define HCLGEVF_RESET_REQUESTED 0
225436667d2SSalil Mehta #define HCLGEVF_RESET_PENDING 1
226436667d2SSalil Mehta unsigned long reset_state; /* requested, pending */
227c88a6e7dSHuazhong Tan struct hclgevf_rst_stats rst_stats;
228436667d2SSalil Mehta u32 reset_attempts;
229f28368bbSHuazhong Tan struct semaphore reset_sem; /* protect reset process */
230436667d2SSalil Mehta
231e2cb1decSSalil Mehta u32 fw_version;
23232e6d104SJian Shen u16 mbx_api_version;
233ec4d9392SHuazhong Tan u16 num_tqps; /* num task queue pairs of this VF */
234e2cb1decSSalil Mehta
235e2cb1decSSalil Mehta u16 alloc_rss_size; /* allocated RSS task queue */
236e2cb1decSSalil Mehta u16 rss_size_max; /* HW defined max RSS task queue */
237e2cb1decSSalil Mehta
238e2cb1decSSalil Mehta u16 num_alloc_vport; /* num vports this driver supports */
2398ed43906SPeiyang Wang nodemask_t numa_node_mask;
240e2cb1decSSalil Mehta u16 rx_buf_len;
241c0425944SPeng Li u16 num_tx_desc; /* desc num of per tx queue */
242c0425944SPeng Li u16 num_rx_desc; /* desc num of per rx queue */
243e2cb1decSSalil Mehta u8 hw_tc_map;
2448e6de441SHuazhong Tan u8 has_pf_mac;
245e2cb1decSSalil Mehta
246e2cb1decSSalil Mehta u16 num_msi;
247e2cb1decSSalil Mehta u16 num_msi_left;
248e2cb1decSSalil Mehta u16 num_msi_used;
249580a05f9SYonglong Liu u16 num_nic_msix; /* Num of nic vectors for this VF */
25007acf909SJian Shen u16 num_roce_msix; /* Num of roce vectors for this VF */
25107acf909SJian Shen u16 roce_base_msix_offset;
252e2cb1decSSalil Mehta u16 *vector_status;
253e2cb1decSSalil Mehta int *vector_irq;
254e2cb1decSSalil Mehta
2553462207dSYufeng Mo bool gro_en;
2563462207dSYufeng Mo
257fe4144d4SJian Shen unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
258fe4144d4SJian Shen
259ee4bcd3bSJian Shen struct hclgevf_mac_table_cfg mac_table;
260ee4bcd3bSJian Shen
261e2cb1decSSalil Mehta struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */
26207a0556aSSalil Mehta struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */
263e2cb1decSSalil Mehta
264b3c3fe8eSYunsheng Lin struct delayed_work service_task;
265e2cb1decSSalil Mehta
2664afc310cSJie Wang struct hclge_comm_tqp *htqp;
267e2cb1decSSalil Mehta
268e2cb1decSSalil Mehta struct hnae3_handle nic;
269e2cb1decSSalil Mehta struct hnae3_handle roce;
270e2cb1decSSalil Mehta
271e2cb1decSSalil Mehta struct hnae3_client *nic_client;
272e2cb1decSSalil Mehta struct hnae3_client *roce_client;
273e2cb1decSSalil Mehta u32 flag;
274ff200099SYunsheng Lin unsigned long serv_processed_cnt;
275ff200099SYunsheng Lin unsigned long last_serv_processed;
276cd624299SYufeng Mo
277cd624299SYufeng Mo struct devlink *devlink;
278e2cb1decSSalil Mehta };
279e2cb1decSSalil Mehta
hclgevf_is_reset_pending(struct hclgevf_dev * hdev)280ef5f8e50SHuazhong Tan static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev)
281ef5f8e50SHuazhong Tan {
282ef5f8e50SHuazhong Tan return !!hdev->reset_pending;
283ef5f8e50SHuazhong Tan }
284ef5f8e50SHuazhong Tan
285d3410018SYufeng Mo int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev,
286d3410018SYufeng Mo struct hclge_vf_to_pf_msg *send_msg, bool need_resp,
287e2cb1decSSalil Mehta u8 *resp_data, u16 resp_len);
288e2cb1decSSalil Mehta void hclgevf_mbx_handler(struct hclgevf_dev *hdev);
28907a0556aSSalil Mehta void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev);
29007a0556aSSalil Mehta
291e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state);
2924a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
2934a152de9SFuyun Liang u8 duplex);
29435a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev);
29507a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev);
29692f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
297767975e5SJie Wang struct hclge_mbx_port_base_vlan *port_base_vlan);
298939ccd10SJijie Shao struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle);
299e2cb1decSSalil Mehta #endif
300