Lines Matching +full:0 +full:x28000
32 #define QE_MURAM_SIZE 0x10000UL
42 #define QE_MURAM_SIZE 0x20000UL
77 #define QE_MURAM_SIZE 0x6000UL
92 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
106 #define QE_MURAM_SIZE 0x6000UL
125 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
134 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
142 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
152 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
163 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
171 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
180 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
189 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
200 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
206 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
212 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
213 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
222 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
223 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
224 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
225 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
258 #define CONFIG_SYS_PME_CLK 0
263 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
265 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
279 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
288 #define CONFIG_SYS_FM1_CLK 0
294 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
319 #define CONFIG_SYS_NUM_FM1_10GEC 0
339 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
342 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
349 #define QE_MURAM_SIZE 0x6000UL
369 #define CONFIG_SYS_FM1_CLK 0
370 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
373 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
380 #define QE_MURAM_SIZE 0x6000UL
409 #define CONFIG_SYS_FM1_CLK 0
415 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
417 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
431 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000