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/openbmc/u-boot/board/nvidia/venice2/
H A Das3722_init.h9 #define AS3722_I2C_ADDR 0x80
11 #define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
12 #define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
13 #define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
14 #define AS3722_SDCONTROL_REG 0x4D
16 #define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
17 #define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
18 #define AS3722_LDCONTROL_REG 0x4E
21 #define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
23 #define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
[all …]
/openbmc/u-boot/include/configs/
H A DMCR3000.h13 "sdram_type=SDRAM\0" \
14 "flash_type=AM29LV160DB\0" \
15 "loadaddr=0x400000\0" \
16 "filename=uImage.lzma\0" \
17 "nfsroot=/opt/ofs\0" \
18 "dhcp_ip=ip=:::::eth0:dhcp\0" \
19 "console_args=console=ttyCPM0,115200N8\0" \
25 "bootm 0x04060000 - 0x04050000\0" \
32 "tftp 0xf00000 mcr3000.dtb;" \
33 "bootm ${loadaddr} - 0xf00000\0" \
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h12 #define REGS_AHB0_BASE 0x01C00000
13 #define REGS_AHB1_BASE 0x00800000
14 #define REGS_AHB2_BASE 0x03000000
15 #define REGS_APB0_BASE 0x06000000
16 #define REGS_APB1_BASE 0x07000000
17 #define REGS_RCPUS_BASE 0x08000000
19 #define SUNXI_SRAM_D_BASE 0x08100000
22 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
23 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
25 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dgaudi2_blocks_linux_driver.h16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
/openbmc/u-boot/board/toradex/apalis-tk1/
H A Das3722_init.h8 #define AS3722_I2C_ADDR 0x80
10 #define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
11 #define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
12 #define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
13 #define AS3722_SDCONTROL_REG 0x4D
15 #define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */
16 #define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
17 #define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */
18 #define AS3722_LDCONTROL_REG 0x4E
20 #define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
/openbmc/phosphor-logging/extensions/openpower-pels/registry/
H A Dmessage_registry.json9 "ReasonCode": "0x1001",
31 "ReasonCode": "0x1002",
52 "ReasonCode": "0x1003",
68 "ReasonCode": "0x1004",
85 "ReasonCode": "0x1005",
102 "ReasonCode": "0x1006",
117 "ReasonCode": "0x1007",
146 "ReasonCode": "0x1008",
175 "ReasonCode": "0x1009",
204 "ReasonCode": "0x100A",
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp153.dtsi35 reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
42 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
48 reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
55 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
H A Dstm32mp133.dtsi13 reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
20 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
26 reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
33 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
39 reg = <0x48003000 0x400>;
46 #size-cells = <0>;
49 adc1: adc@0 {
53 #size-cells = <0>;
54 reg = <0x0>;
56 interrupts = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/power/supply/
H A Dqcom,pm8941-coincell.yaml59 #size-cells = <0>;
63 reg = <0x2800>;
/openbmc/linux/arch/mips/pci/
H A Dpci-generic.c14 * addresses to be allocated in the 0x000-0x0ff region
15 * modulo 0x400.
18 * the low 10 bits of the IO address. The 0x00-0xff region
20 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
21 * but we want to try to avoid allocating at 0x2900-0x2bff
22 * which might have be mirrored at 0x0100-0x03ff..
31 if (res->flags & IORESOURCE_IO && start & 0x300) in pcibios_align_resource()
32 start = (start + 0x3ff) & ~0x3ff; in pcibios_align_resource()
55 if (res->start != 0) { in pci_remap_iospace()
62 return 0; in pci_remap_iospace()
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc5125twr.dts30 #size-cells = <0>;
32 PowerPC,5125@0 {
34 reg = <0>;
35 d-cache-line-size = <0x20>; // 32 bytes
36 i-cache-line-size = <0x20>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
47 reg = <0x00000000 0x10000000>; // 256MB at 0
52 reg = <0x30000000 0x08000>; // 32K at 0x30000000
57 #size-cells = <0>;
[all …]
/openbmc/linux/arch/xtensa/kernel/
H A Dpci.c30 * addresses to be allocated in the 0x000-0x0ff region
31 * modulo 0x400.
34 * the low 10 bits of the IO address. The 0x00-0xff region
36 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
37 * but we want to try to avoid allocating at 0x2900-0x2bff
38 * which might have be mirrored at 0x0100-0x03ff..
48 if (size > 0x100) { in pcibios_align_resource()
54 if (start & 0x300) in pcibios_align_resource()
55 start = (start + 0x3ff) & ~0x3ff; in pcibios_align_resource()
86 return 0; in pci_iobar_pfn()
/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dqspi.h14 u16 mr; /* 0x00 Mode */
16 u16 dlyr; /* 0x04 Delay */
18 u16 wr; /* 0x08 Wrap */
20 u16 ir; /* 0x0C Interrupt */
22 u16 ar; /* 0x10 Address */
24 u16 dr; /* 0x14 Data */
29 #define QSPI_QMR_MSTR (0x8000)
30 #define QSPI_QMR_DOHIE (0x4000)
31 #define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
32 #define QSPI_QMR_BITS_MASK (0xC3FF)
[all …]
/openbmc/linux/arch/m68k/kernel/
H A Dpcibios.c19 * addresses to be allocated in the 0x000-0x0ff region
20 * modulo 0x400.
23 * the low 10 bits of the IO address. The 0x00-0xff region
25 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
26 * but we want to try to avoid allocating at 0x2900-0x2bff
27 * which might be mirrored at 0x0100-0x03ff..
34 if ((res->flags & IORESOURCE_IO) && (start & 0x300)) in pcibios_align_resource()
35 start = (start + 0x3ff) & ~0x3ff; in pcibios_align_resource()
54 for (idx = 0; idx < 6; idx++) { in pcibios_enable_device()
79 pr_info("PCI: enabling device %s (0x%04x -> 0x%04x)\n", in pcibios_enable_device()
[all …]
/openbmc/linux/sound/soc/amd/acp/
H A Dchip_offset_byte.h14 #define ACPAXI2AXI_ATU_CTRL 0xC40
15 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC20
16 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC24
18 #define ACP_PGFSM_CONTROL 0x141C
19 #define ACP_PGFSM_STATUS 0x1420
20 #define ACP_SOFT_RESET 0x1000
21 #define ACP_CONTROL 0x1004
24 (adata->acp_base + adata->rsrc->irq_reg_offset + offset + (ctrl * 0x04))
26 #define ACP_EXTERNAL_INTR_ENB(adata) ACP_EXTERNAL_INTR_REG_ADDR(adata, 0x0, 0x0)
27 #define ACP_EXTERNAL_INTR_CNTL(adata, ctrl) ACP_EXTERNAL_INTR_REG_ADDR(adata, 0x4, ctrl)
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dbrcmu_d11.h20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
23 #define BRCMU_CHSPEC_CH_MASK 0x00ff
24 #define BRCMU_CHSPEC_CH_SHIFT 0
25 #define BRCMU_CHSPEC_CHL_MASK 0x000f
26 #define BRCMU_CHSPEC_CHL_SHIFT 0
27 #define BRCMU_CHSPEC_CHH_MASK 0x00f0
36 #define BRCMU_CHSPEC_D11N_SB_MASK 0x0300
38 #define BRCMU_CHSPEC_D11N_SB_L 0x0100 /* control lower */
39 #define BRCMU_CHSPEC_D11N_SB_U 0x0200 /* control upper */
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dpm8998.dtsi35 pm8998_lsid0: pmic@0 {
37 reg = <0x0 SPMI_USID>;
39 #size-cells = <0>;
44 reg = <0x800>;
45 mode-bootloader = <0x2>;
46 mode-recovery = <0x1>;
50 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
58 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
67 reg = <0x2400>;
68 interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
[all …]
/openbmc/linux/drivers/tty/serial/8250/
H A D8250_acorn.c54 info->vaddr = ecardm_iomap(ec, type->type, 0, 0); in serial_card_probe()
62 memset(&uart, 0, sizeof(struct uart_8250_port)); in serial_card_probe()
70 for (i = 0; i < info->num_ports; i++) { in serial_card_probe()
77 return 0; in serial_card_probe()
87 for (i = 0; i < info->num_ports; i++) in serial_card_remove()
88 if (info->ports[i] > 0) in serial_card_remove()
98 .offset = { 0x2800, 0x2400, 0x2000 },
105 .offset = { 0x2000, 0x2020 },
111 { 0xffff, 0xffff }
/openbmc/linux/include/linux/
H A Dkbd_kern.h36 #define LED_SHOW_FLAGS 0 /* traditional state */
41 #define VC_SCROLLOCK 0 /* scroll-lock mode */
47 #define VC_XLATE 0 /* translate keycodes using keymap */
54 #define VC_APPLIC 0 /* application key mode */
57 #define VC_CRLF 3 /* 0 - enter sends CR, 1 - enter sends CRLF */
58 #define VC_META 4 /* 0 - meta, 1 - meta=prefix with ESC */
122 #define U(x) ((x) ^ 0xf000)
124 #define BRL_UC_ROW 0x2800
/openbmc/u-boot/fs/ext4/
H A Dcrc16.c13 /** CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1) */
15 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
16 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
17 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
18 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
19 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
20 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
21 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
22 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
23 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/linux/lib/
H A Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/u-boot/fs/ubifs/
H A Dcrc16.c11 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
13 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
14 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
15 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
16 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
17 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
18 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
19 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
20 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
21 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-digctl.h15 mxs_reg_32(hw_digctl_ctrl) /* 0x000 */
16 mxs_reg_32(hw_digctl_status) /* 0x010 */
17 mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */
18 mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */
19 mxs_reg_32(hw_digctl_emi_status) /* 0x040 */
20 mxs_reg_32(hw_digctl_read_margin) /* 0x050 */
21 uint32_t hw_digctl_writeonce; /* 0x060 */
23 mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */
24 mxs_reg_32(hw_digctl_bist_status) /* 0x080 */
25 uint32_t hw_digctl_entropy; /* 0x090 */
[all …]
/openbmc/linux/arch/mips/include/asm/mach-ar7/
H A Dar7.h16 #define AR7_SDRAM_BASE 0x14000000
18 #define AR7_REGS_BASE 0x08610000
20 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
21 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
22 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
23 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
24 #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
25 #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
26 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
27 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
[all …]

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