Home
last modified time | relevance | path

Searched +full:0 +full:x2100 (Results 1 – 25 of 171) sorted by relevance

1234567

/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dingenic,pinctrl.yaml18 which the pin is associated and N is an integer from 0 to 31 identifying the
22 pins. The X2000 and the X2100 contains 5 GPIO ports, PA to PE, for a total of
47 - ingenic,x2100-pinctrl
65 const: 0
68 "^gpio@[0-9]$":
86 - ingenic,x2100-gpio
170 reg = <0x10010000 0x600>;
173 #size-cells = <0>;
175 gpio@0 {
177 reg = <0>;
[all …]
/openbmc/linux/arch/arm/mach-mv78xx0/
H A Dmv78xx0.h17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
[all …]
/openbmc/linux/drivers/isdn/hardware/mISDN/
H A Dhfc_pci.h16 #define HFCPCI_BTRANS_THRESMASK 0x00
19 #define PCI_ENA_MEMIO 0x02
20 #define PCI_ENA_MASTER 0x04
23 #define HCFPCI_C_I 0x08
24 #define HFCPCI_TRxR 0x0C
25 #define HFCPCI_MON1_D 0x28
26 #define HFCPCI_MON2_D 0x2C
29 #define HFCPCI_B1_SSL 0x80
30 #define HFCPCI_B2_SSL 0x84
31 #define HFCPCI_AUX1_SSL 0x88
[all …]
/openbmc/linux/arch/mips/generic/
H A Dboard-ingenic.c28 return "X2100"; in ingenic_get_system_type()
64 #define INGENIC_CGU_BASE 0x10000000
77 if (offset < 0) in ingenic_force_12M_ext()
94 cgu = ioremap(INGENIC_CGU_BASE, 0x4); in ingenic_force_12M_ext()
114 if (!fdt_node_check_compatible(fdt, 0, "qi,lb60") && in ingenic_fixup_fdt()
115 fdt_path_offset(fdt, "/memory") < 0) in ingenic_fixup_fdt()
116 early_init_dt_add_memory_arch(0, SZ_32M); in ingenic_fixup_fdt()
153 { .compatible = "ingenic,x2100", .data = (void *)MACH_INGENIC_X2100 },
181 return 0; in ingenic_pm_enter()
197 return 0; in ingenic_pm_init()
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddiu.txt20 reg = <0x2c000 100>;
28 reg = <0x2100 0x100>;
29 interrupts = <64 0x8>;
/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dsc64-regs.h12 #define SC_BASE_ADDR 0x61840000
14 #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
15 #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
16 #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
17 #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
18 #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
19 #define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018)
21 #define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
22 #define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
23 #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
[all …]
/openbmc/linux/arch/arm/mach-orion5x/
H A Dorion5x.h36 #define ORION5X_REGS_PHYS_BASE 0xf1000000
37 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000)
40 #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
41 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000
44 #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
45 #define ORION5X_PCI_IO_BUS_BASE 0x00010000
48 #define ORION5X_SRAM_PHYS_BASE (0xf2200000)
52 #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
53 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
56 #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
[all …]
/openbmc/linux/arch/mips/boot/dts/realtek/
H A Drtl83xx.dtsi14 #address-cells = <0>;
23 ranges = <0x0 0x18000000 0x10000>;
27 reg = <0x2000 0x100>;
44 reg = <0x2100 0x100>;
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/
H A D0005-Platform-CS1000-Increase-RSE_COMMS-buffer-size.patch25 -#define RSE_COMMS_PAYLOAD_MAX_SIZE (0x2100)
32 +#define RSE_COMMS_PAYLOAD_MAX_SIZE (0x43C0)
/openbmc/qemu/tests/tcg/s390x/
H A Dvistr.c23 .h[0] = 0x1234, .h[1] = 0x0056, .h[2] = 0x7800, .h[3] = 0x0000, in main()
24 .h[4] = 0x0078, .h[5] = 0x0000, .h[6] = 0x6543, .h[7] = 0x2100 in main()
27 .w[0] = 0x12340000, .w[1] = 0x78654300, in main()
28 .w[2] = 0x0, .w[3] = 0x12, in main()
31 vistr(&vd, &vs16, 1, 0); in main()
32 if (vd.h[0] != 0x1234 || vd.h[1] != 0x0056 || vd.h[2] != 0x7800 || in main()
38 vistr(&vd, &vs32, 2, 0); in main()
39 if (vd.w[0] != 0x12340000 || vd.w[1] != 0x78654300 || vd.w[2] || vd.w[3]) { in main()
44 return 0; in main()
/openbmc/linux/sound/soc/codecs/
H A Drt5514.h15 #define RT5514_DEVICE_ID 0x10ec5514
17 #define RT5514_RESET 0x2000
18 #define RT5514_PWR_ANA1 0x2004
19 #define RT5514_PWR_ANA2 0x2008
20 #define RT5514_I2S_CTRL1 0x2010
21 #define RT5514_I2S_CTRL2 0x2014
22 #define RT5514_VAD_CTRL6 0x2030
23 #define RT5514_EXT_VAD_CTRL 0x206c
24 #define RT5514_DIG_IO_CTRL 0x2070
25 #define RT5514_PAD_CTRL1 0x2080
[all …]
/openbmc/linux/drivers/phy/broadcom/
H A Dphy-bcm-ns2-pcie.c11 #define BLK_ADDR_REG_OFFSET 0x1f
12 #define PLL_AFE1_100MHZ_BLK 0x2100
13 #define PLL_CLK_AMP_OFFSET 0x03
14 #define PLL_CLK_AMP_2P05V 0x2b18
31 return 0; in ns2_pci_phy_init()
66 return 0; in ns2_pci_phy_probe()
/openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-pcie.dtsi8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
[all …]
/openbmc/linux/drivers/scsi/arm/
H A Dcumana_1.c39 #define CTRL 0x16fc
40 #define STAT 0x2004
41 #define L(v) (((v)<<16)|((v) & 0x0000ffff))
42 #define H(v) (((v)>>16)|((v) & 0xffff0000))
49 u8 __iomem *dma = hostdata->pdma_io + 0x2000; in cumanascsi_pwrite()
51 if(!len) return 0; in cumanascsi_pwrite()
53 writeb(0x02, base + CTRL); in cumanascsi_pwrite()
60 if(status & 0x80) in cumanascsi_pwrite()
62 if(!(status & 0x40)) in cumanascsi_pwrite()
73 if(len == 0) in cumanascsi_pwrite()
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_ti814x.c17 #define PRCM_MOD_EN 0x2
20 #define OSC_SRC0 0
32 #define SELFREQDCO_HS2 0x00000801
33 #define SELFREQDCO_HS1 0x00001001
35 #define MPU_N 0x1
36 #define MPU_M 0x3C
38 #define MPU_CLKCTRL 0x1
43 #define L3_CLKCTRL 0x801
48 #define DDR_CLKCTRL 0x801
51 #define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
[all …]
H A Dclock_ti816x.c33 #define CM_PLL_BASE (CTRL_BASE + 0x0400)
37 #define MAIN_P 0x1
38 #define MAIN_INTFREQ1 0x8
39 #define MAIN_FRACFREQ1 0x800000
40 #define MAIN_MDIV1 0x2
41 #define MAIN_INTFREQ2 0xE
42 #define MAIN_FRACFREQ2 0x0
43 #define MAIN_MDIV2 0x1
44 #define MAIN_INTFREQ3 0x8
45 #define MAIN_FRACFREQ3 0xAAAAB0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sm8250-venus.yaml113 reg = <0x0aa00000 0xff000>;
129 iommus = <&apps_smmu 0x2100 0x0400>;
/openbmc/linux/include/video/
H A Dtrident.h4 #define TRIDENTFB_DEBUG 0
20 #define CYBER9320 0x9320
21 #define CYBER9388 0x9388
22 #define CYBER9382 0x9382 /* the real PCI id for this is 9660 */
23 #define CYBER9385 0x9385 /* ditto */
24 #define CYBER9397 0x9397
25 #define CYBER9397DVD 0x939A
26 #define CYBER9520 0x9520
27 #define CYBER9525DVD 0x9525
28 #define TGUI9440 0x9440
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-overo-common-dvi.dtsi13 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
14 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
15 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
16 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
17 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
18 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
19 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
20 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
21 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
22 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
[all …]
H A Domap3-thunder.dts17 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
18 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
19 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
20 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
21 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
22 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
23 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
24 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
25 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
26 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
[all …]
/openbmc/linux/drivers/phy/renesas/
H A Dr8a779f0-ether-serdes.c18 #define R8A779F0_ETH_SERDES_OFFSET 0x0400
19 #define R8A779F0_ETH_SERDES_BANK_SELECT 0x03fc
78 for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { in r8a779f0_eth_serdes_common_init_ram()
80 ret = r8a779f0_eth_serdes_reg_wait(channel, 0x026c, 0x180, BIT(0), 0x01); in r8a779f0_eth_serdes_common_init_ram()
85 r8a779f0_eth_serdes_write32(dd->addr, 0x026c, 0x180, 0x03); in r8a779f0_eth_serdes_common_init_ram()
97 r8a779f0_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x0097); in r8a779f0_eth_serdes_common_setting()
98 r8a779f0_eth_serdes_write32(dd->addr, 0x01d0, 0x180, 0x0060); in r8a779f0_eth_serdes_common_setting()
99 r8a779f0_eth_serdes_write32(dd->addr, 0x01d8, 0x180, 0x2200); in r8a779f0_eth_serdes_common_setting()
100 r8a779f0_eth_serdes_write32(dd->addr, 0x01d4, 0x180, 0x0000); in r8a779f0_eth_serdes_common_setting()
101 r8a779f0_eth_serdes_write32(dd->addr, 0x01e0, 0x180, 0x003d); in r8a779f0_eth_serdes_common_setting()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da2xx_gpu.c18 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit()
42 OUT_RING(ring, 0x00000000); in a2xx_submit()
49 OUT_RING(ring, 0x80000000); in a2xx_submit()
58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
62 /* All fields present (bits 9:0) */ in a2xx_me_init()
63 OUT_RING(ring, 0x000003ff); in a2xx_me_init()
65 OUT_RING(ring, 0x00000000); in a2xx_me_init()
67 OUT_RING(ring, 0x00000000); in a2xx_me_init()
69 OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000); in a2xx_me_init()
70 OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000); in a2xx_me_init()
[all …]
/openbmc/linux/include/linux/soc/pxa/
H A Dcpu.h18 * PXA210 B0 0x69052922 0x2926C013
19 * PXA210 B1 0x69052923 0x3926C013
20 * PXA210 B2 0x69052924 0x4926C013
21 * PXA210 C0 0x69052D25 0x5926C013
23 * PXA250 A0 0x69052100 0x09264013
24 * PXA250 A1 0x69052101 0x19264013
25 * PXA250 B0 0x69052902 0x29264013
26 * PXA250 B1 0x69052903 0x39264013
27 * PXA250 B2 0x69052904 0x49264013
28 * PXA250 C0 0x69052D05 0x59264013
[all …]
/openbmc/linux/drivers/mfd/
H A Dsi476x-prop.c25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array()
38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range()
49 0x0000, in si476x_core_is_valid_property_a10()
50 0x0500, 0x0501, in si476x_core_is_valid_property_a10()
51 0x0600, in si476x_core_is_valid_property_a10()
52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10()
53 0x0718, in si476x_core_is_valid_property_a10()
54 0x1207, 0x1208, in si476x_core_is_valid_property_a10()
55 0x2007, in si476x_core_is_valid_property_a10()
56 0x2300, in si476x_core_is_valid_property_a10()
[all …]

1234567