17 #define PRCM_MOD_EN		0x2
20 #define OSC_SRC0		0
32 #define SELFREQDCO_HS2		0x00000801
33 #define SELFREQDCO_HS1		0x00001001
35 #define MPU_N			0x1
36 #define MPU_M			0x3C
38 #define MPU_CLKCTRL		0x1
43 #define L3_CLKCTRL		0x801
48 #define DDR_CLKCTRL		0x801
51 #define ADPLLJ_CLKCTRL_HS2	0x00000801 /* HS2 mode, TINT2 = 1 */
52 #define ADPLLJ_CLKCTRL_HS1	0x00001001 /* HS1 mode, TINT2 = 1 */
61 #define ADPLLJ_CLKCTRL_TINITZ		(1 << 0)
72 #define ADPLLJ_STATUS_BYPASS		(1 << 0)
76 #define ADPLLJ_TENABLE_ENB		(1 << 0)
77 #define ADPLLJ_TENABLEDIV_ENB		(1 << 0)
81 #define MPU_PLL_BASE			(PLL_SUBSYS_BASE + 0x048)
82 #define L3_PLL_BASE			(PLL_SUBSYS_BASE + 0x110)
83 #define DDR_PLL_BASE			(PLL_SUBSYS_BASE + 0x290)
100 #define OSC_SRC_CTRL			(PLL_SUBSYS_BASE + 0x2C0)
102 #define ENET_CLKCTRL_CMPL		0x30000
104 #define SATA_PLL_BASE			(CTRL_BASE + 0x0720)
118 #define SEL_IN_FREQ		(0x1 << 31)
119 #define DIGCLRZ			(0x1 << 30)
120 #define ENDIGLDO		(0x1 << 4)
121 #define APLL_CP_CURR		(0x1 << 3)
122 #define ENBGSC_REF		(0x1 << 2)
123 #define ENPLLLDO		(0x1 << 1)
124 #define ENPLL			(0x1 << 0)
132 #define PLL_LOCK		(0x1 << 0)
134 #define ENSATAMODE		(0x1 << 31)
135 #define PLLREFSEL		(0x1 << 30)
136 #define MDIVINT			(0x4b << 18)
137 #define EN_CLKAUX		(0x1 << 5)
138 #define EN_CLK125M		(0x1 << 4)
139 #define EN_CLK100M		(0x1 << 3)
140 #define EN_CLK50M		(0x1 << 2)
150 #define DIGLDO_EN_CAPLESSMODE	(0x1 << 22)
151 #define PLLDO_EN_LDO_STABLE	(0x1 << 11)
152 #define PLLDO_EN_BUF_CUR	(0x1 << 7)
153 #define PLLDO_EN_LP		(0x1 << 6)
154 #define PLLDO_CTRL_TRIM_1_4V	(0x10 << 1)
179 	while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)  in enable_per_clocks()
182 	while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)  in enable_per_clocks()
212 	u32 sig_val = 0;  in pll_sigma_delta_val()
227 	u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;  in pll_config()
228 	u32 sig_val = 0, hs_mod = 0;  in pll_config()
298 	writel(0x1EDA4C3D, 0x481C5040);  in unlock_pll_control_mmr()
299 	writel(0x2FF1AC2B, 0x48140060);  in unlock_pll_control_mmr()
300 	writel(0xF757FDC0, 0x48140064);  in unlock_pll_control_mmr()
301 	writel(0xE2BC3A6D, 0x48140068);  in unlock_pll_control_mmr()
302 	writel(0x1EBF131D, 0x4814006c);  in unlock_pll_control_mmr()
303 	writel(0x6F361E05, 0x48140070);  in unlock_pll_control_mmr()
308 	pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);  in mpu_pll_config()
313 	u32 l3_osc_src, rd_osc_src = 0;  in l3_pll_config()
319 		writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);  in l3_pll_config()
321 		writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);  in l3_pll_config()
356 	while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))  in sata_pll_config()
370 	while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)  in enable_dmm_clocks()
376 	while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)  in enable_dmm_clocks()