33 #define CM_PLL_BASE		(CTRL_BASE + 0x0400)
37 #define MAIN_P			0x1
38 #define MAIN_INTFREQ1		0x8
39 #define MAIN_FRACFREQ1		0x800000
40 #define MAIN_MDIV1		0x2
41 #define MAIN_INTFREQ2		0xE
42 #define MAIN_FRACFREQ2		0x0
43 #define MAIN_MDIV2		0x1
44 #define MAIN_INTFREQ3		0x8
45 #define MAIN_FRACFREQ3		0xAAAAB0
46 #define MAIN_MDIV3		0x3
47 #define MAIN_INTFREQ4		0x9
48 #define MAIN_FRACFREQ4		0x55554F
49 #define MAIN_MDIV4		0x3
50 #define MAIN_INTFREQ5		0x9
51 #define MAIN_FRACFREQ5		0x374BC6
52 #define MAIN_MDIV5		0xC
53 #define MAIN_MDIV6		0x48
54 #define MAIN_MDIV7		0x4
58 #define DDR_P			0x1
59 #define DDR_MDIV1		0x2
60 #define DDR_INTFREQ2		0x8
61 #define DDR_FRACFREQ2		0xD99999
62 #define DDR_MDIV2		0x1E
63 #define DDR_INTFREQ3		0x8
64 #define DDR_FRACFREQ3		0x0
65 #define DDR_MDIV3		0x4
66 #define DDR_INTFREQ4		0xE /* Expansion DDR clk */
67 #define DDR_FRACFREQ4		0x0
68 #define DDR_MDIV4		0x4
69 #define DDR_INTFREQ5		0xE /* Expansion DDR clk */
70 #define DDR_FRACFREQ5		0x0
71 #define DDR_MDIV5		0x4
73 #define CONTROL_STATUS			(CTRL_BASE + 0x40)
74 #define DDR_RCD				(CTRL_BASE + 0x070C)
75 #define CM_TIMER1_CLKSEL		(PRCM_BASE + 0x390)
76 #define CM_ALWON_CUST_EFUSE_CLKCTRL	(PRCM_BASE + 0x1628)
78 #define INTCPS_SYSCONFIG	0x48200010
79 #define CM_SYSCLK10_CLKSEL	0x48180324
82 	unsigned int mainpll_ctrl;	/* offset 0x400 */
98 	unsigned int ddrpll_ctrl;	/* offset 0x440 */
110 	unsigned int videopll_ctrl;	/* offset 0x470 */
119 	unsigned int audiopll_ctrl;	/* offset 0x4A0 */
141 	while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)  in enable_dmm_clocks()
153 	while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)  in enable_emif_clocks()
156 	while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)  in enable_emif_clocks()
159 	while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)  in enable_emif_clocks()
174 	for (i = 0; i < 50*d; i++)  in ddr_delay()
180 	u32 main_pll_ctrl = 0;  in main_pll_init_ti816x()
184 	main_pll_ctrl &= 0xFFFFFFFB;  in main_pll_init_ti816x()
190 	main_pll_ctrl &= 0xFFFFFFF7;  in main_pll_init_ti816x()
196 	main_pll_ctrl &= 0xFF;  in main_pll_init_ti816x()
201 	writel(0x0, &cmpll->mainpll_pwd);  in main_pll_init_ti816x()
234 	main_pll_ctrl &= 0xFFFFFFFB;  in main_pll_init_ti816x()
240 	u32 ddr_pll_ctrl = 0;  in ddr_pll_bypass_ti816x()
244 	ddr_pll_ctrl &= 0xFFFFFFFB;  in ddr_pll_bypass_ti816x()
251 	u32 ddr_pll_ctrl = 0;  in ddr_pll_init_ti816x()
254 	ddr_pll_ctrl &= 0xFFFFFFF7;  in ddr_pll_init_ti816x()
260 	ddr_pll_ctrl &= 0xFF;  in ddr_pll_init_ti816x()
267 	writel(0x0, &cmpll->ddrpll_pwd);  in ddr_pll_init_ti816x()
270 	writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);  in ddr_pll_init_ti816x()
276 	writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);  in ddr_pll_init_ti816x()
280 	writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),  in ddr_pll_init_ti816x()
293 	writel(BIT(0), DDR_RCD);  in ddr_pll_init_ti816x()
303 	 * There are 8 timers(0-7) out of which timer 0 is a secure timer.  in peripheral_enable()
304 	 * Timer 0 mux should not be changed  in peripheral_enable()
317 					& (0x80000<<1))>>20) != 1)  in peripheral_enable()
320 	while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)  in peripheral_enable()
323 	writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));  in peripheral_enable()
324 	while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))  in peripheral_enable()
327 	writel(BIT(0), (DM_TIMER1_BASE + 0x38));  in peripheral_enable()
370 	writel(0x0, CM_SYSCLK10_CLKSEL);  in setup_clocks_for_console()
384 	while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)  in setup_clocks_for_console()