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/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-pinctrl.h17 #define PULL_ENABLE (0 << PULLUDEN_SHIFT)
20 #define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE)
23 #define INPUT_DISABLE (0 << RXACTIVE_SHIFT)
33 #define PIN_DEBOUNCE_DISABLE (0 << DEBOUNCE_SHIFT)
41 #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
42 #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
44 #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
45 #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
47 #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
48 #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
[all …]
/openbmc/linux/drivers/media/platform/ti/vpe/
H A Dcsc.h13 #define CSC_CSC00 0x00
14 #define CSC_A0_MASK 0x1fff
15 #define CSC_A0_SHIFT 0
16 #define CSC_B0_MASK 0x1fff
19 #define CSC_CSC01 0x04
20 #define CSC_C0_MASK 0x1fff
21 #define CSC_C0_SHIFT 0
22 #define CSC_A1_MASK 0x1fff
25 #define CSC_CSC02 0x08
26 #define CSC_B1_MASK 0x1fff
[all …]
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_viu.c46 VIU_MATRIX_OSD_EOTF = 0,
51 VIU_LUT_OSD_EOTF = 0,
63 0, 0, 0, /* pre offset */
67 0, 0, 0, /* 10'/11'/12' */
68 0, 0, 0, /* 20'/21'/22' */
70 0, 0, 0 /* mode, right_shift, clip_en */
85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/openbmc/linux/drivers/media/platform/xilinx/
H A Dxilinx-vtc.c66 * The following registers exist in two blocks, one at 0x0020 for the detector
67 * and one at 0x0060 for the generator.
70 #define XVTC_DETECTOR_OFFSET 0x0020
71 #define XVTC_GENERATOR_OFFSET 0x0060
73 #define XVTC_ACTIVE_SIZE 0x0000
75 #define XVTC_ACTIVE_VSIZE_MASK (0x1fff << 16)
76 #define XVTC_ACTIVE_HSIZE_SHIFT 0
77 #define XVTC_ACTIVE_HSIZE_MASK (0x1fff << 0)
79 #define XVTC_TIMING_STATUS 0x0004
82 #define XVTC_TIMING_STATUS_LOCKED (1 << 0)
[all …]
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_vpu_init.c14 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
15 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
16 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
28 0x15561500, 0x14561600, 0x13561700, 0x12561800,
29 0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00,
30 0x0f531e00, 0x0e531f00, 0x0d522100, 0x0c522200,
31 0x0b522300, 0x0b512400, 0x0a502600, 0x0a4f2700,
32 0x094e2900, 0x084e2a00, 0x084d2b00, 0x074c2c01,
33 0x074b2d01, 0x064a2f01, 0x06493001, 0x05483201,
34 0x05473301, 0x05463401, 0x04453601, 0x04433702,
[all …]
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dregs-decon7.h11 #define VIDCON0 0x00
16 #define VIDCON0_ENVID_F (1 << 0)
19 #define VIDOUTCON0 0x4
21 #define VIDOUTCON0_DUAL_MASK (0x3 << 24)
22 #define VIDOUTCON0_DUAL_ON (0x3 << 24)
23 #define VIDOUTCON0_DISP_IF_1_ON (0x2 << 24)
24 #define VIDOUTCON0_DISP_IF_0_ON (0x1 << 24)
25 #define VIDOUTCON0_DUAL_OFF (0x0 << 24)
27 #define VIDOUTCON0_IF_MASK (0x1 << 23)
28 #define VIDOUTCON0_RGBIF (0x0 << 23)
[all …]
H A Dregs-gsc.h14 #define GSC_ENABLE 0x00
16 #define GSC_ENABLE_PP_UPDATE_TIME_CURR (0 << 9)
21 #define GSC_ENABLE_NORM_MODE (0 << 7)
31 #define GSC_ENABLE_ON (1 << 0)
34 #define GSC_SW_RESET 0x04
35 #define GSC_SW_RESET_SRESET (1 << 0)
38 #define GSC_IRQ 0x08
43 #define GSC_IRQ_ENABLE (1 << 0)
46 #define GSC_IN_CON 0x10
63 #define GSC_IN_RGB_SD_NARROW (0 << 14)
[all …]
/openbmc/linux/drivers/media/rc/img-ir/
H A Dimg-ir-sanyo.c31 addr = (raw >> 0) & 0x1fff; in img_ir_sanyo_scancode()
32 addr_inv = (raw >> 13) & 0x1fff; in img_ir_sanyo_scancode()
33 data = (raw >> 26) & 0xff; in img_ir_sanyo_scancode()
34 data_inv = (raw >> 34) & 0xff; in img_ir_sanyo_scancode()
36 if ((data_inv ^ data) != 0xff) in img_ir_sanyo_scancode()
39 if ((addr_inv ^ addr) != 0x1fff) in img_ir_sanyo_scancode()
55 data = in->data & 0xff; in img_ir_sanyo_filter()
56 data_m = in->mask & 0xff; in img_ir_sanyo_filter()
57 data_inv = data ^ 0xff; in img_ir_sanyo_filter()
59 if (in->data & 0xff700000) in img_ir_sanyo_filter()
[all …]
/openbmc/linux/drivers/mfd/
H A Dwm8350-regmap.c23 { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Reset/ID */
24 { 0x7CFF, 0x0C00, 0x0000 }, /* R1 - ID */
25 { 0x007F, 0x0000, 0x0000 }, /* R2 - ROM Mask ID */
26 { 0xBE3B, 0xBE3B, 0x8000 }, /* R3 - System Control 1 */
27 { 0xFEF7, 0xFEF7, 0xF800 }, /* R4 - System Control 2 */
28 { 0x80FF, 0x80FF, 0x8000 }, /* R5 - System Hibernate */
29 { 0xFB0E, 0xFB0E, 0x0000 }, /* R6 - Interface Control */
30 { 0x0000, 0x0000, 0x0000 }, /* R7 */
31 { 0xE537, 0xE537, 0xFFFF }, /* R8 - Power mgmt (1) */
32 { 0x0FF3, 0x0FF3, 0xFFFF }, /* R9 - Power mgmt (2) */
[all …]
/openbmc/linux/drivers/staging/sm750fb/
H A Dsm750_accel.h5 #define HW_ROP2_COPY 0xc
6 #define HW_ROP2_XOR 0x6
8 /* notes: below address are the offset value from de_base_address (0x100000)*/
11 #define DE_BASE_ADDR_TYPE1 0x100000
13 #define DE_BASE_ADDR_TYPE2 0x8000
15 #define DE_BASE_ADDR_TYPE3 0
18 #define DE_PORT_ADDR_TYPE1 0x110000
20 #define DE_PORT_ADDR_TYPE2 0x100000
22 #define DE_PORT_ADDR_TYPE3 0x100000
24 #define DE_SOURCE 0x0
[all …]
/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dpi_regs.h9 #define DPI_EN 0x00
10 #define EN BIT(0)
12 #define DPI_RET 0x04
13 #define RST BIT(0)
15 #define DPI_INTEN 0x08
16 #define INT_VSYNC_EN BIT(0)
20 #define DPI_INTSTA 0x0C
21 #define INT_VSYNC_STA BIT(0)
25 #define DPI_CON 0x10
26 #define BG_ENABLE BIT(0)
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dfb_decoder.h47 #define _PIPE_V_SRCSZ_SHIFT 0
48 #define _PIPE_V_SRCSZ_MASK (0xfff << _PIPE_V_SRCSZ_SHIFT)
50 #define _PIPE_H_SRCSZ_MASK (0x1fff << _PIPE_H_SRCSZ_SHIFT)
53 #define _PRI_PLANE_STRIDE_MASK (0x3ff << 6)
54 #define _PRI_PLANE_X_OFF_SHIFT 0
55 #define _PRI_PLANE_X_OFF_MASK (0x1fff << _PRI_PLANE_X_OFF_SHIFT)
57 #define _PRI_PLANE_Y_OFF_MASK (0xfff << _PRI_PLANE_Y_OFF_SHIFT)
59 #define _CURSOR_MODE 0x3f
61 #define _CURSOR_ALPHA_FORCE_MASK (0x3 << _CURSOR_ALPHA_FORCE_SHIFT)
63 #define _CURSOR_ALPHA_PLANE_MASK (0x3 << _CURSOR_ALPHA_PLANE_SHIFT)
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7722.c18 #define FRQCR 0xa4150000
19 #define VCLKCR 0xa4150004
20 #define SCLKACR 0xa4150008
21 #define SCLKBCR 0xa415000c
22 #define IRDACLKCR 0xa4150018
23 #define PLLCR 0xa4150024
24 #define MSTPCR0 0xa4150030
25 #define MSTPCR1 0xa4150034
26 #define MSTPCR2 0xa4150038
27 #define DLLFRQ 0xa4150050
[all …]
H A Dclock-sh7343.c16 #define FRQCR 0xa4150000
17 #define VCLKCR 0xa4150004
18 #define SCLKACR 0xa4150008
19 #define SCLKBCR 0xa415000c
20 #define PLLCR 0xa4150024
21 #define MSTPCR0 0xa4150030
22 #define MSTPCR1 0xa4150034
23 #define MSTPCR2 0xa4150038
24 #define DLLFRQ 0xa4150050
44 if (__raw_readl(PLLCR) & 0x1000) in dll_recalc()
[all …]
H A Dclock-sh7366.c16 #define FRQCR 0xa4150000
17 #define VCLKCR 0xa4150004
18 #define SCLKACR 0xa4150008
19 #define SCLKBCR 0xa415000c
20 #define PLLCR 0xa4150024
21 #define MSTPCR0 0xa4150030
22 #define MSTPCR1 0xa4150034
23 #define MSTPCR2 0xa4150038
24 #define DLLFRQ 0xa4150050
44 if (__raw_readl(PLLCR) & 0x1000) in dll_recalc()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dvop_rk3288.h71 check_member(rk3288_vop, dsp_vact_st_end_f1, 0x19c);
74 ARGB8888 = 0,
80 LB_YUV_3840X5 = 0x0,
81 LB_YUV_2560X8 = 0x1,
82 LB_RGB_3840X2 = 0x2,
83 LB_RGB_2560X4 = 0x3,
84 LB_RGB_1920X5 = 0x4,
85 LB_RGB_1280X8 = 0x5
89 VOP_MODE_EDP = 0,
99 #define M_FPGA_VERSION (0xffff << 16)
[all …]
/openbmc/linux/drivers/input/gameport/
H A Dfm801-gp.c18 #define PCI_VENDOR_ID_FORTEMEDIA 0x1319
19 #define PCI_DEVICE_ID_FM801_GP 0x0802
34 *buttons = (~w >> 14) & 0x03; in fm801_gp_cooked_read()
35 axes[0] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
37 axes[1] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
39 *buttons |= ((~w >> 14) & 0x03) << 2; in fm801_gp_cooked_read()
40 axes[2] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
42 axes[3] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
43 outw(0xff, gameport->io); /* reset */ in fm801_gp_cooked_read()
45 return 0; in fm801_gp_cooked_read()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
H A Dgm107.c30 return 0; in gm107_fan_pwm_ctrl()
37 *divs = nvkm_rd32(device, 0x10eb20) & 0x1fff; in gm107_fan_pwm_get()
38 *duty = nvkm_rd32(device, 0x10eb24) & 0x1fff; in gm107_fan_pwm_get()
39 return 0; in gm107_fan_pwm_get()
46 nvkm_mask(device, 0x10eb10, 0x1fff, divs); /* keep the high bits */ in gm107_fan_pwm_set()
47 nvkm_wr32(device, 0x10eb14, duty | 0x80000000); in gm107_fan_pwm_set()
48 return 0; in gm107_fan_pwm_set()
/openbmc/linux/drivers/hid/
H A Dhid-uclogic-params-test.c29 .str_desc_size = 0,
35 .res = 0,
37 0x0E, 0x03,
38 0x70, 0xB2,
39 0x10, 0x77,
40 0x08,
41 0x00,
42 0xFF, 0x1F,
43 0x00, 0x00,
47 [UCLOGIC_RDESC_PEN_PH_ID_X_LM] = 0xB270,
[all …]
/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drzg2l_mipi_dsi_regs.h14 #define DSIDPHYCTRL0 0x00
19 #define DSIDPHYCTRL0_EN_BGR BIT(0)
21 #define DSIDPHYTIM0 0x04
23 #define DSIDPHYTIM0_T_INIT(x) ((x) << 0)
25 #define DSIDPHYTIM1 0x08
29 #define DSIDPHYTIM1_TCLK_SETTLE(x) ((x) << 0)
31 #define DSIDPHYTIM2 0x0c
35 #define DSIDPHYTIM2_TCLK_ZERO(x) ((x) << 0)
37 #define DSIDPHYTIM3 0x10
41 #define DSIDPHYTIM3_THS_ZERO(x) ((x) << 0)
[all …]
H A Drcar_mipi_dsi_regs.h11 #define LINKSR 0x010
13 #define LINKSR_HSBUSY (1 << 0)
18 #define TXVMSETR 0x180
19 #define TXVMSETR_SYNSEQ_PULSES (0 << 16)
24 #define TXVMSETR_VSEN_DIS (0 << 4)
26 #define TXVMSETR_HFPBPEN_DIS (0 << 2)
28 #define TXVMSETR_HBPBPEN_DIS (0 << 1)
29 #define TXVMSETR_HSABPEN_EN (1 << 0)
30 #define TXVMSETR_HSABPEN_DIS (0 << 0)
32 #define TXVMCR 0x190
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_util.c17 #define QSEED3_HW_VERSION 0x00
18 #define QSEED3_OP_MODE 0x04
19 #define QSEED3_RGB2Y_COEFF 0x08
20 #define QSEED3_PHASE_INIT 0x0C
21 #define QSEED3_PHASE_STEP_Y_H 0x10
22 #define QSEED3_PHASE_STEP_Y_V 0x14
23 #define QSEED3_PHASE_STEP_UV_H 0x18
24 #define QSEED3_PHASE_STEP_UV_V 0x1C
25 #define QSEED3_PRELOAD 0x20
26 #define QSEED3_DE_SHARPEN 0x24
[all …]
/openbmc/linux/drivers/media/platform/renesas/vsp1/
H A Dvsp1_regs.h17 #define VI6_CMD(n) (0x0000 + (n) * 4)
19 #define VI6_CMD_STRCMD BIT(0)
21 #define VI6_CLK_DCSWT 0x0018
22 #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8)
24 #define VI6_CLK_DCSWT_CSTRW_MASK (0xff << 0)
25 #define VI6_CLK_DCSWT_CSTRW_SHIFT 0
27 #define VI6_SRESET 0x0028
30 #define VI6_STATUS 0x0038
34 #define VI6_WPF_IRQ_ENB(n) (0x0048 + (n) * 12)
37 #define VI6_WPF_IRQ_ENB_FREE BIT(0)
[all …]
/openbmc/u-boot/include/
H A Dfsl_lpuart.h63 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000)
64 #define LPUART_BAUD_OSR_MASK (0x1F000000)
66 #define LPUART_BAUD_OSR(x) ((((uint32_t)(x)) << 24) & 0x1F000000)
67 #define LPUART_BAUD_SBR_MASK (0x1FFF)
68 #define LPUART_BAUD_SBR_SHIFT (0U)
69 #define LPUART_BAUD_SBR(x) (((uint32_t)(x)) & 0x1FFF)
70 #define LPUART_BAUD_M10_MASK (0x20000000U)
71 #define LPUART_BAUD_SBNS_MASK (0x2000U)

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