Lines Matching +full:0 +full:x1fff
71 check_member(rk3288_vop, dsp_vact_st_end_f1, 0x19c);
74 ARGB8888 = 0,
80 LB_YUV_3840X5 = 0x0,
81 LB_YUV_2560X8 = 0x1,
82 LB_RGB_3840X2 = 0x2,
83 LB_RGB_2560X4 = 0x3,
84 LB_RGB_1920X5 = 0x4,
85 LB_RGB_1280X8 = 0x5
89 VOP_MODE_EDP = 0,
99 #define M_FPGA_VERSION (0xffff << 16)
100 #define M_RTL_VERSION (0xffff)
107 #define M_DAM_BURST_LENGTH (0x3 << 18)
117 #define M_DOUB_CH_OVERLAP_NUM (0xf << 4)
119 #define M_DIRECT_PATH_LAYER_SEL (0x3 << 1)
134 #define V_DOUB_CH_OVERLAP_NUM(x) (((x) & 0xf) << 4)
140 #define M_AXI_OUTSTANDING_MAX_NUM (0x1f << 13)
144 #define M_NOC_HURRY_THRESHOLD (0x3f << 3)
145 #define M_NOC_HURRY_VALUE (0x3 << 1)
148 #define V_AXI_OUTSTANDING_MAX_NUM(x) (((x) & 0x1f) << 13)
152 #define V_NOC_HURRY_THRESHOLD(x) (((x) & 0x3f) << 3)
177 #define M_DSP_OUT_MODE (0xf)
199 #define V_DSP_PIN_POL(x) (((x) & 0xf) << 4)
200 #define V_DSP_OUT_MODE(x) ((x) & 0xf)
208 #define M_RK3399_DSP_MIPI_POL (V_RK3399_DSP_MIPI_POL(0xf))
209 #define M_RK3399_DSP_EDP_POL (V_RK3399_DSP_EDP_POL(0xf))
210 #define M_RK3399_DSP_HDMI_POL (V_RK3399_DSP_HDMI_POL(0xf))
211 #define M_RK3399_DSP_LVDS_POL (V_RK3399_DSP_LVDS_POL(0xf))
236 #define M_DSP_BG_RED (0x3f << 20)
237 #define M_DSP_BG_GREEN (0x3f << 10)
238 #define M_DSP_BG_BLUE (0x3f << 0)
240 #define V_DSP_BG_RED(x) (((x) & 0x3f) << 20)
241 #define V_DSP_BG_GREEN(x) (((x) & 0x3f) << 10)
242 #define V_DSP_BG_BLUE(x) (((x) & 0x3f) << 0)
259 #define M_WIN0_EN (1 << 0)
290 #define M_WIN0_YRGB_AXI_GATHER_NUM (0xf << 8)
311 #define V_WIN0_YRGB_AXI_GATHER_NUM(x) (((x) & 0xf) << 8)
322 #define M_WIN0_KEY_COLOR (0x3fffffff)
325 #define V_WIN0_KEY_COLOR(x) ((x) & 0x3fffffff)
328 #define V_ARGB888_VIRWIDTH(x) (((x) & 0x3fff) << 0)
329 #define V_RGB888_VIRWIDTH(x) (((((x * 3) >> 2)+((x) % 3)) & 0x3fff) << 0)
330 #define V_RGB565_VIRWIDTH(x) (((x / 2) & 0x3fff) << 0)
331 #define YUV_VIRWIDTH(x) (((x / 4) & 0x3fff) << 0)
334 #define V_ACT_HEIGHT(x) (((x) & 0x1fff) << 16)
335 #define V_ACT_WIDTH(x) ((x) & 0x1fff)
338 #define V_DSP_HEIGHT(x) (((x) & 0xfff) << 16)
339 #define V_DSP_WIDTH(x) ((x) & 0xfff)
342 #define V_DSP_YST(x) (((x) & 0x1fff) << 16)
343 #define V_DSP_XST(x) ((x) & 0x1fff)
346 #define V_WIN0_VS_OFFSET_CBR(x) (((x) & 0xff) << 24)
347 #define V_WIN0_VS_OFFSET_YRGB(x) (((x) & 0xff) << 16)
348 #define V_WIN0_HS_OFFSET_CBR(x) (((x) & 0xff) << 8)
349 #define V_WIN0_HS_OFFSET_YRGB(x) ((x) & 0xff)
351 #define V_HSYNC(x) (((x)&0x1fff)<<0) /* hsync pulse width */
352 #define V_HORPRD(x) (((x)&0x1fff)<<16) /* horizontal period */
353 #define V_VSYNC(x) (((x)&0x1fff)<<0)
354 #define V_VERPRD(x) (((x)&0x1fff)<<16)
356 #define V_HEAP(x) (((x)&0x1fff)<<0)/* horizontal active end */
357 #define V_HASP(x) (((x)&0x1fff)<<16)/* horizontal active start */
358 #define V_VAEP(x) (((x)&0x1fff)<<0)
359 #define V_VASP(x) (((x)&0x1fff)<<16)