1*11696c5eSBiju Das /* SPDX-License-Identifier: GPL-2.0 */ 2*11696c5eSBiju Das /* 3*11696c5eSBiju Das * RZ/G2L MIPI DSI Interface Registers Definitions 4*11696c5eSBiju Das * 5*11696c5eSBiju Das * Copyright (C) 2022 Renesas Electronics Corporation 6*11696c5eSBiju Das */ 7*11696c5eSBiju Das 8*11696c5eSBiju Das #ifndef __RZG2L_MIPI_DSI_REGS_H__ 9*11696c5eSBiju Das #define __RZG2L_MIPI_DSI_REGS_H__ 10*11696c5eSBiju Das 11*11696c5eSBiju Das #include <linux/bits.h> 12*11696c5eSBiju Das 13*11696c5eSBiju Das /* DPHY Registers */ 14*11696c5eSBiju Das #define DSIDPHYCTRL0 0x00 15*11696c5eSBiju Das #define DSIDPHYCTRL0_CAL_EN_HSRX_OFS BIT(16) 16*11696c5eSBiju Das #define DSIDPHYCTRL0_CMN_MASTER_EN BIT(8) 17*11696c5eSBiju Das #define DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 BIT(2) 18*11696c5eSBiju Das #define DSIDPHYCTRL0_EN_LDO1200 BIT(1) 19*11696c5eSBiju Das #define DSIDPHYCTRL0_EN_BGR BIT(0) 20*11696c5eSBiju Das 21*11696c5eSBiju Das #define DSIDPHYTIM0 0x04 22*11696c5eSBiju Das #define DSIDPHYTIM0_TCLK_MISS(x) ((x) << 24) 23*11696c5eSBiju Das #define DSIDPHYTIM0_T_INIT(x) ((x) << 0) 24*11696c5eSBiju Das 25*11696c5eSBiju Das #define DSIDPHYTIM1 0x08 26*11696c5eSBiju Das #define DSIDPHYTIM1_THS_PREPARE(x) ((x) << 24) 27*11696c5eSBiju Das #define DSIDPHYTIM1_TCLK_PREPARE(x) ((x) << 16) 28*11696c5eSBiju Das #define DSIDPHYTIM1_THS_SETTLE(x) ((x) << 8) 29*11696c5eSBiju Das #define DSIDPHYTIM1_TCLK_SETTLE(x) ((x) << 0) 30*11696c5eSBiju Das 31*11696c5eSBiju Das #define DSIDPHYTIM2 0x0c 32*11696c5eSBiju Das #define DSIDPHYTIM2_TCLK_TRAIL(x) ((x) << 24) 33*11696c5eSBiju Das #define DSIDPHYTIM2_TCLK_POST(x) ((x) << 16) 34*11696c5eSBiju Das #define DSIDPHYTIM2_TCLK_PRE(x) ((x) << 8) 35*11696c5eSBiju Das #define DSIDPHYTIM2_TCLK_ZERO(x) ((x) << 0) 36*11696c5eSBiju Das 37*11696c5eSBiju Das #define DSIDPHYTIM3 0x10 38*11696c5eSBiju Das #define DSIDPHYTIM3_TLPX(x) ((x) << 24) 39*11696c5eSBiju Das #define DSIDPHYTIM3_THS_EXIT(x) ((x) << 16) 40*11696c5eSBiju Das #define DSIDPHYTIM3_THS_TRAIL(x) ((x) << 8) 41*11696c5eSBiju Das #define DSIDPHYTIM3_THS_ZERO(x) ((x) << 0) 42*11696c5eSBiju Das 43*11696c5eSBiju Das /* --------------------------------------------------------*/ 44*11696c5eSBiju Das /* Link Registers */ 45*11696c5eSBiju Das #define LINK_REG_OFFSET 0x10000 46*11696c5eSBiju Das 47*11696c5eSBiju Das /* Link Status Register */ 48*11696c5eSBiju Das #define LINKSR 0x10 49*11696c5eSBiju Das #define LINKSR_LPBUSY BIT(13) 50*11696c5eSBiju Das #define LINKSR_HSBUSY BIT(12) 51*11696c5eSBiju Das #define LINKSR_VICHRUN1 BIT(8) 52*11696c5eSBiju Das #define LINKSR_SQCHRUN1 BIT(4) 53*11696c5eSBiju Das #define LINKSR_SQCHRUN0 BIT(0) 54*11696c5eSBiju Das 55*11696c5eSBiju Das /* Tx Set Register */ 56*11696c5eSBiju Das #define TXSETR 0x100 57*11696c5eSBiju Das #define TXSETR_NUMLANECAP (0x3 << 16) 58*11696c5eSBiju Das #define TXSETR_DLEN (1 << 9) 59*11696c5eSBiju Das #define TXSETR_CLEN (1 << 8) 60*11696c5eSBiju Das #define TXSETR_NUMLANEUSE(x) (((x) & 0x3) << 0) 61*11696c5eSBiju Das 62*11696c5eSBiju Das /* HS Clock Set Register */ 63*11696c5eSBiju Das #define HSCLKSETR 0x104 64*11696c5eSBiju Das #define HSCLKSETR_HSCLKMODE_CONT (1 << 1) 65*11696c5eSBiju Das #define HSCLKSETR_HSCLKMODE_NON_CONT (0 << 1) 66*11696c5eSBiju Das #define HSCLKSETR_HSCLKRUN_HS (1 << 0) 67*11696c5eSBiju Das #define HSCLKSETR_HSCLKRUN_LP (0 << 0) 68*11696c5eSBiju Das 69*11696c5eSBiju Das /* Reset Control Register */ 70*11696c5eSBiju Das #define RSTCR 0x110 71*11696c5eSBiju Das #define RSTCR_SWRST BIT(0) 72*11696c5eSBiju Das #define RSTCR_FCETXSTP BIT(16) 73*11696c5eSBiju Das 74*11696c5eSBiju Das /* Reset Status Register */ 75*11696c5eSBiju Das #define RSTSR 0x114 76*11696c5eSBiju Das #define RSTSR_DL0DIR (1 << 15) 77*11696c5eSBiju Das #define RSTSR_DLSTPST (0xf << 8) 78*11696c5eSBiju Das #define RSTSR_SWRSTV1 (1 << 4) 79*11696c5eSBiju Das #define RSTSR_SWRSTIB (1 << 3) 80*11696c5eSBiju Das #define RSTSR_SWRSTAPB (1 << 2) 81*11696c5eSBiju Das #define RSTSR_SWRSTLP (1 << 1) 82*11696c5eSBiju Das #define RSTSR_SWRSTHS (1 << 0) 83*11696c5eSBiju Das 84*11696c5eSBiju Das /* Clock Lane Stop Time Set Register */ 85*11696c5eSBiju Das #define CLSTPTSETR 0x314 86*11696c5eSBiju Das #define CLSTPTSETR_CLKKPT(x) ((x) << 24) 87*11696c5eSBiju Das #define CLSTPTSETR_CLKBFHT(x) ((x) << 16) 88*11696c5eSBiju Das #define CLSTPTSETR_CLKSTPT(x) ((x) << 2) 89*11696c5eSBiju Das 90*11696c5eSBiju Das /* LP Transition Time Set Register */ 91*11696c5eSBiju Das #define LPTRNSTSETR 0x318 92*11696c5eSBiju Das #define LPTRNSTSETR_GOLPBKT(x) ((x) << 0) 93*11696c5eSBiju Das 94*11696c5eSBiju Das /* Physical Lane Status Register */ 95*11696c5eSBiju Das #define PLSR 0x320 96*11696c5eSBiju Das #define PLSR_CLHS2LP BIT(27) 97*11696c5eSBiju Das #define PLSR_CLLP2HS BIT(26) 98*11696c5eSBiju Das 99*11696c5eSBiju Das /* Video-Input Channel 1 Set 0 Register */ 100*11696c5eSBiju Das #define VICH1SET0R 0x400 101*11696c5eSBiju Das #define VICH1SET0R_VSEN BIT(12) 102*11696c5eSBiju Das #define VICH1SET0R_HFPNOLP BIT(10) 103*11696c5eSBiju Das #define VICH1SET0R_HBPNOLP BIT(9) 104*11696c5eSBiju Das #define VICH1SET0R_HSANOLP BIT(8) 105*11696c5eSBiju Das #define VICH1SET0R_VSTPAFT BIT(1) 106*11696c5eSBiju Das #define VICH1SET0R_VSTART BIT(0) 107*11696c5eSBiju Das 108*11696c5eSBiju Das /* Video-Input Channel 1 Set 1 Register */ 109*11696c5eSBiju Das #define VICH1SET1R 0x404 110*11696c5eSBiju Das #define VICH1SET1R_DLY(x) (((x) & 0xfff) << 2) 111*11696c5eSBiju Das 112*11696c5eSBiju Das /* Video-Input Channel 1 Status Register */ 113*11696c5eSBiju Das #define VICH1SR 0x410 114*11696c5eSBiju Das #define VICH1SR_VIRDY BIT(3) 115*11696c5eSBiju Das #define VICH1SR_RUNNING BIT(2) 116*11696c5eSBiju Das #define VICH1SR_STOP BIT(1) 117*11696c5eSBiju Das #define VICH1SR_START BIT(0) 118*11696c5eSBiju Das 119*11696c5eSBiju Das /* Video-Input Channel 1 Pixel Packet Set Register */ 120*11696c5eSBiju Das #define VICH1PPSETR 0x420 121*11696c5eSBiju Das #define VICH1PPSETR_DT_RGB18 (0x1e << 16) 122*11696c5eSBiju Das #define VICH1PPSETR_DT_RGB18_LS (0x2e << 16) 123*11696c5eSBiju Das #define VICH1PPSETR_DT_RGB24 (0x3e << 16) 124*11696c5eSBiju Das #define VICH1PPSETR_TXESYNC_PULSE (1 << 15) 125*11696c5eSBiju Das #define VICH1PPSETR_VC(x) ((x) << 22) 126*11696c5eSBiju Das 127*11696c5eSBiju Das /* Video-Input Channel 1 Vertical Size Set Register */ 128*11696c5eSBiju Das #define VICH1VSSETR 0x428 129*11696c5eSBiju Das #define VICH1VSSETR_VACTIVE(x) (((x) & 0x7fff) << 16) 130*11696c5eSBiju Das #define VICH1VSSETR_VSPOL_LOW (1 << 15) 131*11696c5eSBiju Das #define VICH1VSSETR_VSPOL_HIGH (0 << 15) 132*11696c5eSBiju Das #define VICH1VSSETR_VSA(x) (((x) & 0xfff) << 0) 133*11696c5eSBiju Das 134*11696c5eSBiju Das /* Video-Input Channel 1 Vertical Porch Set Register */ 135*11696c5eSBiju Das #define VICH1VPSETR 0x42c 136*11696c5eSBiju Das #define VICH1VPSETR_VFP(x) (((x) & 0x1fff) << 16) 137*11696c5eSBiju Das #define VICH1VPSETR_VBP(x) (((x) & 0x1fff) << 0) 138*11696c5eSBiju Das 139*11696c5eSBiju Das /* Video-Input Channel 1 Horizontal Size Set Register */ 140*11696c5eSBiju Das #define VICH1HSSETR 0x430 141*11696c5eSBiju Das #define VICH1HSSETR_HACTIVE(x) (((x) & 0x7fff) << 16) 142*11696c5eSBiju Das #define VICH1HSSETR_HSPOL_LOW (1 << 15) 143*11696c5eSBiju Das #define VICH1HSSETR_HSPOL_HIGH (0 << 15) 144*11696c5eSBiju Das #define VICH1HSSETR_HSA(x) (((x) & 0xfff) << 0) 145*11696c5eSBiju Das 146*11696c5eSBiju Das /* Video-Input Channel 1 Horizontal Porch Set Register */ 147*11696c5eSBiju Das #define VICH1HPSETR 0x434 148*11696c5eSBiju Das #define VICH1HPSETR_HFP(x) (((x) & 0x1fff) << 16) 149*11696c5eSBiju Das #define VICH1HPSETR_HBP(x) (((x) & 0x1fff) << 0) 150*11696c5eSBiju Das 151*11696c5eSBiju Das #endif /* __RZG2L_MIPI_DSI_REGS_H__ */ 152