1*11696c5eSBiju Das /* SPDX-License-Identifier: GPL-2.0 */ 2*11696c5eSBiju Das /* 3*11696c5eSBiju Das * R-Car MIPI DSI Interface Registers Definitions 4*11696c5eSBiju Das * 5*11696c5eSBiju Das * Copyright (C) 2020 Renesas Electronics Corporation 6*11696c5eSBiju Das */ 7*11696c5eSBiju Das 8*11696c5eSBiju Das #ifndef __RCAR_MIPI_DSI_REGS_H__ 9*11696c5eSBiju Das #define __RCAR_MIPI_DSI_REGS_H__ 10*11696c5eSBiju Das 11*11696c5eSBiju Das #define LINKSR 0x010 12*11696c5eSBiju Das #define LINKSR_LPBUSY (1 << 1) 13*11696c5eSBiju Das #define LINKSR_HSBUSY (1 << 0) 14*11696c5eSBiju Das 15*11696c5eSBiju Das /* 16*11696c5eSBiju Das * Video Mode Register 17*11696c5eSBiju Das */ 18*11696c5eSBiju Das #define TXVMSETR 0x180 19*11696c5eSBiju Das #define TXVMSETR_SYNSEQ_PULSES (0 << 16) 20*11696c5eSBiju Das #define TXVMSETR_SYNSEQ_EVENTS (1 << 16) 21*11696c5eSBiju Das #define TXVMSETR_VSTPM (1 << 15) 22*11696c5eSBiju Das #define TXVMSETR_PIXWDTH (1 << 8) 23*11696c5eSBiju Das #define TXVMSETR_VSEN_EN (1 << 4) 24*11696c5eSBiju Das #define TXVMSETR_VSEN_DIS (0 << 4) 25*11696c5eSBiju Das #define TXVMSETR_HFPBPEN_EN (1 << 2) 26*11696c5eSBiju Das #define TXVMSETR_HFPBPEN_DIS (0 << 2) 27*11696c5eSBiju Das #define TXVMSETR_HBPBPEN_EN (1 << 1) 28*11696c5eSBiju Das #define TXVMSETR_HBPBPEN_DIS (0 << 1) 29*11696c5eSBiju Das #define TXVMSETR_HSABPEN_EN (1 << 0) 30*11696c5eSBiju Das #define TXVMSETR_HSABPEN_DIS (0 << 0) 31*11696c5eSBiju Das 32*11696c5eSBiju Das #define TXVMCR 0x190 33*11696c5eSBiju Das #define TXVMCR_VFCLR (1 << 12) 34*11696c5eSBiju Das #define TXVMCR_EN_VIDEO (1 << 0) 35*11696c5eSBiju Das 36*11696c5eSBiju Das #define TXVMSR 0x1a0 37*11696c5eSBiju Das #define TXVMSR_STR (1 << 16) 38*11696c5eSBiju Das #define TXVMSR_VFRDY (1 << 12) 39*11696c5eSBiju Das #define TXVMSR_ACT (1 << 8) 40*11696c5eSBiju Das #define TXVMSR_RDY (1 << 0) 41*11696c5eSBiju Das 42*11696c5eSBiju Das #define TXVMSCR 0x1a4 43*11696c5eSBiju Das #define TXVMSCR_STR (1 << 16) 44*11696c5eSBiju Das 45*11696c5eSBiju Das #define TXVMPSPHSETR 0x1c0 46*11696c5eSBiju Das #define TXVMPSPHSETR_DT_RGB16 (0x0e << 16) 47*11696c5eSBiju Das #define TXVMPSPHSETR_DT_RGB18 (0x1e << 16) 48*11696c5eSBiju Das #define TXVMPSPHSETR_DT_RGB18_LS (0x2e << 16) 49*11696c5eSBiju Das #define TXVMPSPHSETR_DT_RGB24 (0x3e << 16) 50*11696c5eSBiju Das #define TXVMPSPHSETR_DT_YCBCR16 (0x2c << 16) 51*11696c5eSBiju Das 52*11696c5eSBiju Das #define TXVMVPRMSET0R 0x1d0 53*11696c5eSBiju Das #define TXVMVPRMSET0R_HSPOL_HIG (0 << 17) 54*11696c5eSBiju Das #define TXVMVPRMSET0R_HSPOL_LOW (1 << 17) 55*11696c5eSBiju Das #define TXVMVPRMSET0R_VSPOL_HIG (0 << 16) 56*11696c5eSBiju Das #define TXVMVPRMSET0R_VSPOL_LOW (1 << 16) 57*11696c5eSBiju Das #define TXVMVPRMSET0R_CSPC_RGB (0 << 4) 58*11696c5eSBiju Das #define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4) 59*11696c5eSBiju Das #define TXVMVPRMSET0R_BPP_16 (0 << 0) 60*11696c5eSBiju Das #define TXVMVPRMSET0R_BPP_18 (1 << 0) 61*11696c5eSBiju Das #define TXVMVPRMSET0R_BPP_24 (2 << 0) 62*11696c5eSBiju Das 63*11696c5eSBiju Das #define TXVMVPRMSET1R 0x1d4 64*11696c5eSBiju Das #define TXVMVPRMSET1R_VACTIVE(x) (((x) & 0x7fff) << 16) 65*11696c5eSBiju Das #define TXVMVPRMSET1R_VSA(x) (((x) & 0xfff) << 0) 66*11696c5eSBiju Das 67*11696c5eSBiju Das #define TXVMVPRMSET2R 0x1d8 68*11696c5eSBiju Das #define TXVMVPRMSET2R_VFP(x) (((x) & 0x1fff) << 16) 69*11696c5eSBiju Das #define TXVMVPRMSET2R_VBP(x) (((x) & 0x1fff) << 0) 70*11696c5eSBiju Das 71*11696c5eSBiju Das #define TXVMVPRMSET3R 0x1dc 72*11696c5eSBiju Das #define TXVMVPRMSET3R_HACTIVE(x) (((x) & 0x7fff) << 16) 73*11696c5eSBiju Das #define TXVMVPRMSET3R_HSA(x) (((x) & 0xfff) << 0) 74*11696c5eSBiju Das 75*11696c5eSBiju Das #define TXVMVPRMSET4R 0x1e0 76*11696c5eSBiju Das #define TXVMVPRMSET4R_HFP(x) (((x) & 0x1fff) << 16) 77*11696c5eSBiju Das #define TXVMVPRMSET4R_HBP(x) (((x) & 0x1fff) << 0) 78*11696c5eSBiju Das 79*11696c5eSBiju Das /* 80*11696c5eSBiju Das * PHY-Protocol Interface (PPI) Registers 81*11696c5eSBiju Das */ 82*11696c5eSBiju Das #define PPISETR 0x700 83*11696c5eSBiju Das #define PPISETR_DLEN_0 (0x1 << 0) 84*11696c5eSBiju Das #define PPISETR_DLEN_1 (0x3 << 0) 85*11696c5eSBiju Das #define PPISETR_DLEN_2 (0x7 << 0) 86*11696c5eSBiju Das #define PPISETR_DLEN_3 (0xf << 0) 87*11696c5eSBiju Das #define PPISETR_CLEN (1 << 8) 88*11696c5eSBiju Das 89*11696c5eSBiju Das #define PPICLCR 0x710 90*11696c5eSBiju Das #define PPICLCR_TXREQHS (1 << 8) 91*11696c5eSBiju Das #define PPICLCR_TXULPSEXT (1 << 1) 92*11696c5eSBiju Das #define PPICLCR_TXULPSCLK (1 << 0) 93*11696c5eSBiju Das 94*11696c5eSBiju Das #define PPICLSR 0x720 95*11696c5eSBiju Das #define PPICLSR_HSTOLP (1 << 27) 96*11696c5eSBiju Das #define PPICLSR_TOHS (1 << 26) 97*11696c5eSBiju Das #define PPICLSR_STPST (1 << 0) 98*11696c5eSBiju Das 99*11696c5eSBiju Das #define PPICLSCR 0x724 100*11696c5eSBiju Das #define PPICLSCR_HSTOLP (1 << 27) 101*11696c5eSBiju Das #define PPICLSCR_TOHS (1 << 26) 102*11696c5eSBiju Das 103*11696c5eSBiju Das #define PPIDLSR 0x760 104*11696c5eSBiju Das #define PPIDLSR_STPST (0xf << 0) 105*11696c5eSBiju Das 106*11696c5eSBiju Das /* 107*11696c5eSBiju Das * Clocks registers 108*11696c5eSBiju Das */ 109*11696c5eSBiju Das #define LPCLKSET 0x1000 110*11696c5eSBiju Das #define LPCLKSET_CKEN (1 << 8) 111*11696c5eSBiju Das #define LPCLKSET_LPCLKDIV(x) (((x) & 0x3f) << 0) 112*11696c5eSBiju Das 113*11696c5eSBiju Das #define CFGCLKSET 0x1004 114*11696c5eSBiju Das #define CFGCLKSET_CKEN (1 << 8) 115*11696c5eSBiju Das #define CFGCLKSET_CFGCLKDIV(x) (((x) & 0x3f) << 0) 116*11696c5eSBiju Das 117*11696c5eSBiju Das #define DOTCLKDIV 0x1008 118*11696c5eSBiju Das #define DOTCLKDIV_CKEN (1 << 8) 119*11696c5eSBiju Das #define DOTCLKDIV_DOTCLKDIV(x) (((x) & 0x3f) << 0) 120*11696c5eSBiju Das 121*11696c5eSBiju Das #define VCLKSET 0x100c 122*11696c5eSBiju Das #define VCLKSET_CKEN (1 << 16) 123*11696c5eSBiju Das #define VCLKSET_COLOR_RGB (0 << 8) 124*11696c5eSBiju Das #define VCLKSET_COLOR_YCC (1 << 8) 125*11696c5eSBiju Das #define VCLKSET_DIV_V3U(x) (((x) & 0x3) << 4) 126*11696c5eSBiju Das #define VCLKSET_DIV_V4H(x) (((x) & 0x7) << 4) 127*11696c5eSBiju Das #define VCLKSET_BPP_16 (0 << 2) 128*11696c5eSBiju Das #define VCLKSET_BPP_18 (1 << 2) 129*11696c5eSBiju Das #define VCLKSET_BPP_18L (2 << 2) 130*11696c5eSBiju Das #define VCLKSET_BPP_24 (3 << 2) 131*11696c5eSBiju Das #define VCLKSET_LANE(x) (((x) & 0x3) << 0) 132*11696c5eSBiju Das 133*11696c5eSBiju Das #define VCLKEN 0x1010 134*11696c5eSBiju Das #define VCLKEN_CKEN (1 << 0) 135*11696c5eSBiju Das 136*11696c5eSBiju Das #define PHYSETUP 0x1014 137*11696c5eSBiju Das #define PHYSETUP_HSFREQRANGE(x) (((x) & 0x7f) << 16) 138*11696c5eSBiju Das #define PHYSETUP_HSFREQRANGE_MASK (0x7f << 16) 139*11696c5eSBiju Das #define PHYSETUP_CFGCLKFREQRANGE(x) (((x) & 0x3f) << 8) 140*11696c5eSBiju Das #define PHYSETUP_SHUTDOWNZ (1 << 1) 141*11696c5eSBiju Das #define PHYSETUP_RSTZ (1 << 0) 142*11696c5eSBiju Das 143*11696c5eSBiju Das #define CLOCKSET1 0x101c 144*11696c5eSBiju Das #define CLOCKSET1_LOCK_PHY (1 << 17) 145*11696c5eSBiju Das #define CLOCKSET1_LOCK (1 << 16) 146*11696c5eSBiju Das #define CLOCKSET1_CLKSEL (1 << 8) 147*11696c5eSBiju Das #define CLOCKSET1_CLKINSEL_EXTAL (0 << 2) 148*11696c5eSBiju Das #define CLOCKSET1_CLKINSEL_DIG (1 << 2) 149*11696c5eSBiju Das #define CLOCKSET1_CLKINSEL_DU (1 << 3) 150*11696c5eSBiju Das #define CLOCKSET1_SHADOW_CLEAR (1 << 1) 151*11696c5eSBiju Das #define CLOCKSET1_UPDATEPLL (1 << 0) 152*11696c5eSBiju Das 153*11696c5eSBiju Das #define CLOCKSET2 0x1020 154*11696c5eSBiju Das #define CLOCKSET2_M(x) (((x) & 0xfff) << 16) 155*11696c5eSBiju Das #define CLOCKSET2_VCO_CNTRL(x) (((x) & 0x3f) << 8) 156*11696c5eSBiju Das #define CLOCKSET2_N(x) (((x) & 0xf) << 0) 157*11696c5eSBiju Das 158*11696c5eSBiju Das #define CLOCKSET3 0x1024 159*11696c5eSBiju Das #define CLOCKSET3_PROP_CNTRL(x) (((x) & 0x3f) << 24) 160*11696c5eSBiju Das #define CLOCKSET3_INT_CNTRL(x) (((x) & 0x3f) << 16) 161*11696c5eSBiju Das #define CLOCKSET3_CPBIAS_CNTRL(x) (((x) & 0x7f) << 8) 162*11696c5eSBiju Das #define CLOCKSET3_GMP_CNTRL(x) (((x) & 0x3) << 0) 163*11696c5eSBiju Das 164*11696c5eSBiju Das #define PHTW 0x1034 165*11696c5eSBiju Das #define PHTW_DWEN (1 << 24) 166*11696c5eSBiju Das #define PHTW_TESTDIN_DATA(x) (((x) & 0xff) << 16) 167*11696c5eSBiju Das #define PHTW_CWEN (1 << 8) 168*11696c5eSBiju Das #define PHTW_TESTDIN_CODE(x) (((x) & 0xff) << 0) 169*11696c5eSBiju Das 170*11696c5eSBiju Das #define PHTR 0x1038 171*11696c5eSBiju Das #define PHTR_TEST (1 << 16) 172*11696c5eSBiju Das 173*11696c5eSBiju Das #define PHTC 0x103c 174*11696c5eSBiju Das #define PHTC_TESTCLR (1 << 0) 175*11696c5eSBiju Das 176*11696c5eSBiju Das #endif /* __RCAR_MIPI_DSI_REGS_H__ */ 177