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/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpmmu_hbw_stlb_masks.h24 #define PMMU_HBW_STLB_BUSY_BUSY_SHIFT 0
25 #define PMMU_HBW_STLB_BUSY_BUSY_MASK 0xFFFFFFFF
28 #define PMMU_HBW_STLB_ASID_ASID_SHIFT 0
29 #define PMMU_HBW_STLB_ASID_ASID_MASK 0x3FF
32 #define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0
33 #define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF
36 #define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0
37 #define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF
40 #define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
41 #define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
[all …]
H A Ddcore0_hmmu0_stlb_masks.h24 #define DCORE0_HMMU0_STLB_BUSY_BUSY_SHIFT 0
25 #define DCORE0_HMMU0_STLB_BUSY_BUSY_MASK 0xFFFFFFFF
28 #define DCORE0_HMMU0_STLB_ASID_ASID_SHIFT 0
29 #define DCORE0_HMMU0_STLB_ASID_ASID_MASK 0x3FF
32 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0
33 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF
36 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0
37 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF
40 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
41 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
[all …]
/openbmc/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu981_regs.h28 #define av1_dec_e AV1_DEC_REG(1, 0, 0x1)
29 #define av1_dec_abort_e AV1_DEC_REG(1, 5, 0x1)
30 #define av1_dec_tile_int_e AV1_DEC_REG(1, 7, 0x1)
32 #define av1_dec_clk_gate_e AV1_DEC_REG(2, 10, 0x1)
34 #define av1_dec_out_ec_bypass AV1_DEC_REG(3, 8, 0x1)
35 #define av1_write_mvs_e AV1_DEC_REG(3, 12, 0x1)
36 #define av1_filtering_dis AV1_DEC_REG(3, 14, 0x1)
37 #define av1_dec_out_dis AV1_DEC_REG(3, 15, 0x1)
38 #define av1_dec_out_ec_byte_word AV1_DEC_REG(3, 16, 0x1)
39 #define av1_skip_mode AV1_DEC_REG(3, 26, 0x1)
[all …]
H A Drockchip_vpu2_regs.h13 #define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24))
14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16)
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0)
16 #define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24))
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16)
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0)
19 #define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24))
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16)
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0)
22 #define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24))
[all …]
/openbmc/linux/drivers/dma/ti/
H A Dk3-udma.h12 #define UDMA_REV_REG 0x0
13 #define UDMA_PERF_CTL_REG 0x4
14 #define UDMA_EMU_CTL_REG 0x8
15 #define UDMA_PSIL_TO_REG 0x10
16 #define UDMA_UTC_CTL_REG 0x1c
17 #define UDMA_CAP_REG(i) (0x20 + ((i) * 4))
18 #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
19 #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88
22 #define UDMA_CHAN_RT_CTL_REG 0x0
23 #define UDMA_CHAN_RT_SWTRIG_REG 0x8
[all …]
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c16 { DDRC_DBG1(0), 0x00000001 },
18 { DDRC_PWRCTL(0), 0x00000001 },
19 { DDRC_MSTR(0), 0xa3080020 },
20 { DDRC_MSTR2(0), 0x00000000 },
21 { DDRC_RFSHTMG(0), 0x006100E0 },
22 { DDRC_INIT0(0), 0xC003061B },
23 { DDRC_INIT1(0), 0x009D0000 },
24 { DDRC_INIT3(0), 0x00D4002D },
26 { DDRC_INIT4(0), 0x00330008 },
28 { DDRC_INIT4(0), 0x00310008 },
[all …]
H A Dlpddr4_timing.c15 { DDRC_DBG1(0), 0x00000001 },
16 { DDRC_PWRCTL(0), 0x00000001 },
17 { DDRC_MSTR(0), 0xa3080020 },
18 { DDRC_MSTR2(0), 0x00000000 },
19 { DDRC_RFSHTMG(0), 0x006100E0 },
20 { DDRC_INIT0(0), 0xC003061B },
21 { DDRC_INIT1(0), 0x009D0000 },
22 { DDRC_INIT3(0), 0x00D4002D },
24 { DDRC_INIT4(0), 0x00330008 },
26 { DDRC_INIT4(0), 0x00310008 },
[all …]
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dthermal-sensor.yaml35 0 on sensor nodes with only a single sensor and at least 1 on nodes
37 enum: [0, 1]
57 reg = <0 0x0c263000 0 0x1ff>, /* TM */
58 <0 0x0c222000 0 0x1ff>; /* SROT */
68 reg = <0 0x0c265000 0 0x1ff>, /* TM */
69 <0 0x0c223000 0 0x1ff>; /* SROT */
/openbmc/linux/drivers/gpu/host1x/hw/
H A Dhw_host1x01_sync.h29 * <x> value 'r' after being shifted to place its LSB at bit 0.
46 return 0x400 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
52 return 0x40 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
58 return 0x60 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
64 return 0x68 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
70 return 0x80 + channel * REGISTER_STRIDE; in host1x_sync_cf_setup_r()
76 return (r >> 0) & 0x1ff; in host1x_sync_cf_setup_base_v()
82 return (r >> 16) & 0x1ff; in host1x_sync_cf_setup_limit_v()
88 return 0xac; in host1x_sync_cmdproc_stop_r()
94 return 0xb0; in host1x_sync_ch_teardown_r()
[all …]
/openbmc/linux/drivers/thermal/tegra/
H A Dtegra210-soctherm.c24 #define TEGRA210_THERMTRIP_ANY_EN_MASK (0x1 << 31)
25 #define TEGRA210_THERMTRIP_MEM_EN_MASK (0x1 << 30)
26 #define TEGRA210_THERMTRIP_GPU_EN_MASK (0x1 << 29)
27 #define TEGRA210_THERMTRIP_CPU_EN_MASK (0x1 << 28)
28 #define TEGRA210_THERMTRIP_TSENSE_EN_MASK (0x1 << 27)
29 #define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK (0x1ff << 18)
30 #define TEGRA210_THERMTRIP_CPU_THRESH_MASK (0x1ff << 9)
31 #define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK 0x1ff
33 #define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK (0x1ff << 18)
34 #define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK (0x1ff << 9)
[all …]
/openbmc/linux/drivers/staging/media/rkvdec/
H A Drkvdec-regs.h7 #define RKVDEC_REG_INTERRUPT 0x004
8 #define RKVDEC_INTERRUPT_DEC_E BIT(0)
32 #define RKVDEC_REG_SYSCTRL 0x008
33 #define RKVDEC_IN_ENDIAN BIT(0)
44 #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
45 #define RKVDEC_MODE(x) (((x) & 0x03) << 20)
55 #define RKVDEC_REG_PICPAR 0x00C
56 #define RKVDEC_Y_HOR_VIRSTRIDE(x) ((x) & 0x1ff)
58 #define RKVDEC_UV_HOR_VIRSTRIDE(x) (((x) & 0x1ff) << 12)
59 #define RKVDEC_SLICE_NUM_LOWBITS(x) (((x) & 0x7ff) << 21)
[all …]
/openbmc/linux/drivers/net/dsa/
H A Dbcm_sf2_regs.h13 REG_SWITCH_CNTRL = 0,
36 #define MDIO_MASTER_SEL (1 << 0)
39 #define SF2_REV_MASK 0xffff
41 #define SWITCH_TOP_REV_MASK 0xffff
44 #define PHY_REVISION_MASK 0xffff
47 #define IDDQ_BIAS (1 << 0)
54 #define PHY_PHYAD_MASK 0x1F
57 #define CROSSBAR_BCM4908_INT_P7 0
59 #define CROSSBAR_BCM4908_EXT_SERDES 0
64 #define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0
[all …]
/openbmc/linux/drivers/clk/sifive/
H A Dsifive-prci.h28 #define PRCI_COREPLLCFG0_OFFSET 0x4
29 #define PRCI_COREPLLCFG0_DIVR_SHIFT 0
30 #define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
32 #define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
34 #define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
36 #define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
38 #define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
40 #define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
42 #define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
45 #define PRCI_COREPLLCFG1_OFFSET 0x8
[all …]
/openbmc/linux/drivers/mtd/nand/raw/ingenic/
H A Djz4740_ecc.c19 #define JZ_REG_NAND_ECC_CTRL 0x00
20 #define JZ_REG_NAND_DATA 0x04
21 #define JZ_REG_NAND_PAR0 0x08
22 #define JZ_REG_NAND_PAR1 0x0C
23 #define JZ_REG_NAND_PAR2 0x10
24 #define JZ_REG_NAND_IRQ_STAT 0x14
25 #define JZ_REG_NAND_IRQ_CTRL 0x18
26 #define JZ_REG_NAND_ERR(x) (0x1C + ((x) << 2))
32 #define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
39 #define JZ_NAND_STATUS_ERROR BIT(0)
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dau1200fb.h33 #define AU1200_LCD_ADDR 0xB5000000
64 uint32 reserved2[(0x0100-0x0058)/4];
77 uint32 reserved3[(0x0400-0x0180)/4];
79 volatile uint32 palette[(0x0800-0x0400)/4];
86 #define LCD_SCREEN_SX (0x07FF<<19)
87 #define LCD_SCREEN_SY (0x07FF<< 8)
90 #define LCD_SCREEN_PT (7<<0)
91 #define LCD_SCREEN_PT_TFT (0<<0)
94 #define LCD_SCREEN_PT_CSTN (1<<0)
95 #define LCD_SCREEN_PT_CDSTN (2<<0)
[all …]
/openbmc/linux/drivers/gpu/ipu-v3/
H A Dipu-ic.c18 #define IC_CONF 0x0000
19 #define IC_PRP_ENC_RSC 0x0004
20 #define IC_PRP_VF_RSC 0x0008
21 #define IC_PP_RSC 0x000C
22 #define IC_CMBP_1 0x0010
23 #define IC_CMBP_2 0x0014
24 #define IC_IDMAC_1 0x0018
25 #define IC_IDMAC_2 0x001C
26 #define IC_IDMAC_3 0x0020
27 #define IC_IDMAC_4 0x0024
[all …]
/openbmc/libcper/generator/sections/
H A Dgen-section-pci-bus.c23 *validation &= 0x1FF; //Validation 9-63 in generate_section_pci_bus()
25 *validation = 0x1FF; in generate_section_pci_bus()
27 *validation = 0x155; in generate_section_pci_bus()
30 *reserved = 0; in generate_section_pci_bus()
32 *bus_command &= ((UINT64)0x1 << 56); //Bus command bytes bar bit 56. in generate_section_pci_bus()
/openbmc/linux/drivers/memory/tegra/
H A Dmc.h15 #define MC_INTSTATUS 0x00
16 #define MC_INTMASK 0x04
17 #define MC_ERR_STATUS 0x08
18 #define MC_ERR_ADR 0x0c
19 #define MC_GART_ERROR_REQ 0x30
20 #define MC_EMEM_ADR_CFG 0x54
21 #define MC_DECERR_EMEM_OTHERS_STATUS 0x58
22 #define MC_SECURITY_VIOLATION_STATUS 0x74
23 #define MC_EMEM_ARB_CFG 0x90
24 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9_smc.h22 #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x04)
23 #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x08)
24 #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x0C)
29 u32 setup; /* 0x00 SMC Setup Register */
30 u32 pulse; /* 0x04 SMC Pulse Register */
31 u32 cycle; /* 0x08 SMC Cycle Register */
32 u32 mode; /* 0x0C SMC Mode Register */
41 #define AT91_SMC_SETUP_NWE(x) (x & 0x3f)
42 #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8)
43 #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16)
[all …]
H A Dsama5d3_smc.h13 #define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600)
14 #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604)
15 #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608)
16 #define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x60c)
17 #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x610)
20 u32 setup; /* 0x600 SMC Setup Register */
21 u32 pulse; /* 0x604 SMC Pulse Register */
22 u32 cycle; /* 0x608 SMC Cycle Register */
23 u32 timings; /* 0x60C SMC Cycle Register */
24 u32 mode; /* 0x610 SMC Mode Register */
[all …]
H A Dsama5d2_smc.h13 #define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x700)
14 #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x704)
15 #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x708)
16 #define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x70c)
17 #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x710)
20 u32 setup; /* 0x600 SMC Setup Register */
21 u32 pulse; /* 0x604 SMC Pulse Register */
22 u32 cycle; /* 0x608 SMC Cycle Register */
23 u32 timings; /* 0x60C SMC Cycle Register */
24 u32 mode; /* 0x610 SMC Mode Register */
[all …]
/openbmc/u-boot/tools/
H A Datmelimage.c62 for (pos = 0; pos < ARRAY_SIZE(configs); pos++) { in atmel_find_pmecc_parameter_in_token()
63 if (strncmp(token, configs[pos], strlen(configs[pos])) == 0) { in atmel_find_pmecc_parameter_in_token()
72 case 0: in atmel_find_pmecc_parameter_in_token()
122 for (pos = 0; pos < ARRAY_SIZE(nand_pmecc_header); pos++) in atmel_verify_header()
123 if (ints[pos] >> 28 != 0xC) in atmel_verify_header()
132 for (pos = 0; pos < 7; pos++) { in atmel_verify_header()
133 debug("atmelimage: interrupt vector #%zu is 0x%08X\n", pos+1, in atmel_verify_header()
142 if ((ints[pos] & 0xff000000) == 0xea000000) in atmel_verify_header()
145 if ((ints[pos] & 0xfffff000) == 0xe59ff000) in atmel_verify_header()
146 /* valid LDR (I=0, P=1, U=1, B=0, W=0, L=1) */ in atmel_verify_header()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/
H A Dvlv_sideband_reg.h10 #define BUNIT_REG_BISOC 0x11
13 #define _SSPM0_SSC(val) ((val) << 0)
14 #define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
15 #define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
16 #define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
17 #define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
18 #define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
20 #define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
21 #define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
22 #define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
[all …]
/openbmc/linux/drivers/media/dvb-frontends/drx39xyj/
H A Ddrxj_map.h37 * Generated by: IDF:x 1.3.0
56 #define ATV_COMM_EXEC__A 0xC00000
58 #define ATV_COMM_EXEC__M 0x3
59 #define ATV_COMM_EXEC__PRE 0x0
60 #define ATV_COMM_EXEC_STOP 0x0
61 #define ATV_COMM_EXEC_ACTIVE 0x1
62 #define ATV_COMM_EXEC_HOLD 0x2
64 #define ATV_COMM_STATE__A 0xC00001
66 #define ATV_COMM_STATE__M 0xFFFF
67 #define ATV_COMM_STATE__PRE 0x0
[all …]
/openbmc/linux/include/video/
H A Dpmagb-b-fb.h16 #define PMAGB_B_ROM 0x000000 /* REX option ROM */
17 #define PMAGB_B_SFB 0x100000 /* SFB ASIC */
18 #define PMAGB_B_GP0 0x140000 /* general purpose output 0 */
19 #define PMAGB_B_GP1 0x180000 /* general purpose output 1 */
20 #define PMAGB_B_BT459 0x1c0000 /* Bt459 RAMDAC */
21 #define PMAGB_B_FBMEM 0x200000 /* frame buffer */
22 #define PMAGB_B_SIZE 0x400000 /* address space size */
25 #define SFB_REG_VID_HOR 0x64 /* video horizontal setup */
26 #define SFB_REG_VID_VER 0x68 /* video vertical setup */
27 #define SFB_REG_VID_BASE 0x6c /* video base address */
[all …]

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