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/openbmc/linux/arch/sh/boards/mach-sh03/
H A Dsetup.c26 [0] = {
27 .start = 0x1f0,
28 .end = 0x1f0 + 8,
32 .start = 0x1f0 + 0x206,
33 .end = 0x1f0 +8 + 0x206 + 8,
50 [0] = {
51 .start = 0xa0800000,
52 .end = 0xa0800000,
84 /* IDE cmd address : 0x1f0-0x1f7 and 0x3f6 */ in sh03_devices_setup()
85 cf_ide_resources[0].start += (unsigned long)cf_ide_base; in sh03_devices_setup()
[all …]
/openbmc/linux/arch/sh/boards/mach-lboxre2/
H A Dsetup.c19 [0] = {
20 .start = 0x1f0,
21 .end = 0x1f0 + 8 ,
25 .start = 0x1f0 + 0x206,
26 .end = 0x1f0 +8 + 0x206 + 8,
62 cf_ide_resources[0].start += cf0_io_base ; in lboxre2_devices_setup()
63 cf_ide_resources[0].end += cf0_io_base ; in lboxre2_devices_setup()
/openbmc/linux/arch/sh/boards/mach-se/7721/
H A Dsetup.c41 [0] = {
42 .start = PA_MRSHPC_IO + 0x1f0,
43 .end = PA_MRSHPC_IO + 0x1f0 + 8 ,
47 .start = PA_MRSHPC_IO + 0x1f0 + 0x206,
48 .end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8,
79 __raw_writew(0x0000, 0xA405010C); /* PGCR */ in se7721_setup()
80 __raw_writew(0x0000, 0xA405010E); /* PHCR */ in se7721_setup()
81 __raw_writew(0x00AA, 0xA4050118); /* PPCR */ in se7721_setup()
82 __raw_writew(0x0000, 0xA4050124); /* PSELA */ in se7721_setup()
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_5_0_sm8150.h12 .max_mixer_blendstages = 0xb,
26 .base = 0x0, .len = 0x45c,
29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_5_1_sc8180x.h12 .max_mixer_blendstages = 0xb,
26 .base = 0x0, .len = 0x45c,
29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_5_4_sm6125.h13 .max_mixer_blendstages = 0x6,
24 .base = 0x0, .len = 0x45c,
25 .features = 0,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
36 .base = 0x1000, .len = 0x1e0,
41 .base = 0x1200, .len = 0x1e0,
46 .base = 0x1400, .len = 0x1e0,
51 .base = 0x1600, .len = 0x1e0,
[all …]
/openbmc/linux/arch/sh/boards/mach-se/7722/
H A Dsetup.c46 [0] = {
48 .start = PA_LAN + 0x300,
49 .end = PA_LAN + 0x300 + 0x10 ,
60 .id = 0,
63 .coherent_dma_mask = 0xffffffff,
71 [0] = {
72 .start = PA_MRSHPC_IO + 0x1f0,
73 .end = PA_MRSHPC_IO + 0x1f0 + 8 ,
77 .start = PA_MRSHPC_IO + 0x1f0 + 0x206,
78 .end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8,
[all …]
/openbmc/linux/arch/sh/boards/mach-se/770x/
H A Dsetup.c37 smsc_config(ACTIVATE_INDEX, 0x01); in smsc_setup()
42 smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */ in smsc_setup()
43 smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */ in smsc_setup()
47 smsc_config(ACTIVATE_INDEX, 0x01); in smsc_setup()
48 smsc_config(IO_BASE_HI_INDEX, 0x03); in smsc_setup()
49 smsc_config(IO_BASE_LO_INDEX, 0xf8); in smsc_setup()
54 smsc_config(ACTIVATE_INDEX, 0x01); in smsc_setup()
55 smsc_config(IO_BASE_HI_INDEX, 0x02); in smsc_setup()
56 smsc_config(IO_BASE_LO_INDEX, 0xf8); in smsc_setup()
61 smsc_config(ACTIVATE_INDEX, 0x01); in smsc_setup()
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dtpc0_qm_masks.h23 #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
H A Dnic0_qm0_masks.h23 #define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
H A Dmme0_qm_masks.h23 #define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
H A Ddma0_qm_masks.h23 #define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
/openbmc/linux/arch/sh/boards/mach-hp6xx/
H A Dsetup.c21 #define SCPCR 0xa4000116
22 #define SCPDR 0xa4000136
26 [0] = {
27 .start = 0x15000000 + 0x1f0,
28 .end = 0x15000000 + 0x1f0 + 0x08 - 0x01,
32 .start = 0x15000000 + 0x1fe,
33 .end = 0x15000000 + 0x1fe + 0x01,
37 .start = evt2irq(0xba0),
87 sh_dac_output(0, pdata->channel); in dac_audio_stop()
149 sh_dac_output(0, DAC_SPEAKER_VOLUME); in hp6xx_setup()
/openbmc/linux/drivers/ata/
H A Dpata_legacy.c70 module_param(probe_all, int, 0);
74 static int probe_mask = ~0;
75 module_param(probe_mask, int, 0);
79 module_param(autospeed, int, 0);
83 module_param(pio_mask, int, 0);
86 static int iordy_mask = 0xFFFFFFFF;
87 module_param(iordy_mask, int, 0);
91 module_param(ht6560a, int, 0);
95 module_param(ht6560b, int, 0);
99 module_param(opti82c611a, int, 0);
[all …]
/openbmc/qemu/hw/misc/
H A Dbcm2835_mphi.c36 qemu_set_irq(s->irq, 0); in mphi_lower_irq()
42 uint32_t val = 0; in mphi_reg_read()
45 case 0x28: /* outdda */ in mphi_reg_read()
48 case 0x2c: /* outddb */ in mphi_reg_read()
51 case 0x4c: /* ctrl */ in mphi_reg_read()
55 case 0x50: /* intstat */ in mphi_reg_read()
58 case 0x1f0: /* swirq_set */ in mphi_reg_read()
61 case 0x1f4: /* swirq_clr */ in mphi_reg_read()
75 int do_irq = 0; in mphi_reg_write()
78 case 0x28: /* outdda */ in mphi_reg_write()
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_edma0_qm_masks.h24 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
H A Dpdma0_qm_masks.h24 #define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
/openbmc/u-boot/include/configs/
H A Defi-x86_payload.h17 #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
18 "stdout=serial,vidconsole\0" \
19 "stderr=serial,vidconsole\0"
24 #define CONFIG_SYS_ATA_BASE_ADDR 0
25 #define CONFIG_SYS_ATA_DATA_OFFSET 0
26 #define CONFIG_SYS_ATA_REG_OFFSET 0
27 #define CONFIG_SYS_ATA_ALT_OFFSET 0
28 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
29 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
H A Dcoreboot.h17 #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
18 "stdout=serial,vidconsole\0" \
19 "stderr=serial,vidconsole\0"
24 #define CONFIG_SYS_ATA_BASE_ADDR 0
25 #define CONFIG_SYS_ATA_DATA_OFFSET 0
26 #define CONFIG_SYS_ATA_REG_OFFSET 0
27 #define CONFIG_SYS_ATA_ALT_OFFSET 0
28 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
29 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
H A Dqemu-x86.h17 #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \
18 "stdout=serial,vidconsole\0" \
19 "stderr=serial,vidconsole\0"
28 #define CONFIG_SYS_ATA_BASE_ADDR 0
29 #define CONFIG_SYS_ATA_DATA_OFFSET 0
30 #define CONFIG_SYS_ATA_REG_OFFSET 0
31 #define CONFIG_SYS_ATA_ALT_OFFSET 0
32 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
33 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
38 #define CONFIG_SPL_TEXT_BASE 0xfffd0000
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-v4_20.h10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88
11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90
13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
20 #define QSERDES_V4_20_RX_DFE_3 0x110
21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
[all …]
/openbmc/linux/include/dt-bindings/clock/
H A Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
H A Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53-tx53.dtsi55 reg = <0x70000000 0>;
69 clock-frequency = <0>;
75 #clock-cells = <0>;
82 pinctrl-0 = <&pinctrl_gpio_key>;
95 pinctrl-0 = <&pinctrl_stk5led>;
124 pinctrl-0 = <&pinctrl_can_xcvr>;
134 pinctrl-0 = <&pinctrl_usbh1_vbus>;
145 pinctrl-0 = <&pinctrl_usbotg_vbus>;
167 pinctrl-0 = <&pinctrl_ssi1>;
173 pinctrl-0 = <&pinctrl_can1>;
[all …]
/openbmc/u-boot/include/
H A Dcortina.h11 #define VILLA_GLOBAL_CHIP_ID_LSB 0x000
12 #define VILLA_GLOBAL_CHIP_ID_MSB 0x001
13 #define VILLA_GLOBAL_BIST_CONTROL 0x002
14 #define VILLA_GLOBAL_BIST_STATUS 0x003
15 #define VILLA_GLOBAL_LINE_SOFT_RESET 0x007
16 #define VILLA_GLOBAL_HOST_SOFT_RESET 0x008
17 #define VILLA_GLOBAL_DWNLD_CHECKSUM_CTRL 0x00A
18 #define VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS 0x00B
19 #define VILLA_GLOBAL_MSEQCLKCTRL 0x00E
20 #define VILLA_MSEQ_OPTIONS 0x1D0
[all …]

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