1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DCORE0_EDMA0_QM 19*e65e175bSOded Gabbay * (Prototype: QMAN) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_CFG0 */ 24*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 25*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF 26*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 27*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 28*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9 29*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 30*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT 14 31*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_CFG1 */ 34*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 35*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF 36*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 37*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 38*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 39*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 40*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 41*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 42*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 43*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 44*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 45*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_CFG2 */ 48*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_SHIFT 0 49*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x1 50*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_SHIFT 1 51*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 0x2 52*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_SHIFT 4 53*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_MASK 0x10 54*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_SHIFT 5 55*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_MASK 0x20 56*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_SHIFT 6 57*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_MASK 0x40 58*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_SHIFT 7 59*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_MASK 0x80 60*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_SHIFT 8 61*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_MASK 0x100 62*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_SHIFT 9 63*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_MASK 0x200 64*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_SHIFT 10 65*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_MASK 0x400 66*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_SHIFT 11 67*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_MASK 0x800 68*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_SHIFT 12 69*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_MASK 0x1000 70*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_SHIFT 13 71*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_MASK 0x2000 72*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_SHIFT 14 73*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_MASK 0x4000 74*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_SHIFT 15 75*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_MASK 0x8000 76*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_SHIFT 16 77*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_MASK 0x10000 78*e65e175bSOded Gabbay 79*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_ERR_CFG */ 80*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 81*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF 82*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 83*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 84*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 85*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 86*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 87*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 88*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 89*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 90*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 91*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 92*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 93*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 94*e65e175bSOded Gabbay 95*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_ERR_CFG1 */ 96*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT 0 97*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x1 98*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT 1 99*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_MASK 0x2 100*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT 2 101*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_MASK 0x4 102*e65e175bSOded Gabbay 103*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN */ 104*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_SHIFT 0 105*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_MASK 0xFFFFFF 106*e65e175bSOded Gabbay 107*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_AXCACHE */ 108*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AR_SHIFT 0 109*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AR_MASK 0xF 110*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AW_SHIFT 16 111*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AW_MASK 0xF0000 112*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AW_SHIFT 20 113*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AW_MASK 0xF00000 114*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AR_SHIFT 24 115*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AR_MASK 0xF000000 116*e65e175bSOded Gabbay 117*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_STS0 */ 118*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 119*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF 120*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 121*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 122*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 123*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 124*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 125*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 126*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 127*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 128*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 129*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 130*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 131*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 132*e65e175bSOded Gabbay 133*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_STS1 */ 134*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_SHIFT 0 135*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 0x1 136*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_SHIFT 1 137*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_MASK 0x2 138*e65e175bSOded Gabbay 139*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_ERR_STS */ 140*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_SHIFT 0 141*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_MASK 0x1 142*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_SHIFT 1 143*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_MASK 0x2 144*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_SHIFT 2 145*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_MASK 0x4 146*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_SHIFT 3 147*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK 0x8 148*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_SHIFT 4 149*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_MASK 0x10 150*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_SHIFT 5 151*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_MASK 0x20 152*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_SHIFT 6 153*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_MASK 0x40 154*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_SHIFT 8 155*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_MASK 0x100 156*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_SHIFT 9 157*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_MASK 0x200 158*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_SHIFT 10 159*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_MASK 0x400 160*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_SHIFT 11 161*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_MASK 0x800 162*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_SHIFT 12 163*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_MASK 0x1000 164*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_SHIFT 13 165*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_MASK 0x2000 166*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_SHIFT 14 167*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_MASK 0x4000 168*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_SHIFT 15 169*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_MASK 0x8000 170*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_SHIFT 16 171*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_MASK 0x10000 172*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_SHIFT 17 173*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_MASK 0x20000 174*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_RSVD_18_24_SHIFT 18 175*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_RSVD_18_24_MASK 0x1FC0000 176*e65e175bSOded Gabbay 177*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_ERR_STS_4 */ 178*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD0_SHIFT 0 179*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD0_MASK 0x1 180*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_SHIFT 1 181*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_MASK 0x2 182*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_SHIFT 2 183*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_MASK 0x4 184*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_SHIFT 3 185*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_MASK 0x8 186*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_SHIFT 4 187*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_MASK 0x10 188*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_SHIFT 5 189*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_MASK 0x20 190*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_SHIFT 6 191*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_MASK 0x40 192*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_SHIFT 8 193*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_MASK 0x100 194*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_SHIFT 9 195*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_MASK 0x200 196*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_SHIFT 10 197*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_MASK 0x400 198*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_SHIFT 11 199*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_MASK 0x800 200*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_SHIFT 12 201*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_MASK 0x1000 202*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_SHIFT 13 203*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_MASK 0x2000 204*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_SHIFT 14 205*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_MASK 0x4000 206*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_SHIFT 15 207*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_MASK 0x8000 208*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_SHIFT 16 209*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_MASK 0x10000 210*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD17_SHIFT 17 211*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD17_MASK 0x20000 212*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18 213*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000 214*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_SHIFT 19 215*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_MASK 0x80000 216*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_SHIFT 20 217*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_MASK 0x100000 218*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21 219*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000 220*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22 221*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000 222*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_SHIFT 23 223*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_MASK 0x800000 224*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_SHIFT 24 225*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_MASK 0x1000000 226*e65e175bSOded Gabbay 227*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN */ 228*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_SHIFT 0 229*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_MASK 0x1 230*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_SHIFT 1 231*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_MASK 0x2 232*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_SHIFT 2 233*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_MASK 0x4 234*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 235*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 236*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_SHIFT 4 237*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_MASK 0x10 238*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 239*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 240*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_SHIFT 6 241*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_MASK 0x40 242*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 243*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 244*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 245*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 246*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 247*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 248*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 249*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 250*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 251*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 252*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 253*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 254*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 255*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 256*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 257*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 258*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_SHIFT 16 259*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_MASK 0x10000 260*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_SHIFT 17 261*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_MASK 0x20000 262*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_SHIFT 18 263*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_MASK 0x1FC0000 264*e65e175bSOded Gabbay 265*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4 */ 266*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_SHIFT 0 267*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_MASK 0x1 268*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_SHIFT 1 269*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_MASK 0x2 270*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_SHIFT 2 271*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_MASK 0x4 272*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 273*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 274*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_SHIFT 4 275*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_MASK 0x10 276*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 277*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 278*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_SHIFT 6 279*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_MASK 0x40 280*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 281*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 282*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 283*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 284*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 285*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 286*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 287*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 288*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 289*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 290*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 291*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 292*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 293*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 294*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 295*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 296*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_SHIFT 16 297*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_MASK 0x10000 298*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_SHIFT 17 299*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_MASK 0x20000 300*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18 301*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000 302*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_SHIFT 19 303*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_MASK 0x80000 304*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_SHIFT 20 305*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_MASK 0x100000 306*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21 307*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000 308*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22 309*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000 310*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_SHIFT 23 311*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_MASK 0x800000 312*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_SHIFT 24 313*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_MASK 0x1000000 314*e65e175bSOded Gabbay 315*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_PROT */ 316*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_PQF_SHIFT 0 317*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_PQF_MASK 0xF 318*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_CQF_SHIFT 4 319*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_CQF_MASK 0x1F0 320*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_CP_SHIFT 9 321*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_CP_MASK 0x3E00 322*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_ERR_SHIFT 14 323*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_ERR_MASK 0x4000 324*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_ARB_SHIFT 15 325*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_ARB_MASK 0x8000 326*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_PQC_SHIFT 16 327*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_PQC_MASK 0x10000 328*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_SHIFT 17 329*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_MASK 0x20000 330*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_SHIFT 18 331*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_MASK 0x40000 332*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_CQ_CTL_MSG_SHIFT 19 333*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_CQ_CTL_MSG_MASK 0x80000 334*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_SHIFT 20 335*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_MASK 0x100000 336*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_CP_WR_ARC_SHIFT 21 337*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_CP_WR_ARC_MASK 0x200000 338*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQF_SHIFT 22 339*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQF_MASK 0x400000 340*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CORE_SHIFT 23 341*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CORE_MASK 0x800000 342*e65e175bSOded Gabbay 343*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQ_BASE_LO */ 344*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_BASE_LO_VAL_SHIFT 0 345*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF 346*e65e175bSOded Gabbay 347*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQ_BASE_HI */ 348*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_BASE_HI_VAL_SHIFT 0 349*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF 350*e65e175bSOded Gabbay 351*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQ_SIZE */ 352*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_SIZE_VAL_SHIFT 0 353*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_SIZE_VAL_MASK 0x1F 354*e65e175bSOded Gabbay 355*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQ_PI */ 356*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_PI_VAL_SHIFT 0 357*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF 358*e65e175bSOded Gabbay 359*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQ_CI */ 360*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_CI_VAL_SHIFT 0 361*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF 362*e65e175bSOded Gabbay 363*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQ_CFG0 */ 364*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_CFG0_FORCE_STALL_SHIFT 0 365*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_CFG0_FORCE_STALL_MASK 0x1 366*e65e175bSOded Gabbay 367*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQ_CFG1 */ 368*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 369*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFF 370*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 371*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 372*e65e175bSOded Gabbay 373*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQ_STS0 */ 374*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_STS0_CREDIT_CNT_SHIFT 0 375*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_STS0_CREDIT_CNT_MASK 0xFF 376*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_STS0_FREE_CNT_SHIFT 8 377*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_STS0_FREE_CNT_MASK 0xFF00 378*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_STS0_INFLIGHT_CNT_SHIFT 16 379*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 380*e65e175bSOded Gabbay 381*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQ_STS1 */ 382*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_STS1_BUF_EMPTY_SHIFT 0 383*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_STS1_BUF_EMPTY_MASK 0x1 384*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_STS1_BUSY_SHIFT 1 385*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQ_STS1_BUSY_MASK 0x2 386*e65e175bSOded Gabbay 387*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_CFG0 */ 388*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CFG0_IF_B2B_EN_SHIFT 0 389*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CFG0_IF_B2B_EN_MASK 0x1 390*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CFG0_IF_MSG_EN_SHIFT 1 391*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CFG0_IF_MSG_EN_MASK 0x2 392*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CFG0_CTL_MSG_EN_SHIFT 2 393*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CFG0_CTL_MSG_EN_MASK 0x4 394*e65e175bSOded Gabbay 395*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_STS0 */ 396*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_STS0_CREDIT_CNT_SHIFT 0 397*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_STS0_CREDIT_CNT_MASK 0xFF 398*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_STS0_FREE_CNT_SHIFT 8 399*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_STS0_FREE_CNT_MASK 0xFF00 400*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_STS0_INFLIGHT_CNT_SHIFT 16 401*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 402*e65e175bSOded Gabbay 403*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_CFG1 */ 404*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 405*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFF 406*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 407*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 408*e65e175bSOded Gabbay 409*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_STS1 */ 410*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_STS1_BUF_EMPTY_SHIFT 0 411*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_STS1_BUF_EMPTY_MASK 0x1 412*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_STS1_BUSY_SHIFT 1 413*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_STS1_BUSY_MASK 0x2 414*e65e175bSOded Gabbay 415*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_PTR_LO_0 */ 416*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 417*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF 418*e65e175bSOded Gabbay 419*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_PTR_HI_0 */ 420*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 421*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF 422*e65e175bSOded Gabbay 423*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_TSIZE_0 */ 424*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0 425*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF 426*e65e175bSOded Gabbay 427*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_CTL_0 */ 428*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_0_UP_SHIFT 28 429*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_0_UP_MASK 0xF0000000 430*e65e175bSOded Gabbay 431*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_PTR_LO_1 */ 432*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 433*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF 434*e65e175bSOded Gabbay 435*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_PTR_HI_1 */ 436*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 437*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF 438*e65e175bSOded Gabbay 439*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_TSIZE_1 */ 440*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0 441*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF 442*e65e175bSOded Gabbay 443*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_CTL_1 */ 444*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_1_UP_SHIFT 28 445*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_1_UP_MASK 0xF0000000 446*e65e175bSOded Gabbay 447*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_PTR_LO_2 */ 448*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 449*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF 450*e65e175bSOded Gabbay 451*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_PTR_HI_2 */ 452*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 453*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF 454*e65e175bSOded Gabbay 455*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_TSIZE_2 */ 456*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0 457*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF 458*e65e175bSOded Gabbay 459*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_CTL_2 */ 460*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_2_UP_SHIFT 28 461*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_2_UP_MASK 0xF0000000 462*e65e175bSOded Gabbay 463*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_PTR_LO_3 */ 464*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 465*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF 466*e65e175bSOded Gabbay 467*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_PTR_HI_3 */ 468*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 469*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF 470*e65e175bSOded Gabbay 471*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_TSIZE_3 */ 472*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0 473*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF 474*e65e175bSOded Gabbay 475*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_CTL_3 */ 476*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_3_UP_SHIFT 28 477*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_3_UP_MASK 0xF0000000 478*e65e175bSOded Gabbay 479*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_PTR_LO_4 */ 480*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 481*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF 482*e65e175bSOded Gabbay 483*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_PTR_HI_4 */ 484*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 485*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF 486*e65e175bSOded Gabbay 487*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_TSIZE_4 */ 488*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0 489*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF 490*e65e175bSOded Gabbay 491*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_CTL_4 */ 492*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_4_UP_SHIFT 28 493*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_4_UP_MASK 0xF0000000 494*e65e175bSOded Gabbay 495*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_TSIZE_STS */ 496*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 497*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF 498*e65e175bSOded Gabbay 499*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_PTR_LO_STS */ 500*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 501*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF 502*e65e175bSOded Gabbay 503*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_PTR_HI_STS */ 504*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 505*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF 506*e65e175bSOded Gabbay 507*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_IFIFO_STS */ 508*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CNT_SHIFT 0 509*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CNT_MASK 0x7 510*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_IFIFO_STS_RDY_SHIFT 4 511*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_IFIFO_STS_RDY_MASK 0x10 512*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CTL_STALL_SHIFT 8 513*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CTL_STALL_MASK 0x100 514*e65e175bSOded Gabbay 515*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO */ 516*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 517*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF 518*e65e175bSOded Gabbay 519*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI */ 520*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 521*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF 522*e65e175bSOded Gabbay 523*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO */ 524*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 525*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF 526*e65e175bSOded Gabbay 527*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI */ 528*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 529*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF 530*e65e175bSOded Gabbay 531*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO */ 532*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 533*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF 534*e65e175bSOded Gabbay 535*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI */ 536*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 537*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF 538*e65e175bSOded Gabbay 539*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO */ 540*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 541*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF 542*e65e175bSOded Gabbay 543*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI */ 544*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 545*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF 546*e65e175bSOded Gabbay 547*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_FENCE0_RDATA */ 548*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 549*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF 550*e65e175bSOded Gabbay 551*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_FENCE1_RDATA */ 552*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 553*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF 554*e65e175bSOded Gabbay 555*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_FENCE2_RDATA */ 556*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 557*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF 558*e65e175bSOded Gabbay 559*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_FENCE3_RDATA */ 560*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 561*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF 562*e65e175bSOded Gabbay 563*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_FENCE0_CNT */ 564*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 565*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF 566*e65e175bSOded Gabbay 567*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_FENCE1_CNT */ 568*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 569*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF 570*e65e175bSOded Gabbay 571*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_FENCE2_CNT */ 572*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 573*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF 574*e65e175bSOded Gabbay 575*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_FENCE3_CNT */ 576*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 577*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF 578*e65e175bSOded Gabbay 579*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_BARRIER_CFG */ 580*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 581*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF 582*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 583*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 584*e65e175bSOded Gabbay 585*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ 586*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 587*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFF 588*e65e175bSOded Gabbay 589*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ 590*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 591*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFF 592*e65e175bSOded Gabbay 593*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET */ 594*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 595*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFF 596*e65e175bSOded Gabbay 597*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 */ 598*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_SHIFT 0 599*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_MASK 0xFFFF 600*e65e175bSOded Gabbay 601*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 */ 602*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_SHIFT 0 603*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_MASK 0xFFFF 604*e65e175bSOded Gabbay 605*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 */ 606*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_SHIFT 0 607*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_MASK 0xFFFF 608*e65e175bSOded Gabbay 609*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 */ 610*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_SHIFT 0 611*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_MASK 0xFFFF 612*e65e175bSOded Gabbay 613*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 */ 614*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_SHIFT 0 615*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_MASK 0xFFFF 616*e65e175bSOded Gabbay 617*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_STS */ 618*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 619*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFF 620*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_ERDY_SHIFT 8 621*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_ERDY_MASK 0x100 622*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_SWITCH_EN_SHIFT 9 623*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_SWITCH_EN_MASK 0x200 624*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_MRDY_SHIFT 10 625*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_MRDY_MASK 0x400 626*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_SW_STOP_SHIFT 11 627*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_SW_STOP_MASK 0x800 628*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_FENCE_ID_SHIFT 12 629*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_FENCE_ID_MASK 0x3000 630*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 14 631*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x4000 632*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_FENCE_TARGET_SHIFT 16 633*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_FENCE_TARGET_MASK 0x3FFF0000 634*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_CUR_CQ_SHIFT 30 635*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_STS_CUR_CQ_MASK 0x40000000 636*e65e175bSOded Gabbay 637*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_CURRENT_INST_LO */ 638*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 639*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF 640*e65e175bSOded Gabbay 641*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_CURRENT_INST_HI */ 642*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 643*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF 644*e65e175bSOded Gabbay 645*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_PRED */ 646*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_PRED_VAL_SHIFT 0 647*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_PRED_VAL_MASK 0xFFFFFFFF 648*e65e175bSOded Gabbay 649*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_PRED_UPEN */ 650*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_PRED_UPEN_VAL_SHIFT 0 651*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_PRED_UPEN_VAL_MASK 0xFFFFFFFF 652*e65e175bSOded Gabbay 653*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_DBG_0 */ 654*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_DBG_0_CS_SHIFT 0 655*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_DBG_0_CS_MASK 0x1F 656*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 5 657*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x20 658*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 6 659*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x40 660*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 7 661*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x80 662*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_DBG_0_STALL_SHIFT 8 663*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_DBG_0_STALL_MASK 0x100 664*e65e175bSOded Gabbay 665*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED */ 666*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_TH_SHIFT 0 667*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_TH_MASK 0x3 668*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_VAL_SHIFT 8 669*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_VAL_MASK 0x300 670*e65e175bSOded Gabbay 671*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_IN_DATA_LO */ 672*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_IN_DATA_LO_VAL_SHIFT 0 673*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_IN_DATA_LO_VAL_MASK 0xFFFFFFFF 674*e65e175bSOded Gabbay 675*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_IN_DATA_HI */ 676*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_IN_DATA_HI_VAL_SHIFT 0 677*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_IN_DATA_HI_VAL_MASK 0xFFFFFFFF 678*e65e175bSOded Gabbay 679*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQC_HBW_BASE_LO */ 680*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_HBW_BASE_LO_VAL_SHIFT 0 681*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_HBW_BASE_LO_VAL_MASK 0xFFFFFFFF 682*e65e175bSOded Gabbay 683*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQC_HBW_BASE_HI */ 684*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_HBW_BASE_HI_VAL_SHIFT 0 685*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_HBW_BASE_HI_VAL_MASK 0xFFFFFFFF 686*e65e175bSOded Gabbay 687*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQC_SIZE */ 688*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_SIZE_VAL_SHIFT 0 689*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_SIZE_VAL_MASK 0xFFFFFFFF 690*e65e175bSOded Gabbay 691*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQC_PI */ 692*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_PI_VAL_SHIFT 0 693*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_PI_VAL_MASK 0xFFFFFFFF 694*e65e175bSOded Gabbay 695*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQC_LBW_WDATA */ 696*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_LBW_WDATA_VAL_SHIFT 0 697*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_LBW_WDATA_VAL_MASK 0xFFFFFFFF 698*e65e175bSOded Gabbay 699*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQC_LBW_BASE_LO */ 700*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_LBW_BASE_LO_VAL_SHIFT 0 701*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_LBW_BASE_LO_VAL_MASK 0xFFFFFFFF 702*e65e175bSOded Gabbay 703*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQC_LBW_BASE_HI */ 704*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_LBW_BASE_HI_VAL_SHIFT 0 705*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_LBW_BASE_HI_VAL_MASK 0xFFFFFFFF 706*e65e175bSOded Gabbay 707*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQC_CFG */ 708*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_CFG_EN_SHIFT 0 709*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_CFG_EN_MASK 0x1 710*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_CFG_DIRECT_SHIFT 4 711*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_CFG_DIRECT_MASK 0x10 712*e65e175bSOded Gabbay 713*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND */ 714*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0 715*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3 716*e65e175bSOded Gabbay 717*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_MASK */ 718*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MASK_VAL_SHIFT 0 719*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MASK_VAL_MASK 0xF 720*e65e175bSOded Gabbay 721*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_CFG_0 */ 722*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CFG_0_PRIO_TYPE_SHIFT 0 723*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CFG_0_PRIO_TYPE_MASK 0x1 724*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 725*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 726*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CFG_0_EN_SHIFT 8 727*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CFG_0_EN_MASK 0x100 728*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 9 729*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x200 730*e65e175bSOded Gabbay 731*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH */ 732*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_SHIFT 0 733*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_MASK 0x3 734*e65e175bSOded Gabbay 735*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_WRR_WEIGHT */ 736*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 737*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFF 738*e65e175bSOded Gabbay 739*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_CFG_1 */ 740*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CFG_1_CLR_SHIFT 0 741*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CFG_1_CLR_MASK 0x1 742*e65e175bSOded Gabbay 743*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED */ 744*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 745*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F 746*e65e175bSOded Gabbay 747*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_MST_CRED_INC */ 748*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 749*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF 750*e65e175bSOded Gabbay 751*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST */ 752*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_SHIFT 0 753*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_MASK 0xFFFFFFFF 754*e65e175bSOded Gabbay 755*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ 756*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 757*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF 758*e65e175bSOded Gabbay 759*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN */ 760*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 761*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF 762*e65e175bSOded Gabbay 763*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1 */ 764*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_SHIFT 0 765*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_MASK 0xFFFFFFFF 766*e65e175bSOded Gabbay 767*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT */ 768*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_SHIFT 0 769*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_MASK 0xFFFFFFFF 770*e65e175bSOded Gabbay 771*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_SLV_ID */ 772*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_SLV_ID_VAL_SHIFT 0 773*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_SLV_ID_VAL_MASK 0x7F 774*e65e175bSOded Gabbay 775*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_MST_QUIET_PER */ 776*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 777*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF 778*e65e175bSOded Gabbay 779*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT */ 780*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 781*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F 782*e65e175bSOded Gabbay 783*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_BASE_LO */ 784*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_BASE_LO_VAL_SHIFT 0 785*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF 786*e65e175bSOded Gabbay 787*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_BASE_HI */ 788*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_BASE_HI_VAL_SHIFT 0 789*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF 790*e65e175bSOded Gabbay 791*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_STATE_STS */ 792*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_STATE_STS_VAL_SHIFT 0 793*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF 794*e65e175bSOded Gabbay 795*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS */ 796*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_SHIFT 0 797*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_MASK 0x7F 798*e65e175bSOded Gabbay 799*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_MSG_STS */ 800*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MSG_STS_FULL_SHIFT 0 801*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MSG_STS_FULL_MASK 0x1 802*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 803*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 804*e65e175bSOded Gabbay 805*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD */ 806*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_SHIFT 0 807*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_MASK 0x3 808*e65e175bSOded Gabbay 809*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_ERR_CAUSE */ 810*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_SHIFT 0 811*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_MASK 0x1 812*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_SHIFT 1 813*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_MASK 0x2 814*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 815*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 816*e65e175bSOded Gabbay 817*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_ERR_MSG_EN */ 818*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_SHIFT 0 819*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_MASK 0x1 820*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_SHIFT 1 821*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_MASK 0x2 822*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 823*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 824*e65e175bSOded Gabbay 825*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_ERR_STS_DRP */ 826*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 827*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 828*e65e175bSOded Gabbay 829*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_MST_CRED_STS */ 830*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 831*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F 832*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_IDX_SHIFT 24 833*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_IDX_MASK 0x1F000000 834*e65e175bSOded Gabbay 835*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1 */ 836*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_VAL_SHIFT 0 837*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_VAL_MASK 0x7F 838*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_IDX_SHIFT 24 839*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_IDX_MASK 0x1F000000 840*e65e175bSOded Gabbay 841*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG */ 842*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_SHIFT 0 843*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_MASK 0x1 844*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_SHIFT 4 845*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_MASK 0x10 846*e65e175bSOded Gabbay 847*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_CFG0 */ 848*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_SHIFT 0 849*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_MASK 0x1 850*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_SHIFT 1 851*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_MASK 0x2 852*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_SHIFT 2 853*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_MASK 0x4 854*e65e175bSOded Gabbay 855*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_CFG1 */ 856*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_SHIFT 0 857*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_MASK 0xFF 858*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 859*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 860*e65e175bSOded Gabbay 861*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_PTR_LO */ 862*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_VAL_SHIFT 0 863*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF 864*e65e175bSOded Gabbay 865*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_PTR_HI */ 866*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_VAL_SHIFT 0 867*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF 868*e65e175bSOded Gabbay 869*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_TSIZE */ 870*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_VAL_SHIFT 0 871*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_VAL_MASK 0xFFFFFFFF 872*e65e175bSOded Gabbay 873*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_CTL */ 874*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CTL_UP_SHIFT 28 875*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CTL_UP_MASK 0xF0000000 876*e65e175bSOded Gabbay 877*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS */ 878*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CNT_SHIFT 0 879*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CNT_MASK 0x7 880*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_RDY_SHIFT 4 881*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_RDY_MASK 0x10 882*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_SHIFT 8 883*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_MASK 0x100 884*e65e175bSOded Gabbay 885*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_STS0 */ 886*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_SHIFT 0 887*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_MASK 0xFF 888*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_STS0_FREE_CNT_SHIFT 8 889*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_STS0_FREE_CNT_MASK 0xFF00 890*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_SHIFT 16 891*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 892*e65e175bSOded Gabbay 893*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_STS1 */ 894*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_SHIFT 0 895*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_MASK 0x1 896*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUSY_SHIFT 1 897*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUSY_MASK 0x2 898*e65e175bSOded Gabbay 899*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS */ 900*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS_VAL_SHIFT 0 901*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF 902*e65e175bSOded Gabbay 903*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS */ 904*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_SHIFT 0 905*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF 906*e65e175bSOded Gabbay 907*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS */ 908*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_SHIFT 0 909*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF 910*e65e175bSOded Gabbay 911*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI */ 912*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_SHIFT 0 913*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_MASK 0xFFFFFFFF 914*e65e175bSOded Gabbay 915*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO */ 916*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_SHIFT 0 917*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_MASK 0xFFFFFFFF 918*e65e175bSOded Gabbay 919*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI */ 920*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0 921*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF 922*e65e175bSOded Gabbay 923*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO */ 924*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0 925*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF 926*e65e175bSOded Gabbay 927*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI */ 928*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0 929*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF 930*e65e175bSOded Gabbay 931*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO */ 932*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0 933*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF 934*e65e175bSOded Gabbay 935*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI */ 936*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0 937*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF 938*e65e175bSOded Gabbay 939*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO */ 940*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0 941*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF 942*e65e175bSOded Gabbay 943*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI */ 944*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0 945*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF 946*e65e175bSOded Gabbay 947*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO */ 948*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0 949*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF 950*e65e175bSOded Gabbay 951*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ADDR_OVRD */ 952*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ADDR_OVRD_IDX_SHIFT 0 953*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ADDR_OVRD_IDX_MASK 0xFF 954*e65e175bSOded Gabbay 955*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_IFIFO_CI */ 956*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_IFIFO_CI_VAL_SHIFT 0 957*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF 958*e65e175bSOded Gabbay 959*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI */ 960*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI_VAL_SHIFT 0 961*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF 962*e65e175bSOded Gabbay 963*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CQ_CTL_CI */ 964*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_CI_VAL_SHIFT 0 965*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF 966*e65e175bSOded Gabbay 967*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_CQ_CTL_CI */ 968*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CTL_CI_VAL_SHIFT 0 969*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF 970*e65e175bSOded Gabbay 971*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_CFG */ 972*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CFG_SWITCH_EN_SHIFT 0 973*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CFG_SWITCH_EN_MASK 0x1 974*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CFG_SWITCH_WD_EN_SHIFT 1 975*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_CFG_SWITCH_WD_EN_MASK 0x2 976*e65e175bSOded Gabbay 977*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_EXT_SWITCH */ 978*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_EXT_SWITCH_VAL_SHIFT 0 979*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_EXT_SWITCH_VAL_MASK 0x1 980*e65e175bSOded Gabbay 981*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_SWITCH_WD_SET */ 982*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_SWITCH_WD_SET_VAL_SHIFT 0 983*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_SWITCH_WD_SET_VAL_MASK 0xFFFFFFFF 984*e65e175bSOded Gabbay 985*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_CP_SWITCH_WD */ 986*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_SWITCH_WD_VAL_SHIFT 0 987*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_CP_SWITCH_WD_VAL_MASK 0xFFFFFFFF 988*e65e175bSOded Gabbay 989*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO */ 990*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_SHIFT 0 991*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_MASK 0xFFFFFFFF 992*e65e175bSOded Gabbay 993*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI */ 994*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_SHIFT 0 995*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_MASK 0xFFFFFFFF 996*e65e175bSOded Gabbay 997*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI */ 998*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_SHIFT 0 999*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF 1000*e65e175bSOded Gabbay 1001*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO */ 1002*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_SHIFT 0 1003*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF 1004*e65e175bSOded Gabbay 1005*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE */ 1006*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_SHIFT 0 1007*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_MASK 0xFFFFFFFF 1008*e65e175bSOded Gabbay 1009*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI */ 1010*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_SHIFT 0 1011*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF 1012*e65e175bSOded Gabbay 1013*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO */ 1014*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_SHIFT 0 1015*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF 1016*e65e175bSOded Gabbay 1017*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_QM_BASE_ADDR_HI */ 1018*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_QM_BASE_ADDR_HI_VAL_SHIFT 0 1019*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_QM_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF 1020*e65e175bSOded Gabbay 1021*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_QM_BASE_ADDR_LO */ 1022*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_QM_BASE_ADDR_LO_VAL_SHIFT 0 1023*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_QM_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF 1024*e65e175bSOded Gabbay 1025*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND */ 1026*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0 1027*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3 1028*e65e175bSOded Gabbay 1029*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQC_STS_0 */ 1030*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_STS_0_COMP_DATA_SHIFT 0 1031*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_STS_0_COMP_DATA_MASK 0xFFFF 1032*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_STS_0_COMP_OFST_SHIFT 16 1033*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_STS_0_COMP_OFST_MASK 0xFFFF0000 1034*e65e175bSOded Gabbay 1035*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PQC_STS_1 */ 1036*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_SHIFT 0 1037*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_MASK 0xF 1038*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_SHIFT 4 1039*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_MASK 0x10 1040*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_SHIFT 5 1041*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_MASK 0x20 1042*e65e175bSOded Gabbay 1043*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_SEI_STATUS */ 1044*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_SEI_STATUS_QM_INT_SHIFT 0 1045*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_SEI_STATUS_QM_INT_MASK 0x1 1046*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_SEI_STATUS_ARC_INT_SHIFT 1 1047*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_SEI_STATUS_ARC_INT_MASK 0x2 1048*e65e175bSOded Gabbay 1049*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_SEI_MASK */ 1050*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_SEI_MASK_QM_INT_SHIFT 0 1051*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_SEI_MASK_QM_INT_MASK 0x1 1052*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_SEI_MASK_ARC_INT_SHIFT 1 1053*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_SEI_MASK_ARC_INT_MASK 0x2 1054*e65e175bSOded Gabbay 1055*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO */ 1056*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 1057*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF 1058*e65e175bSOded Gabbay 1059*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI */ 1060*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 1061*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF 1062*e65e175bSOded Gabbay 1063*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_GLBL_ERR_WDATA */ 1064*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 1065*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF 1066*e65e175bSOded Gabbay 1067*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_L2H_MASK_LO */ 1068*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_L2H_MASK_LO_VAL_SHIFT 20 1069*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_L2H_MASK_LO_VAL_MASK 0xFFF00000 1070*e65e175bSOded Gabbay 1071*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_L2H_MASK_HI */ 1072*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_L2H_MASK_HI_VAL_SHIFT 0 1073*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF 1074*e65e175bSOded Gabbay 1075*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_L2H_CMPR_LO */ 1076*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_L2H_CMPR_LO_VAL_SHIFT 20 1077*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_L2H_CMPR_LO_VAL_MASK 0xFFF00000 1078*e65e175bSOded Gabbay 1079*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_L2H_CMPR_HI */ 1080*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_L2H_CMPR_HI_VAL_SHIFT 0 1081*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF 1082*e65e175bSOded Gabbay 1083*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_LOCAL_RANGE_BASE */ 1084*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 1085*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF 1086*e65e175bSOded Gabbay 1087*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE */ 1088*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 1089*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF 1090*e65e175bSOded Gabbay 1091*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1 */ 1092*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 1093*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF 1094*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 1095*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 1096*e65e175bSOded Gabbay 1097*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0 */ 1098*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 1099*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF 1100*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 1101*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 1102*e65e175bSOded Gabbay 1103*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1 */ 1104*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 1105*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF 1106*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 1107*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 1108*e65e175bSOded Gabbay 1109*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0 */ 1110*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 1111*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF 1112*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 1113*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 1114*e65e175bSOded Gabbay 1115*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_IND_GW_APB_CFG */ 1116*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 1117*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF 1118*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 1119*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 1120*e65e175bSOded Gabbay 1121*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_IND_GW_APB_WDATA */ 1122*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 1123*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF 1124*e65e175bSOded Gabbay 1125*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_IND_GW_APB_RDATA */ 1126*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 1127*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF 1128*e65e175bSOded Gabbay 1129*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_IND_GW_APB_STATUS */ 1130*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 1131*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 1132*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 1133*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 1134*e65e175bSOded Gabbay 1135*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PERF_CNT_FREE_LO */ 1136*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_FREE_LO_VAL_SHIFT 0 1137*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_FREE_LO_VAL_MASK 0xFFFFFFFF 1138*e65e175bSOded Gabbay 1139*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PERF_CNT_FREE_HI */ 1140*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_FREE_HI_VAL_SHIFT 0 1141*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_FREE_HI_VAL_MASK 0xFFFFFFFF 1142*e65e175bSOded Gabbay 1143*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO */ 1144*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO_VAL_SHIFT 0 1145*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO_VAL_MASK 0xFFFFFFFF 1146*e65e175bSOded Gabbay 1147*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI */ 1148*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI_VAL_SHIFT 0 1149*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI_VAL_MASK 0xFFFFFFFF 1150*e65e175bSOded Gabbay 1151*e65e175bSOded Gabbay /* DCORE0_EDMA0_QM_PERF_CNT_CFG */ 1152*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_CFG_PQ_MASK_SHIFT 0 1153*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_CFG_PQ_MASK_MASK 0xF 1154*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_CFG_CQ_MASK_SHIFT 8 1155*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_CFG_CQ_MASK_MASK 0x1F00 1156*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_CFG_CP_MASK_SHIFT 16 1157*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_CFG_CP_MASK_MASK 0x1F0000 1158*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_CFG_AGENT_MASK_SHIFT 24 1159*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_CFG_AGENT_MASK_MASK 0x1000000 1160*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_FREE_SHIFT 30 1161*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_FREE_MASK 0x40000000 1162*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_IDLE_SHIFT 31 1163*e65e175bSOded Gabbay #define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_IDLE_MASK 0x80000000 1164*e65e175bSOded Gabbay 1165*e65e175bSOded Gabbay #endif /* ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ */ 1166