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/openbmc/u-boot/board/cssi/MCR3000/
H A Dnand.c13 #define BIT_CLE ((unsigned short)0x0800)
14 #define BIT_ALE ((unsigned short)0x0400)
15 #define BIT_NCE ((unsigned short)0x1000)
21 unsigned short pddat = 0; in nand_hwcontrol()
55 setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00); in board_nand_init()
56 clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00); in board_nand_init()
57 clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000); in board_nand_init()
63 return 0; in board_nand_init()
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Domap.h15 #define SMX_APE_BASE 0x68000000
18 #define OMAP34XX_GPMC_BASE 0x6E000000
21 #define OMAP34XX_SMS_BASE 0x6C000000
24 #define OMAP34XX_SDRC_BASE 0x6D000000
29 #define OMAP34XX_CORE_L4_IO_BASE 0x48000000
30 #define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
31 #define OMAP34XX_ID_L4_IO_BASE 0x4830A200
32 #define OMAP34XX_L4_PER 0x49000000
36 #define OMAP34XX_DMA4_BASE 0x48056000
39 #define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
[all …]
/openbmc/linux/arch/mips/include/asm/mach-ar7/
H A Dar7.h16 #define AR7_SDRAM_BASE 0x14000000
18 #define AR7_REGS_BASE 0x08610000
20 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
21 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
22 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
23 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
24 #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
25 #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
26 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
27 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
[all …]
/openbmc/linux/drivers/hwtracing/intel_th/
H A Dpti.h12 REG_PTI_CTL = 0x1c00,
15 #define PTI_EN BIT(0)
17 #define PTI_MODE 0xf0
20 #define PTI_CLKDIV 0x000f0000
21 #define PTI_PATGENMODE 0x00f00000
26 #define LPP_DEST_PTI BIT(0)
/openbmc/linux/arch/powerpc/boot/dts/
H A Dep88xc.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xfa200100 0x40>;
48 0x0 0x0 0xfc000000 0x4000000
49 0x3 0x0 0xfa000000 0x1000000
[all …]
/openbmc/linux/arch/riscv/include/asm/
H A Dkvm_aia_aplic.h14 #define APLIC_DOMAINCFG 0x0000
15 #define APLIC_DOMAINCFG_RDONLY 0x80000000
18 #define APLIC_DOMAINCFG_BE BIT(0)
20 #define APLIC_SOURCECFG_BASE 0x0004
22 #define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff
23 #define APLIC_SOURCECFG_SM_MASK 0x00000007
24 #define APLIC_SOURCECFG_SM_INACTIVE 0x0
25 #define APLIC_SOURCECFG_SM_DETACH 0x1
26 #define APLIC_SOURCECFG_SM_EDGE_RISE 0x4
27 #define APLIC_SOURCECFG_SM_EDGE_FALL 0x5
[all …]
/openbmc/linux/Documentation/devicetree/bindings/fsi/
H A Dibm,fsi2spi.yaml37 reg = <0x1c00 0x400>;
/openbmc/u-boot/configs/
H A Dchromebook_samus_defconfig2 CONFIG_SYS_TEXT_BASE=0xFFE00000
3 CONFIG_SYS_MALLOC_F_LEN=0x1c00
5 CONFIG_DEBUG_UART_BASE=0x3f8
/openbmc/linux/arch/arm/mach-omap2/
H A Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
H A Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
/openbmc/linux/drivers/bus/
H A Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
/openbmc/linux/sound/pci/ctxfi/
H A Dctmixer.h20 #define INIT_VOL 0x1c00
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/
H A Dga102.c31 .addr2 = 0x1c00,
47 return 0; in ga102_nvdec_nofw()
60 return nvkm_nvdec_new_(ga102_nvdec_fwif, device, type, inst, 0x848000, pnvdec); in ga102_nvdec_new()
/openbmc/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,rpmh-rsc.yaml78 enum: [ 0, 1, 2, 3 ]
97 - const: drv-0
115 '^regulators(-[0-9])?$':
133 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
134 // 2, the register offsets for DRV2 start at 0D00, the register
136 // DRV0: 0x179C0000
137 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
138 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
139 // TCS-OFFSET: 0xD00
145 reg = <0x179c0000 0x10000>,
[all …]
/openbmc/linux/drivers/mfd/
H A Dtimberdale.h23 #define TIMB_REV_MAJOR 0x00
24 #define TIMB_REV_MINOR 0x04
25 #define TIMB_HW_CONFIG 0x08
26 #define TIMB_SW_RST 0x40
29 #define TIMB_HW_CONFIG_SPI_8BIT 0x80
31 #define TIMB_HW_VER_MASK 0x0f
32 #define TIMB_HW_VER0 0x00
33 #define TIMB_HW_VER1 0x01
34 #define TIMB_HW_VER2 0x02
35 #define TIMB_HW_VER3 0x03
[all …]
/openbmc/linux/drivers/media/platform/renesas/rcar-vin/
H A Drcar-csi2.c31 #define TREF_REG 0x00
32 #define TREF_TREF BIT(0)
35 #define SRST_REG 0x04
36 #define SRST_SRST BIT(0)
39 #define PHYCNT_REG 0x08
46 #define PHYCNT_ENABLE_0 BIT(0)
49 #define CHKSUM_REG 0x0c
51 #define CHKSUM_CRC_EN BIT(0)
55 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1
56 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_tpc0_eml_spmu_regs.h23 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x1000
25 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008
27 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010
29 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018
31 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020
33 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028
35 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8
37 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC
39 #define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200
41 #define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204
[all …]
/openbmc/linux/drivers/edac/
H A Daltera_edac.h15 #define CV_CTLCFG_OFST 0x00
18 #define CV_CTLCFG_ECC_EN 0x400
19 #define CV_CTLCFG_ECC_CORR_EN 0x800
20 #define CV_CTLCFG_GEN_SB_ERR 0x2000
21 #define CV_CTLCFG_GEN_DB_ERR 0x4000
26 #define CV_DRAMADDRW_OFST 0x2C
29 #define DRAMADDRW_COLBIT_MASK 0x001F
30 #define DRAMADDRW_COLBIT_SHIFT 0
31 #define DRAMADDRW_ROWBIT_MASK 0x03E0
33 #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
[all …]
/openbmc/linux/include/linux/mfd/wm8350/
H A Dsupply.h17 #define WM8350_BATTERY_CHARGER_CONTROL_1 0xA8
18 #define WM8350_BATTERY_CHARGER_CONTROL_2 0xA9
19 #define WM8350_BATTERY_CHARGER_CONTROL_3 0xAA
22 * R168 (0xA8) - Battery Charger Control 1
24 #define WM8350_CHG_ENA_R168 0x8000
25 #define WM8350_CHG_THR 0x2000
26 #define WM8350_CHG_EOC_SEL_MASK 0x1C00
27 #define WM8350_CHG_TRICKLE_TEMP_CHOKE 0x0200
28 #define WM8350_CHG_TRICKLE_USB_CHOKE 0x0100
29 #define WM8350_CHG_RECOVER_T 0x0080
[all …]
/openbmc/u-boot/board/freescale/common/
H A Dcds_via.c17 pci_hose_write_config_byte(hose, dev, 0x48, 0x08); in mpc85xx_config_via()
22 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); in mpc85xx_config_via()
23 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); in mpc85xx_config_via()
27 * open from 0x00000000-0x00001fff in PCI I/O space. in mpc85xx_config_via()
31 bridge = PCI_BDF(0,BRIDGE_ID,0); in mpc85xx_config_via()
32 pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); in mpc85xx_config_via()
33 pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); in mpc85xx_config_via()
34 pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); in mpc85xx_config_via()
35 pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); in mpc85xx_config_via()
49 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8); in mpc85xx_config_via_usbide()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dtonga_baco.c40 { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },
41 { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
42 { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
43 { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff },
44 { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 },
45 { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff },
46 { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 },
47 { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 },
48 { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
49 { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Dibm-power10-dual.dtsi8 #size-cells = <0>;
10 cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
12 cfam@0,0 {
13 reg = <0 0>;
16 chip-id = <0>;
20 reg = <0x1000 0x400>;
25 reg = <0x1800 0x400>;
27 #size-cells = <0>;
29 cfam0_i2c0: i2c-bus@0 {
31 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/parport/
H A Dparport_serial.c25 titan_110l = 0,
102 dev->subsystem_device == 0x0299) in netmos_parallel_init()
110 * and serial ports. The form is 0x00PS, where <P> is the number of in netmos_parallel_init()
113 par->numports = (dev->subsystem_device & 0xf0) >> 4; in netmos_parallel_init()
118 return 0; in netmos_parallel_init()
125 /* netmos_9855 */ { 1, { { 0, -1 }, }, netmos_parallel_init },
126 /* netmos_9855_2p */ { 2, { { 0, -1 }, { 2, -1 }, } },
128 /* netmos_9900_2p */ {2, { { 0, 1 }, { 3, 4 }, } },
129 /* netmos_99xx_1p */ {1, { { 0, 1 }, } },
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_110l },
[all …]
/openbmc/linux/drivers/gpu/drm/i915/soc/
H A Dintel_pch.h19 PCH_NONE = 0, /* No PCH present */
35 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
36 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
37 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
38 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
39 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
40 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
41 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
42 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
43 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
[all …]
/openbmc/u-boot/board/renesas/rsk7203/
H A Dlowlevel_init.S91 mov #0, r2
99 mov #0, r0
108 CCR1_D: .long 0x0000090B
109 PCCRL4_A: .long 0xFFFE3910
110 PCCRL4_D0: .word 0x0000
112 PECRL4_A: .long 0xFFFE3A10
113 PECRL4_D0: .word 0x0000
115 PECRL3_A: .long 0xFFFE3A12
116 PECRL3_D: .word 0x0000
118 PEIORL_A: .long 0xFFFE3A06
[all …]

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