Lines Matching +full:0 +full:x1c00
15 #define CV_CTLCFG_OFST 0x00
18 #define CV_CTLCFG_ECC_EN 0x400
19 #define CV_CTLCFG_ECC_CORR_EN 0x800
20 #define CV_CTLCFG_GEN_SB_ERR 0x2000
21 #define CV_CTLCFG_GEN_DB_ERR 0x4000
26 #define CV_DRAMADDRW_OFST 0x2C
29 #define DRAMADDRW_COLBIT_MASK 0x001F
30 #define DRAMADDRW_COLBIT_SHIFT 0
31 #define DRAMADDRW_ROWBIT_MASK 0x03E0
33 #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
35 #define CV_DRAMADDRW_CSBIT_MASK 0xE000
39 #define CV_DRAMIFWIDTH_OFST 0x30
46 #define CV_DRAMSTS_OFST 0x38
49 #define CV_DRAMSTS_SBEERR 0x04
50 #define CV_DRAMSTS_DBEERR 0x08
51 #define CV_DRAMSTS_CORR_DROP 0x10
54 #define CV_DRAMINTR_OFST 0x3C
57 #define CV_DRAMINTR_INTREN 0x01
58 #define CV_DRAMINTR_SBEMASK 0x02
59 #define CV_DRAMINTR_DBEMASK 0x04
60 #define CV_DRAMINTR_CORRDROPMASK 0x08
61 #define CV_DRAMINTR_INTRCLR 0x10
64 #define CV_SBECOUNT_OFST 0x40
67 #define CV_DBECOUNT_OFST 0x44
70 #define CV_ERRADDR_OFST 0x48
75 #define A10_ECCCTRL1_OFST 0x00
78 #define A10_ECCCTRL1_ECC_EN 0x001
79 #define A10_ECCCTRL1_CNT_RST 0x010
80 #define A10_ECCCTRL1_AWB_CNT_RST 0x100
85 #define CV_DRAMADDRW 0xFFC2502C
86 #define A10_DRAMADDRW 0xFFCFA0A8
87 #define S10_DRAMADDRW 0xF80110E0
90 #define DRAMADDRW_COLBIT_MASK 0x001F
91 #define DRAMADDRW_COLBIT_SHIFT 0
92 #define DRAMADDRW_ROWBIT_MASK 0x03E0
94 #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
96 #define CV_DRAMADDRW_CSBIT_MASK 0xE000
99 #define A10_DRAMADDRW_BANKBIT_MASK 0x3C00
101 #define A10_DRAMADDRW_GRPBIT_MASK 0xC000
103 #define A10_DRAMADDRW_CSBIT_MASK 0x70000
107 #define CV_DRAMIFWIDTH 0xFFC25030
108 #define A10_DRAMIFWIDTH 0xFFCFB008
109 #define S10_DRAMIFWIDTH 0xF8011008
115 #define A10_DRAMIFWIDTH_16B 0x0
116 #define A10_DRAMIFWIDTH_32B 0x1
117 #define A10_DRAMIFWIDTH_64B 0x2
120 #define A10_ERRINTEN_OFST 0x10
123 #define A10_ERRINTEN_SERRINTEN 0x01
124 #define A10_ERRINTEN_DERRINTEN 0x02
129 #define A10_INTMODE_OFST 0x1C
133 #define A10_INTSTAT_OFST 0x20
136 #define A10_INTSTAT_SBEERR 0x01
137 #define A10_INTSTAT_DBEERR 0x02
140 #define A10_DERRADDR_OFST 0x2C
141 #define A10_SERRADDR_OFST 0x30
144 #define A10_DIAGINTTEST_OFST 0x24
146 #define A10_DIAGINT_TSERRA_MASK 0x0001
147 #define A10_DIAGINT_TDERRA_MASK 0x0100
153 #define A10_SERRCNTREG_OFST 0x3C
155 #define A10_SYMAN_INTMASK_CLR 0xFFD06098
156 #define A10_INTMASK_CLR_OFST 0x10
199 #define ALTR_MAN_GRP_OCRAM_ECC_OFFSET 0x04
200 #define ALTR_OCR_ECC_REG_OFFSET 0x00
201 #define ALTR_OCR_ECC_EN BIT(0)
208 #define ALTR_MAN_GRP_L2_ECC_OFFSET 0x00
209 #define ALTR_L2_ECC_REG_OFFSET 0x00
210 #define ALTR_L2_ECC_EN BIT(0)
215 #define ALTR_A10_ECC_CTRL_OFST 0x08
216 #define ALTR_A10_ECC_EN BIT(0)
220 #define ALTR_A10_ECC_INITSTAT_OFST 0x0C
221 #define ALTR_A10_ECC_INITCOMPLETEA BIT(0)
224 #define ALTR_A10_ECC_ERRINTEN_OFST 0x10
225 #define ALTR_A10_ECC_ERRINTENS_OFST 0x14
226 #define ALTR_A10_ECC_ERRINTENR_OFST 0x18
227 #define ALTR_A10_ECC_SERRINTEN BIT(0)
229 #define ALTR_A10_ECC_INTMODE_OFST 0x1C
230 #define ALTR_A10_ECC_INTMODE BIT(0)
232 #define ALTR_A10_ECC_INTSTAT_OFST 0x20
233 #define ALTR_A10_ECC_SERRPENA BIT(0)
242 #define ALTR_A10_ECC_INTTEST_OFST 0x24
243 #define ALTR_A10_ECC_TSERRA BIT(0)
249 #define A10_SYSMGR_ECC_INTMASK_SET_OFST 0x94
250 #define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
253 #define A10_SYSMGR_ECC_INTSTAT_SERR_OFST 0x9C
254 #define A10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0
255 #define A10_SYSMGR_ECC_INTSTAT_L2 BIT(0)
258 #define A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST 0xA8
263 #define ALTR_A10_L2_ECC_CTL_OFST 0x0
264 #define ALTR_A10_L2_ECC_EN_CTL BIT(0)
266 #define ALTR_A10_L2_ECC_STATUS 0xFFD060A4
267 #define ALTR_A10_L2_ECC_STAT_OFST 0xA4
268 #define ALTR_A10_L2_ECC_SERR_PEND BIT(0)
269 #define ALTR_A10_L2_ECC_MERR_PEND BIT(0)
271 #define ALTR_A10_L2_ECC_CLR_OFST 0x4
276 #define ALTR_A10_L2_ECC_CE_INJ_MASK 0x00000101
277 #define ALTR_A10_L2_ECC_UE_INJ_MASK 0x00010101
280 #define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0))
283 #define ALTR_A10_COMMON_ECC_EN_CTL BIT(0)
292 #define ALTR_S10_ECC_CTRL_SDRAM_OFST 0x00
293 #define ALTR_S10_ECC_EN BIT(0)
295 #define ALTR_S10_ECC_ERRINTEN_OFST 0x10
296 #define ALTR_S10_ECC_ERRINTENS_OFST 0x14
297 #define ALTR_S10_ECC_ERRINTENR_OFST 0x18
298 #define ALTR_S10_ECC_SERRINTEN BIT(0)
300 #define ALTR_S10_ECC_INTMODE_OFST 0x1C
301 #define ALTR_S10_ECC_INTMODE BIT(0)
303 #define ALTR_S10_ECC_INTSTAT_OFST 0x20
304 #define ALTR_S10_ECC_SERRPENA BIT(0)
309 #define ALTR_S10_ECC_INTTEST_OFST 0x24
310 #define ALTR_S10_ECC_TSERRA BIT(0)
315 #define ALTR_S10_DERR_ADDRA_OFST 0x2C
318 #define S10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
319 #define S10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0
322 #define S10_SYSMGR_UE_VAL_OFST 0x220
323 #define S10_SYSMGR_UE_ADDR_OFST 0x224
326 #define S10_DBE_IRQ_MASK 0x3FFFE
329 #define ECC_BLK_ADDRESS_OFST 0x40
330 #define ECC_BLK_RDATA0_OFST 0x44
331 #define ECC_BLK_RDATA1_OFST 0x48
332 #define ECC_BLK_RDATA2_OFST 0x4C
333 #define ECC_BLK_RDATA3_OFST 0x50
334 #define ECC_BLK_WDATA0_OFST 0x54
335 #define ECC_BLK_WDATA1_OFST 0x58
336 #define ECC_BLK_WDATA2_OFST 0x5C
337 #define ECC_BLK_WDATA3_OFST 0x60
338 #define ECC_BLK_RECC0_OFST 0x64
339 #define ECC_BLK_RECC1_OFST 0x68
340 #define ECC_BLK_WECC0_OFST 0x6C
341 #define ECC_BLK_WECC1_OFST 0x70
342 #define ECC_BLK_DBYTECTRL_OFST 0x74
343 #define ECC_BLK_ACCCTRL_OFST 0x78
344 #define ECC_BLK_STARTACC_OFST 0x7C
346 #define ECC_XACT_KICK 0x10000
347 #define ECC_WORD_WRITE 0xFF
348 #define ECC_WRITE_DOVR 0x101
349 #define ECC_WRITE_EDOVR 0x103
350 #define ECC_READ_EOVR 0x2
351 #define ECC_READ_EDOVR 0x3