Home
last modified time | relevance | path

Searched +full:0 +full:x1a8 (Results 1 – 25 of 229) sorted by relevance

12345678910

/openbmc/linux/drivers/clk/st/
H A Dclkgen-pll.c26 #define C32_NDIV_MASK (0xff)
27 #define C32_IDF_MASK (0x7)
28 #define C32_ODF_MASK (0x3f)
29 #define C32_LDF_MASK (0x7f)
30 #define C32_CP_MASK (0x1f)
37 #define C28_NDIV_MASK (0xff)
38 #define C28_IDF_MASK (0x7)
39 #define C28_ODF_MASK (0x3f)
77 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
78 .pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8),
[all …]
/openbmc/linux/drivers/media/platform/chips-media/
H A Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcs-ufs-v6.h10 #define QPHY_V6_PCS_UFS_PHY_START 0x000
11 #define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V6_PCS_UFS_SW_RESET 0x008
13 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
14 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
15 #define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c
16 #define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
17 #define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
18 #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
19 #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
[all …]
H A Dphy-qcom-qmp-pcs-v2.h10 #define QPHY_V2_PCS_SW_RESET 0x000
11 #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V2_PCS_START_CONTROL 0x008
13 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
14 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
15 #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
16 #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
17 #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
18 #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064
19 #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v6.h9 #define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
10 #define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c
11 #define QSERDES_V6_TX_TX_DRV_LVL 0x14
12 #define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
13 #define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
14 #define QSERDES_V6_TX_TX_BAND 0x24
15 #define QSERDES_V6_TX_INTERFACE_SELECT 0x2c
16 #define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34
17 #define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
18 #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
[all …]
H A Dphy-qcom-qmp-qserdes-com-v6.h11 #define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x00
12 #define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x04
13 #define QSERDES_V6_COM_CP_CTRL_MODE1 0x10
14 #define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x14
15 #define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x18
16 #define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c
17 #define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x20
18 #define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x24
19 #define QSERDES_V6_COM_DEC_START_MODE1 0x28
20 #define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
[all …]
H A Dphy-qcom-qmp-qserdes-com-v5.h10 #define QSERDES_V5_COM_ATB_SEL1 0x000
11 #define QSERDES_V5_COM_ATB_SEL2 0x004
12 #define QSERDES_V5_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V5_COM_BG_TIMER 0x00c
14 #define QSERDES_V5_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V5_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V5_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V5_COM_SSC_PER1 0x01c
18 #define QSERDES_V5_COM_SSC_PER2 0x020
19 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-com-v4.h10 #define QSERDES_V4_COM_ATB_SEL1 0x000
11 #define QSERDES_V4_COM_ATB_SEL2 0x004
12 #define QSERDES_V4_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V4_COM_BG_TIMER 0x00c
14 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V4_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V4_COM_SSC_PER1 0x01c
18 #define QSERDES_V4_COM_SSC_PER2 0x020
19 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Daspeed,ast2xxx-scu-ic.txt15 ranges = <0 0x1e6e2000 0x1a8>;
/openbmc/linux/drivers/tty/serial/8250/
H A D8250_fourport.c16 SERIAL8250_FOURPORT(0x1a0, 9),
17 SERIAL8250_FOURPORT(0x1a8, 9),
18 SERIAL8250_FOURPORT(0x1b0, 9),
19 SERIAL8250_FOURPORT(0x1b8, 9),
20 SERIAL8250_FOURPORT(0x2a0, 5),
21 SERIAL8250_FOURPORT(0x2a8, 5),
22 SERIAL8250_FOURPORT(0x2b0, 5),
23 SERIAL8250_FOURPORT(0x2b8, 5),
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
H A Dg84.c34 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) in g84_temp_get()
35 return nvkm_rd32(device, 0x20400); in g84_temp_get()
46 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) { in g84_sensor_setup()
47 nvkm_mask(device, 0x20008, 0x80008000, 0x80000000); in g84_sensor_setup()
48 nvkm_mask(device, 0x2000c, 0x80000003, 0x00000000); in g84_sensor_setup()
63 /* enable RISING and FALLING IRQs for shutdown, THRS 0, 1, 2 and 4 */ in g84_therm_program_alarms()
64 nvkm_wr32(device, 0x20000, 0x000003ff); in g84_therm_program_alarms()
67 nvkm_wr32(device, 0x20484, sensor->thrs_shutdown.hysteresis); in g84_therm_program_alarms()
68 nvkm_wr32(device, 0x20480, sensor->thrs_shutdown.temp); in g84_therm_program_alarms()
71 nvkm_wr32(device, 0x204c4, sensor->thrs_fan_boost.temp); in g84_therm_program_alarms()
[all …]
/openbmc/linux/arch/m68k/ifpsp060/
H A Dfplsp.doc87 fmovm.x &0x01,-(%sp) # pass operand on stack
88 bsr.l _060FPLSP_TOP+0x1a8 # branch to fsin routine
89 add.l &0xc,%sp # clear operand from stack
100 bsr.l _060FPLSP_TOP+0x168 # branch to frem routine
101 addq.l &0x8,%sp # clear operands from stack
132 0x000: _060LSP__facoss_
133 0x008: _060LSP__facosd_
134 0x010: _060LSP__facosx_
135 0x018: _060LSP__fasins_
136 0x020: _060LSP__fasind_
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/openbmc/linux/drivers/usb/host/
H A Dehci-fsl.h9 #define FSL_SOC_USB_SBUSCFG 0x90
10 #define SBUSCFG_INCR8 0x02 /* INCR8, specified */
11 #define FSL_SOC_USB_ULPIVP 0x170
12 #define FSL_SOC_USB_PORTSC1 0x184
14 #define PORT_PTS_UTMI (0<<30)
18 #define FSL_SOC_USB_PORTSC2 0x188
19 #define FSL_SOC_USB_USBMODE 0x1a8
20 #define USBMODE_CM_MASK (3 << 0) /* controller mode mask */
21 #define USBMODE_CM_HOST (3 << 0) /* controller mode: host */
24 #define FSL_SOC_USB_USBGENCTRL 0x200
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpucfg.h17 u32 rst; /* base + 0x0 */
18 u32 ctrl; /* base + 0x4 */
19 u32 status; /* base + 0x8 */
20 u8 res[0x34]; /* base + 0xc */
24 u8 res0[0x40]; /* 0x000 */
25 struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */
26 u8 res1[0x44]; /* 0x140 */
27 u32 gen_ctrl; /* 0x184 */
28 u32 l2_status; /* 0x188 */
29 u8 res2[0x4]; /* 0x18c */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Daspeed-p2a-ctrl.txt40 reg = <0x1e6e2000 0x1a8>;
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dpins-imx8mq.h24 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
25 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
26 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
27 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
28 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
29 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
30 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
31 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
32 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
33 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/openbmc/linux/drivers/usb/fotg210/
H A Dfotg210-udc.h14 /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
15 #define FOTG210_GMIR 0xC4
16 #define GMIR_INT_POLARITY 0x8 /*Active High*/
17 #define GMIR_MHC_INT 0x4
18 #define GMIR_MOTG_INT 0x2
19 #define GMIR_MDEV_INT 0x1
21 /* Device Main Control Register(0x100) */
22 #define FOTG210_DMCR 0x100
29 #define DMCR_CAP_RMWAKUP (1 << 0)
31 /* Device Address Register(0x104) */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Daspeed,ast2x00-scu.yaml45 '^p2a-control@[0-9a-f]+$':
49 '^pinctrl(@[0-9a-f]+)?$':
55 '^interrupt-controller@[0-9a-f]+$':
59 '^silicon-id@[0-9a-f]+$':
97 reg = <0x1e6e2000 0x1a8>;
103 ranges = <0x0 0x1e6e2000 0x1000>;
107 reg = <0x7c 0x4>, <0x150 0x8>;
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8186-mm.c14 .set_ofs = 0x104,
15 .clr_ofs = 0x108,
16 .sta_ofs = 0x100,
20 .set_ofs = 0x1a4,
21 .clr_ofs = 0x1a8,
22 .sta_ofs = 0x1a0,
33 GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "top_disp", 0),
57 GATE_MM1(CLK_MM_DSI0_DSI_CK_DOMAIN, "mm_dsi0_dsi_domain", "top_disp", 0),
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Daspeed,ast2400-pinctrl.yaml202 reg = <0x1e6e2000 0x1a8>;
208 ranges = <0x0 0x1e6e2000 0x1000>;
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]

12345678910