13e45ed3cSNishad Kamdar /* SPDX-License-Identifier: GPL-2.0+ */ 258c559e6SRamneek Mehresh /* Copyright (C) 2005-2010,2012 Freescale Semiconductor, Inc. 380cb9aeeSRandy Vinson * Copyright (c) 2005 MontaVista Software 480cb9aeeSRandy Vinson */ 580cb9aeeSRandy Vinson #ifndef _EHCI_FSL_H 680cb9aeeSRandy Vinson #define _EHCI_FSL_H 780cb9aeeSRandy Vinson 880cb9aeeSRandy Vinson /* offsets for the non-ehci registers in the FSL SOC USB controller */ 9761bbcb7SAnatolij Gustschin #define FSL_SOC_USB_SBUSCFG 0x90 10761bbcb7SAnatolij Gustschin #define SBUSCFG_INCR8 0x02 /* INCR8, specified */ 1180cb9aeeSRandy Vinson #define FSL_SOC_USB_ULPIVP 0x170 1280cb9aeeSRandy Vinson #define FSL_SOC_USB_PORTSC1 0x184 1380cb9aeeSRandy Vinson #define PORT_PTS_MSK (3<<30) 1480cb9aeeSRandy Vinson #define PORT_PTS_UTMI (0<<30) 1580cb9aeeSRandy Vinson #define PORT_PTS_ULPI (2<<30) 1680cb9aeeSRandy Vinson #define PORT_PTS_SERIAL (3<<30) 1780cb9aeeSRandy Vinson #define PORT_PTS_PTW (1<<28) 1880cb9aeeSRandy Vinson #define FSL_SOC_USB_PORTSC2 0x188 1913b7ee2aSAnatolij Gustschin #define FSL_SOC_USB_USBMODE 0x1a8 2013b7ee2aSAnatolij Gustschin #define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ 2113b7ee2aSAnatolij Gustschin #define USBMODE_CM_HOST (3 << 0) /* controller mode: host */ 2213b7ee2aSAnatolij Gustschin #define USBMODE_ES (1 << 2) /* (Big) Endian Select */ 23230f7edeSAnatolij Gustschin 24230f7edeSAnatolij Gustschin #define FSL_SOC_USB_USBGENCTRL 0x200 25230f7edeSAnatolij Gustschin #define USBGENCTRL_PPP (1 << 3) 26230f7edeSAnatolij Gustschin #define USBGENCTRL_PFP (1 << 2) 27230f7edeSAnatolij Gustschin #define FSL_SOC_USB_ISIPHYCTRL 0x204 28230f7edeSAnatolij Gustschin #define ISIPHYCTRL_PXE (1) 29230f7edeSAnatolij Gustschin #define ISIPHYCTRL_PHYE (1 << 4) 30230f7edeSAnatolij Gustschin 3180cb9aeeSRandy Vinson #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ 3280cb9aeeSRandy Vinson #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ 3380cb9aeeSRandy Vinson #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ 347378c57aSChristian Engelmayer #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ 357378c57aSChristian Engelmayer #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ 3680cb9aeeSRandy Vinson #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ 3728c56ea1SShengzhou Liu #define CTRL_UTMI_PHY_EN (1<<9) 38529febeeSShengzhou Liu #define CTRL_PHY_CLK_VALID (1 << 17) 3940acc095SLi Yang #define SNOOP_SIZE_2GB 0x1e 4058c559e6SRamneek Mehresh 4158c559e6SRamneek Mehresh /* control Register Bit Masks */ 424e02bea8SNikhil Badola #define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */ 4358c559e6SRamneek Mehresh #define ULPI_INT_EN (1<<0) 4458c559e6SRamneek Mehresh #define WU_INT_EN (1<<1) 4558c559e6SRamneek Mehresh #define USB_CTRL_USB_EN (1<<2) 4658c559e6SRamneek Mehresh #define LINE_STATE_FILTER__EN (1<<3) 4758c559e6SRamneek Mehresh #define KEEP_OTG_ON (1<<4) 4858c559e6SRamneek Mehresh #define OTG_PORT (1<<5) 4958c559e6SRamneek Mehresh #define PLL_RESET (1<<8) 5058c559e6SRamneek Mehresh #define UTMI_PHY_EN (1<<9) 5158c559e6SRamneek Mehresh #define ULPI_PHY_CLK_SEL (1<<10) 523735ba8dSShengzhou Liu #define PHY_CLK_VALID (1<<17) 535dfff995SSuresh Gupta 545dfff995SSuresh Gupta /* Retry count for checking UTMI PHY CLK validity */ 555dfff995SSuresh Gupta #define UTMI_PHY_CLK_VALID_CHK_RETRY 5 5680cb9aeeSRandy Vinson #endif /* _EHCI_FSL_H */ 57