Home
last modified time | relevance | path

Searched +full:0 +full:x1a20 (Results 1 – 25 of 32) sorted by relevance

12

/openbmc/linux/drivers/video/backlight/
H A Dlms283gf05.c33 { 0x07, 0x0000, 0 },
34 { 0x13, 0x0000, 10 },
36 { 0x11, 0x3004, 0 },
37 { 0x14, 0x200F, 0 },
38 { 0x10, 0x1a20, 0 },
39 { 0x13, 0x0040, 50 },
41 { 0x13, 0x0060, 0 },
42 { 0x13, 0x0070, 200 },
44 { 0x01, 0x0127, 0 },
45 { 0x02, 0x0700, 0 },
[all …]
/openbmc/u-boot/board/zipitz2/
H A Dzipitz2.c37 gd->bd->bi_boot_params = 0xa0000100; in board_init()
42 return 0; in board_init()
49 return 0; in dram_init()
59 return 0; in board_usb_init()
64 return 0; in board_usb_cleanup()
74 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; in dram_init_banksize()
75 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; in dram_init_banksize()
77 return 0; in dram_init_banksize()
83 pxa_mmc_register(0); in board_mmc_init()
84 return 0; in board_mmc_init()
[all …]
/openbmc/qemu/hw/display/
H A Dati_dbg.c11 {"MM_INDEX", 0x0000},
12 {"MM_DATA", 0x0004},
13 {"CLOCK_CNTL_INDEX", 0x0008},
14 {"CLOCK_CNTL_DATA", 0x000c},
15 {"BIOS_0_SCRATCH", 0x0010},
16 {"BUS_CNTL", 0x0030},
17 {"BUS_CNTL1", 0x0034},
18 {"GEN_INT_CNTL", 0x0040},
19 {"GEN_INT_STATUS", 0x0044},
20 {"CRTC_GEN_CNTL", 0x0050},
[all …]
H A Dati_regs.h17 * 0x0000-0x00ff Misc regs also accessible via io and mmio space
18 * 0x0100-0x0eff Misc regs only accessible via mmio
19 * 0x0f00-0x0fff Read-only copy of PCI config regs
20 * 0x1000-0x13ff Concurrent Command Engine (CCE) regs
21 * 0x1400-0x1fff GUI (drawing engine) regs
29 #define MM_INDEX 0x0000
30 #define MM_DATA 0x0004
31 #define CLOCK_CNTL_INDEX 0x0008
32 #define CLOCK_CNTL_DATA 0x000c
33 #define BIOS_0_SCRATCH 0x0010
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dboard_env_spec.h12 #define MV_6710_DEV_ID 0x6710
14 #define MV_6710_Z1_REV 0x0
19 #define MV_78130_DEV_ID 0x7813
20 #define MV_78160_DEV_ID 0x7816
21 #define MV_78230_DEV_ID 0x7823
22 #define MV_78260_DEV_ID 0x7826
23 #define MV_78460_DEV_ID 0x7846
24 #define MV_78000_DEV_ID 0x7888
26 #define MV_FPGA_DEV_ID 0x2107
28 #define MV_78XX0_Z1_REV 0x0
[all …]
/openbmc/linux/include/video/
H A Daty128.h13 #define CLOCK_CNTL_INDEX 0x0008
14 #define CLOCK_CNTL_DATA 0x000c
15 #define BIOS_0_SCRATCH 0x0010
16 #define BUS_CNTL 0x0030
17 #define BUS_CNTL1 0x0034
18 #define GEN_INT_CNTL 0x0040
19 #define CRTC_GEN_CNTL 0x0050
20 #define CRTC_EXT_CNTL 0x0054
21 #define DAC_CNTL 0x0058
22 #define I2C_CNTL_1 0x0094
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dsamsung,pinctrl.yaml78 "^[a-z]+[0-9]*-gpio-bank$":
143 reg = <0x7f008000 0x1000>;
149 interrupts-extended = <&vic0 0>,
151 <&vic1 0>,
166 samsung,pins = "gpa-0", "gpa-1";
168 samsung,pin-pud = <0>;
179 reg = <0x11400000 0x1000>;
183 pinctrl-0 = <&sleep0>;
196 samsung,pins = "gpa0-0", "gpa0-1";
198 samsung,pin-pud = <0>;
[all …]
/openbmc/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-reg.h13 #define HOST_REGISTER1 0x0000
14 #define HOST_REGISTER2 0x0001
17 #define CHIP_CTRL 0x0100
18 #define AFE_AB_CTRL 0x0104
19 #define AFE_CD_CTRL 0x0108
20 #define AFE_EF_CTRL 0x010C
21 #define AFE_GH_CTRL 0x0110
22 #define DENC_AB_CTRL 0x0114
23 #define BYP_AB_CTRL 0x0118
24 #define MON_A_CTRL 0x011C
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c.h11 u8 res0[0x30]; /* 0x120 */
12 u8 vid[2]; /* 0x150 */
15 u8 mac_addr[ETH_ALEN]; /* 0x157 */
16 u8 res2[0x3d];
20 u8 res0[0x4a]; /* 0x120 */
21 u8 mac_addr[ETH_ALEN]; /* 0x16a */
25 u8 mac_addr[ETH_ALEN]; /* 0x120 */
33 u8 ltr_cap; /* 0x133 */
38 u8 res0:2; /* 0x144 */
62 u8 res0[0x0e];
[all …]
H A Dphy.c107 PHY_BAND_2G = 0,
116 for (i = 0; i <= RTW_CHANNEL_WIDTH_40; i++) { in rtw_phy_cck_pd_init()
117 for (j = 0; j < RTW_RF_PATH_MAX; j++) in rtw_phy_cck_pd_init()
194 path_div->path_a_cnt = 0; in rtw_phy_tx_path_div_init()
195 path_div->path_a_sum = 0; in rtw_phy_tx_path_div_init()
196 path_div->path_b_cnt = 0; in rtw_phy_tx_path_div_init()
197 path_div->path_b_sum = 0; in rtw_phy_tx_path_div_init()
206 dm_info->fa_history[3] = 0; in rtw_phy_init()
207 dm_info->fa_history[2] = 0; in rtw_phy_init()
208 dm_info->fa_history[1] = 0; in rtw_phy_init()
[all …]
/openbmc/linux/drivers/gpu/drm/loongson/
H A Dlsdc_regs.h24 #define LS7A1000_PIXPLL0_REG 0x04B0
25 #define LS7A1000_PIXPLL1_REG 0x04C0
28 #define LS7A1000_PLL_GFX_REG 0x0490
30 #define LS7A1000_CONF_REG_BASE 0x10010000
34 #define LS7A2000_PIXPLL0_REG 0x04B0
35 #define LS7A2000_PIXPLL1_REG 0x04C0
38 #define LS7A2000_PLL_GFX_REG 0x0490
40 #define LS7A2000_CONF_REG_BASE 0x10010000
43 #define CFG_PIX_FMT_MASK GENMASK(2, 0)
46 LSDC_PF_NONE = 0,
[all …]
/openbmc/qemu/include/hw/pci-host/
H A Dpnv_phb4_regs.h32 * stacks, thus for PEC2, the global registers are at offset 0, the
33 * PHB3 registers at offset 0x40, the PHB4 at offset 0x80 etc....
36 * it is 0 based, ie PHB3 is at 0x100 PHB4 is a 0x140 etc..
38 #define PEC_STACK_OFFSET 0x40
41 #define PEC_NEST_PBCQ_HW_CONFIG 0x00
42 #define PEC_NEST_DROP_PRIO_CTRL 0x01
43 #define PEC_NEST_PBCQ_ERR_INJECT 0x02
44 #define PEC_NEST_PCI_NEST_CLK_TRACE_CTL 0x03
45 #define PEC_NEST_PBCQ_PMON_CTRL 0x04
46 #define PEC_NEST_PBCQ_PBUS_ADDR_EXT 0x05
[all …]
/openbmc/linux/drivers/net/usb/
H A Daqc111.c33 if (unlikely(ret < 0)) in aqc111_read_cmd_nopm()
35 "Failed to read(0x%x) reg index 0x%04x: %d\n", in aqc111_read_cmd_nopm()
49 if (unlikely(ret < 0)) in aqc111_read_cmd()
51 "Failed to read(0x%x) reg index 0x%04x: %d\n", in aqc111_read_cmd()
60 int ret = 0; in aqc111_read16_cmd_nopm()
71 int ret = 0; in aqc111_read16_cmd()
95 err = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), in __aqc111_write_cmd()
100 if (unlikely(err < 0)) in __aqc111_write_cmd()
102 "Failed to write(0x%x) reg index 0x%04x: %d\n", in __aqc111_write_cmd()
126 if (usb_autopm_get_interface(dev->intf) < 0) in aqc111_write_cmd()
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A Dhal_com_phycfg.c17 u8 value = 0; in PHY_GetTxPowerByRateBase()
20 return 0; in PHY_GetTxPowerByRateBase()
24 value = pHalData->TxPwrByRateBase2_4G[RfPath][0]; in PHY_GetTxPowerByRateBase()
50 pHalData->TxPwrByRateBase2_4G[RfPath][0] = Value; in phy_SetTxPowerByRateBase()
88 u8 index = 0; in PHY_GetRateSectionIndexOfTxPowerByRate()
90 if (pDM_Odm->PhyRegPgVersion == 0) { in PHY_GetRateSectionIndexOfTxPowerByRate()
93 index = 0; in PHY_GetRateSectionIndexOfTxPowerByRate()
104 else if (BitMask == 0x000000ff) in PHY_GetRateSectionIndexOfTxPowerByRate()
148 u8 i = 0; in PHY_GetRateValuesOfTxPowerByRate()
153 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_6M); in PHY_GetRateValuesOfTxPowerByRate()
[all …]
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_registers.h16 #define VPP2_DUMMY_DATA 0x1900
17 #define VPP2_LINE_IN_LENGTH 0x1901
18 #define VPP2_PIC_IN_HEIGHT 0x1902
19 #define VPP2_SCALE_COEF_IDX 0x1903
20 #define VPP2_SCALE_COEF 0x1904
21 #define VPP2_VSC_REGION12_STARTP 0x1905
22 #define VPP2_VSC_REGION34_STARTP 0x1906
23 #define VPP2_VSC_REGION4_ENDP 0x1907
24 #define VPP2_VSC_START_PHASE_STEP 0x1908
25 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
[all …]
/openbmc/linux/include/linux/mfd/mt6357/
H A Dregisters.h10 #define MT6357_TOP0_ID 0x0
11 #define MT6357_TOP0_REV0 0x2
12 #define MT6357_TOP0_DSN_DBI 0x4
13 #define MT6357_TOP0_DSN_DXI 0x6
14 #define MT6357_HWCID 0x8
15 #define MT6357_SWCID 0xa
16 #define MT6357_PONSTS 0xc
17 #define MT6357_POFFSTS 0xe
18 #define MT6357_PSTSCTL 0x10
19 #define MT6357_PG_DEB_STS0 0x12
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_reg.h12 #define RVU_AF_MSIXTR_BASE (0x10)
13 #define RVU_AF_ECO (0x20)
14 #define RVU_AF_BLK_RST (0x30)
15 #define RVU_AF_PF_BAR4_ADDR (0x40)
16 #define RVU_AF_RAS (0x100)
17 #define RVU_AF_RAS_W1S (0x108)
18 #define RVU_AF_RAS_ENA_W1S (0x110)
19 #define RVU_AF_RAS_ENA_W1C (0x118)
20 #define RVU_AF_GEN_INT (0x120)
21 #define RVU_AF_GEN_INT_W1S (0x128)
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7757.c30 DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */
31 DEFINE_RES_IRQ(evt2irq(0x700)),
36 .id = 0,
50 DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */
51 DEFINE_RES_IRQ(evt2irq(0xb80)),
70 DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */
71 DEFINE_RES_IRQ(evt2irq(0xf00)),
89 DEFINE_RES_MEM(0xfe430000, 0x20),
90 DEFINE_RES_IRQ(evt2irq(0x580)),
91 DEFINE_RES_IRQ(evt2irq(0x5a0)),
[all …]
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_registers.h18 #define VPP2_DUMMY_DATA 0x1900
19 #define VPP2_LINE_IN_LENGTH 0x1901
20 #define VPP2_PIC_IN_HEIGHT 0x1902
21 #define VPP2_SCALE_COEF_IDX 0x1903
22 #define VPP2_SCALE_COEF 0x1904
23 #define VPP2_VSC_REGION12_STARTP 0x1905
24 #define VPP2_VSC_REGION34_STARTP 0x1906
25 #define VPP2_VSC_REGION4_ENDP 0x1907
26 #define VPP2_VSC_START_PHASE_STEP 0x1908
27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]
H A Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
H A Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433.dtsi48 #clock-cells = <0>;
53 #size-cells = <0>;
91 reg = <0x100>;
96 i-cache-size = <0x8000>;
99 d-cache-size = <0x8000>;
109 reg = <0x101>;
112 i-cache-size = <0x8000>;
115 d-cache-size = <0x8000>;
125 reg = <0x102>;
128 i-cache-size = <0x8000>;
[all …]
/openbmc/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/openbmc/linux/sound/soc/mediatek/mt8188/
H A Dmt8188-reg.h14 #define AUDIO_TOP_CON0 (0x0000)
15 #define AUDIO_TOP_CON1 (0x0004)
16 #define AUDIO_TOP_CON2 (0x0008)
17 #define AUDIO_TOP_CON3 (0x000c)
18 #define AUDIO_TOP_CON4 (0x0010)
19 #define AUDIO_TOP_CON5 (0x0014)
20 #define AUDIO_TOP_CON6 (0x0018)
21 #define AFE_MAS_HADDR_MSB (0x0020)
22 #define AFE_MEMIF_ONE_HEART (0x0024)
23 #define AFE_MUX_SEL_CFG (0x0044)
[all …]

12