126b3f3ccSNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2c7cd6c5aSSunil Goutham /* Marvell RVU Admin Function driver 354d55781SSunil Goutham * 4c7cd6c5aSSunil Goutham * Copyright (C) 2018 Marvell. 554d55781SSunil Goutham * 654d55781SSunil Goutham */ 754d55781SSunil Goutham 854d55781SSunil Goutham #ifndef RVU_REG_H 954d55781SSunil Goutham #define RVU_REG_H 1054d55781SSunil Goutham 1154d55781SSunil Goutham /* Admin function registers */ 1254d55781SSunil Goutham #define RVU_AF_MSIXTR_BASE (0x10) 1354d55781SSunil Goutham #define RVU_AF_ECO (0x20) 1454d55781SSunil Goutham #define RVU_AF_BLK_RST (0x30) 1554d55781SSunil Goutham #define RVU_AF_PF_BAR4_ADDR (0x40) 1654d55781SSunil Goutham #define RVU_AF_RAS (0x100) 1754d55781SSunil Goutham #define RVU_AF_RAS_W1S (0x108) 1854d55781SSunil Goutham #define RVU_AF_RAS_ENA_W1S (0x110) 1954d55781SSunil Goutham #define RVU_AF_RAS_ENA_W1C (0x118) 2054d55781SSunil Goutham #define RVU_AF_GEN_INT (0x120) 2154d55781SSunil Goutham #define RVU_AF_GEN_INT_W1S (0x128) 2254d55781SSunil Goutham #define RVU_AF_GEN_INT_ENA_W1S (0x130) 2354d55781SSunil Goutham #define RVU_AF_GEN_INT_ENA_W1C (0x138) 2454d55781SSunil Goutham #define RVU_AF_AFPF_MBOX0 (0x02000) 2554d55781SSunil Goutham #define RVU_AF_AFPF_MBOX1 (0x02008) 2654d55781SSunil Goutham #define RVU_AF_AFPFX_MBOXX(a, b) (0x2000 | (a) << 4 | (b) << 3) 2754d55781SSunil Goutham #define RVU_AF_PFME_STATUS (0x2800) 2854d55781SSunil Goutham #define RVU_AF_PFTRPEND (0x2810) 2954d55781SSunil Goutham #define RVU_AF_PFTRPEND_W1S (0x2820) 3054d55781SSunil Goutham #define RVU_AF_PF_RST (0x2840) 3154d55781SSunil Goutham #define RVU_AF_HWVF_RST (0x2850) 3254d55781SSunil Goutham #define RVU_AF_PFAF_MBOX_INT (0x2880) 3354d55781SSunil Goutham #define RVU_AF_PFAF_MBOX_INT_W1S (0x2888) 3454d55781SSunil Goutham #define RVU_AF_PFAF_MBOX_INT_ENA_W1S (0x2890) 3554d55781SSunil Goutham #define RVU_AF_PFAF_MBOX_INT_ENA_W1C (0x2898) 3654d55781SSunil Goutham #define RVU_AF_PFFLR_INT (0x28a0) 3754d55781SSunil Goutham #define RVU_AF_PFFLR_INT_W1S (0x28a8) 3854d55781SSunil Goutham #define RVU_AF_PFFLR_INT_ENA_W1S (0x28b0) 3954d55781SSunil Goutham #define RVU_AF_PFFLR_INT_ENA_W1C (0x28b8) 4054d55781SSunil Goutham #define RVU_AF_PFME_INT (0x28c0) 4154d55781SSunil Goutham #define RVU_AF_PFME_INT_W1S (0x28c8) 4254d55781SSunil Goutham #define RVU_AF_PFME_INT_ENA_W1S (0x28d0) 4354d55781SSunil Goutham #define RVU_AF_PFME_INT_ENA_W1C (0x28d8) 4498c56111SSubbaraya Sundeep #define RVU_AF_PFX_BAR4_ADDR(a) (0x5000 | (a) << 4) 4598c56111SSubbaraya Sundeep #define RVU_AF_PFX_BAR4_CFG (0x5200 | (a) << 4) 4698c56111SSubbaraya Sundeep #define RVU_AF_PFX_VF_BAR4_ADDR (0x5400 | (a) << 4) 4798c56111SSubbaraya Sundeep #define RVU_AF_PFX_VF_BAR4_CFG (0x5600 | (a) << 4) 4898c56111SSubbaraya Sundeep #define RVU_AF_PFX_LMTLINE_ADDR (0x5800 | (a) << 4) 49893ae972SGeetha sowjanya #define RVU_AF_SMMU_ADDR_REQ (0x6000) 50893ae972SGeetha sowjanya #define RVU_AF_SMMU_TXN_REQ (0x6008) 51893ae972SGeetha sowjanya #define RVU_AF_SMMU_ADDR_RSP_STS (0x6010) 52893ae972SGeetha sowjanya #define RVU_AF_SMMU_ADDR_TLN (0x6018) 53623da5caSGeetha sowjanya #define RVU_AF_SMMU_TLN_FLIT0 (0x6020) 5454d55781SSunil Goutham 5554d55781SSunil Goutham /* Admin function's privileged PF/VF registers */ 5654d55781SSunil Goutham #define RVU_PRIV_CONST (0x8000000) 5754d55781SSunil Goutham #define RVU_PRIV_GEN_CFG (0x8000010) 5854d55781SSunil Goutham #define RVU_PRIV_CLK_CFG (0x8000020) 5954d55781SSunil Goutham #define RVU_PRIV_ACTIVE_PC (0x8000030) 6054d55781SSunil Goutham #define RVU_PRIV_PFX_CFG(a) (0x8000100 | (a) << 16) 6154d55781SSunil Goutham #define RVU_PRIV_PFX_MSIX_CFG(a) (0x8000110 | (a) << 16) 6254d55781SSunil Goutham #define RVU_PRIV_PFX_ID_CFG(a) (0x8000120 | (a) << 16) 6354d55781SSunil Goutham #define RVU_PRIV_PFX_INT_CFG(a) (0x8000200 | (a) << 16) 649932fb72SRakesh Babu #define RVU_PRIV_PFX_NIXX_CFG(a) (0x8000300 | (a) << 3) 6554d55781SSunil Goutham #define RVU_PRIV_PFX_NPA_CFG (0x8000310) 6654d55781SSunil Goutham #define RVU_PRIV_PFX_SSO_CFG (0x8000320) 6754d55781SSunil Goutham #define RVU_PRIV_PFX_SSOW_CFG (0x8000330) 6854d55781SSunil Goutham #define RVU_PRIV_PFX_TIM_CFG (0x8000340) 699932fb72SRakesh Babu #define RVU_PRIV_PFX_CPTX_CFG(a) (0x8000350 | (a) << 3) 7054d55781SSunil Goutham #define RVU_PRIV_BLOCK_TYPEX_REV(a) (0x8000400 | (a) << 3) 7154d55781SSunil Goutham #define RVU_PRIV_HWVFX_INT_CFG(a) (0x8001280 | (a) << 16) 729932fb72SRakesh Babu #define RVU_PRIV_HWVFX_NIXX_CFG(a) (0x8001300 | (a) << 3) 7354d55781SSunil Goutham #define RVU_PRIV_HWVFX_NPA_CFG (0x8001310) 7454d55781SSunil Goutham #define RVU_PRIV_HWVFX_SSO_CFG (0x8001320) 7554d55781SSunil Goutham #define RVU_PRIV_HWVFX_SSOW_CFG (0x8001330) 7654d55781SSunil Goutham #define RVU_PRIV_HWVFX_TIM_CFG (0x8001340) 779932fb72SRakesh Babu #define RVU_PRIV_HWVFX_CPTX_CFG(a) (0x8001350 | (a) << 3) 7854d55781SSunil Goutham 7954d55781SSunil Goutham /* RVU PF registers */ 8054d55781SSunil Goutham #define RVU_PF_VFX_PFVF_MBOX0 (0x00000) 8154d55781SSunil Goutham #define RVU_PF_VFX_PFVF_MBOX1 (0x00008) 8254d55781SSunil Goutham #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3) 8354d55781SSunil Goutham #define RVU_PF_VF_BAR4_ADDR (0x10) 8454d55781SSunil Goutham #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3) 8554d55781SSunil Goutham #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3) 8654d55781SSunil Goutham #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3) 8754d55781SSunil Goutham #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3) 8854d55781SSunil Goutham #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3) 8954d55781SSunil Goutham #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3) 9054d55781SSunil Goutham #define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8C0 | (a) << 3) 9154d55781SSunil Goutham #define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8E0 | (a) << 3) 9254d55781SSunil Goutham #define RVU_PF_VFFLR_INTX(a) (0x900 | (a) << 3) 9354d55781SSunil Goutham #define RVU_PF_VFFLR_INT_W1SX(a) (0x920 | (a) << 3) 9454d55781SSunil Goutham #define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940 | (a) << 3) 9554d55781SSunil Goutham #define RVU_PF_VFFLR_INT_ENA_W1CX(a) (0x960 | (a) << 3) 9654d55781SSunil Goutham #define RVU_PF_VFME_INTX(a) (0x980 | (a) << 3) 9754d55781SSunil Goutham #define RVU_PF_VFME_INT_W1SX(a) (0x9A0 | (a) << 3) 9854d55781SSunil Goutham #define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9C0 | (a) << 3) 9954d55781SSunil Goutham #define RVU_PF_VFME_INT_ENA_W1CX(a) (0x9E0 | (a) << 3) 10054d55781SSunil Goutham #define RVU_PF_PFAF_MBOX0 (0xC00) 10154d55781SSunil Goutham #define RVU_PF_PFAF_MBOX1 (0xC08) 10254d55781SSunil Goutham #define RVU_PF_PFAF_MBOXX(a) (0xC00 | (a) << 3) 10354d55781SSunil Goutham #define RVU_PF_INT (0xc20) 10454d55781SSunil Goutham #define RVU_PF_INT_W1S (0xc28) 10554d55781SSunil Goutham #define RVU_PF_INT_ENA_W1S (0xc30) 10654d55781SSunil Goutham #define RVU_PF_INT_ENA_W1C (0xc38) 10754d55781SSunil Goutham #define RVU_PF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4) 10854d55781SSunil Goutham #define RVU_PF_MSIX_VECX_CTL(a) (0x008 | (a) << 4) 10954d55781SSunil Goutham #define RVU_PF_MSIX_PBAX(a) (0xF0000 | (a) << 3) 11098c56111SSubbaraya Sundeep #define RVU_PF_VF_MBOX_ADDR (0xC40) 11198c56111SSubbaraya Sundeep #define RVU_PF_LMTLINE_ADDR (0xC48) 11254d55781SSunil Goutham 113021e2e53SAleksey Makarov /* RVU VF registers */ 114021e2e53SAleksey Makarov #define RVU_VF_VFPF_MBOX0 (0x00000) 115021e2e53SAleksey Makarov #define RVU_VF_VFPF_MBOX1 (0x00008) 116021e2e53SAleksey Makarov 1171054a622SSunil Goutham /* NPA block's admin function registers */ 11854d55781SSunil Goutham #define NPA_AF_BLK_RST (0x0000) 1191054a622SSunil Goutham #define NPA_AF_CONST (0x0010) 1201054a622SSunil Goutham #define NPA_AF_CONST1 (0x0018) 1211054a622SSunil Goutham #define NPA_AF_LF_RST (0x0020) 1221054a622SSunil Goutham #define NPA_AF_GEN_CFG (0x0030) 1231054a622SSunil Goutham #define NPA_AF_NDC_CFG (0x0040) 1241054a622SSunil Goutham #define NPA_AF_INP_CTL (0x00D0) 1251054a622SSunil Goutham #define NPA_AF_ACTIVE_CYCLES_PC (0x00F0) 1261054a622SSunil Goutham #define NPA_AF_AVG_DELAY (0x0100) 1271054a622SSunil Goutham #define NPA_AF_GEN_INT (0x0140) 1281054a622SSunil Goutham #define NPA_AF_GEN_INT_W1S (0x0148) 1291054a622SSunil Goutham #define NPA_AF_GEN_INT_ENA_W1S (0x0150) 1301054a622SSunil Goutham #define NPA_AF_GEN_INT_ENA_W1C (0x0158) 1311054a622SSunil Goutham #define NPA_AF_RVU_INT (0x0160) 1321054a622SSunil Goutham #define NPA_AF_RVU_INT_W1S (0x0168) 1331054a622SSunil Goutham #define NPA_AF_RVU_INT_ENA_W1S (0x0170) 1341054a622SSunil Goutham #define NPA_AF_RVU_INT_ENA_W1C (0x0178) 1351054a622SSunil Goutham #define NPA_AF_ERR_INT (0x0180) 1361054a622SSunil Goutham #define NPA_AF_ERR_INT_W1S (0x0188) 1371054a622SSunil Goutham #define NPA_AF_ERR_INT_ENA_W1S (0x0190) 1381054a622SSunil Goutham #define NPA_AF_ERR_INT_ENA_W1C (0x0198) 1391054a622SSunil Goutham #define NPA_AF_RAS (0x01A0) 1401054a622SSunil Goutham #define NPA_AF_RAS_W1S (0x01A8) 1411054a622SSunil Goutham #define NPA_AF_RAS_ENA_W1S (0x01B0) 1421054a622SSunil Goutham #define NPA_AF_RAS_ENA_W1C (0x01B8) 1431054a622SSunil Goutham #define NPA_AF_BP_TEST (0x0200) 1441054a622SSunil Goutham #define NPA_AF_ECO (0x0300) 1451054a622SSunil Goutham #define NPA_AF_AQ_CFG (0x0600) 1461054a622SSunil Goutham #define NPA_AF_AQ_BASE (0x0610) 1471054a622SSunil Goutham #define NPA_AF_AQ_STATUS (0x0620) 1481054a622SSunil Goutham #define NPA_AF_AQ_DOOR (0x0630) 1491054a622SSunil Goutham #define NPA_AF_AQ_DONE_WAIT (0x0640) 1501054a622SSunil Goutham #define NPA_AF_AQ_DONE (0x0650) 1511054a622SSunil Goutham #define NPA_AF_AQ_DONE_ACK (0x0660) 1521054a622SSunil Goutham #define NPA_AF_AQ_DONE_INT (0x0680) 1531054a622SSunil Goutham #define NPA_AF_AQ_DONE_INT_W1S (0x0688) 1541054a622SSunil Goutham #define NPA_AF_AQ_DONE_ENA_W1S (0x0690) 1551054a622SSunil Goutham #define NPA_AF_AQ_DONE_ENA_W1C (0x0698) 156ae2c341eSGeetha sowjanya #define NPA_AF_BATCH_CTL (0x06a0) 1571054a622SSunil Goutham #define NPA_AF_LFX_AURAS_CFG(a) (0x4000 | (a) << 18) 1581054a622SSunil Goutham #define NPA_AF_LFX_LOC_AURAS_BASE(a) (0x4010 | (a) << 18) 1591054a622SSunil Goutham #define NPA_AF_LFX_QINTS_CFG(a) (0x4100 | (a) << 18) 1601054a622SSunil Goutham #define NPA_AF_LFX_QINTS_BASE(a) (0x4110 | (a) << 18) 1611054a622SSunil Goutham #define NPA_PRIV_AF_INT_CFG (0x10000) 1621054a622SSunil Goutham #define NPA_PRIV_LFX_CFG (0x10010) 1631054a622SSunil Goutham #define NPA_PRIV_LFX_INT_CFG (0x10020) 1641054a622SSunil Goutham #define NPA_AF_RVU_LF_CFG_DEBUG (0x10030) 1651054a622SSunil Goutham 1661054a622SSunil Goutham /* NIX block's admin function registers */ 1671054a622SSunil Goutham #define NIX_AF_CFG (0x0000) 1681054a622SSunil Goutham #define NIX_AF_STATUS (0x0010) 1691054a622SSunil Goutham #define NIX_AF_NDC_CFG (0x0018) 1701054a622SSunil Goutham #define NIX_AF_CONST (0x0020) 1711054a622SSunil Goutham #define NIX_AF_CONST1 (0x0028) 1721054a622SSunil Goutham #define NIX_AF_CONST2 (0x0030) 1731054a622SSunil Goutham #define NIX_AF_CONST3 (0x0038) 1741054a622SSunil Goutham #define NIX_AF_SQ_CONST (0x0040) 1751054a622SSunil Goutham #define NIX_AF_CQ_CONST (0x0048) 1761054a622SSunil Goutham #define NIX_AF_RQ_CONST (0x0050) 177e8e095b3SSunil Goutham #define NIX_AF_PL_CONST (0x0058) 1781054a622SSunil Goutham #define NIX_AF_PSE_CONST (0x0060) 1791054a622SSunil Goutham #define NIX_AF_TL1_CONST (0x0070) 1801054a622SSunil Goutham #define NIX_AF_TL2_CONST (0x0078) 1811054a622SSunil Goutham #define NIX_AF_TL3_CONST (0x0080) 1821054a622SSunil Goutham #define NIX_AF_TL4_CONST (0x0088) 1831054a622SSunil Goutham #define NIX_AF_MDQ_CONST (0x0090) 1841054a622SSunil Goutham #define NIX_AF_MC_MIRROR_CONST (0x0098) 1851054a622SSunil Goutham #define NIX_AF_LSO_CFG (0x00A8) 18654d55781SSunil Goutham #define NIX_AF_BLK_RST (0x00B0) 1871054a622SSunil Goutham #define NIX_AF_TX_TSTMP_CFG (0x00C0) 188e8e095b3SSunil Goutham #define NIX_AF_PL_TS (0x00C8) 1891054a622SSunil Goutham #define NIX_AF_RX_CFG (0x00D0) 1901054a622SSunil Goutham #define NIX_AF_AVG_DELAY (0x00E0) 1911054a622SSunil Goutham #define NIX_AF_CINT_DELAY (0x00F0) 192933a01adSGeetha sowjanya #define NIX_AF_VWQE_TIMER (0x00F8) 1931054a622SSunil Goutham #define NIX_AF_RX_MCAST_BASE (0x0100) 1941054a622SSunil Goutham #define NIX_AF_RX_MCAST_CFG (0x0110) 1951054a622SSunil Goutham #define NIX_AF_RX_MCAST_BUF_BASE (0x0120) 1961054a622SSunil Goutham #define NIX_AF_RX_MCAST_BUF_CFG (0x0130) 1971054a622SSunil Goutham #define NIX_AF_RX_MIRROR_BUF_BASE (0x0140) 1981054a622SSunil Goutham #define NIX_AF_RX_MIRROR_BUF_CFG (0x0148) 1991054a622SSunil Goutham #define NIX_AF_LF_RST (0x0150) 2001054a622SSunil Goutham #define NIX_AF_GEN_INT (0x0160) 2011054a622SSunil Goutham #define NIX_AF_GEN_INT_W1S (0x0168) 2021054a622SSunil Goutham #define NIX_AF_GEN_INT_ENA_W1S (0x0170) 2031054a622SSunil Goutham #define NIX_AF_GEN_INT_ENA_W1C (0x0178) 2041054a622SSunil Goutham #define NIX_AF_ERR_INT (0x0180) 2051054a622SSunil Goutham #define NIX_AF_ERR_INT_W1S (0x0188) 2061054a622SSunil Goutham #define NIX_AF_ERR_INT_ENA_W1S (0x0190) 2071054a622SSunil Goutham #define NIX_AF_ERR_INT_ENA_W1C (0x0198) 2081054a622SSunil Goutham #define NIX_AF_RAS (0x01A0) 2091054a622SSunil Goutham #define NIX_AF_RAS_W1S (0x01A8) 2101054a622SSunil Goutham #define NIX_AF_RAS_ENA_W1S (0x01B0) 2111054a622SSunil Goutham #define NIX_AF_RAS_ENA_W1C (0x01B8) 2121054a622SSunil Goutham #define NIX_AF_RVU_INT (0x01C0) 2131054a622SSunil Goutham #define NIX_AF_RVU_INT_W1S (0x01C8) 2141054a622SSunil Goutham #define NIX_AF_RVU_INT_ENA_W1S (0x01D0) 2151054a622SSunil Goutham #define NIX_AF_RVU_INT_ENA_W1C (0x01D8) 2161054a622SSunil Goutham #define NIX_AF_TCP_TIMER (0x01E0) 217c87e6b13SHarman Kalra #define NIX_AF_RX_DEF_ET(a) (0x01F0ull | (uint64_t)(a) << 3) 2181054a622SSunil Goutham #define NIX_AF_RX_DEF_OL2 (0x0200) 2191054a622SSunil Goutham #define NIX_AF_RX_DEF_OIP4 (0x0210) 2201054a622SSunil Goutham #define NIX_AF_RX_DEF_IIP4 (0x0220) 221e8e095b3SSunil Goutham #define NIX_AF_RX_DEF_VLAN0_PCP_DEI (0x0228) 2221054a622SSunil Goutham #define NIX_AF_RX_DEF_OIP6 (0x0230) 223e8e095b3SSunil Goutham #define NIX_AF_RX_DEF_VLAN1_PCP_DEI (0x0238) 2241054a622SSunil Goutham #define NIX_AF_RX_DEF_IIP6 (0x0240) 2251054a622SSunil Goutham #define NIX_AF_RX_DEF_OTCP (0x0250) 2261054a622SSunil Goutham #define NIX_AF_RX_DEF_ITCP (0x0260) 2271054a622SSunil Goutham #define NIX_AF_RX_DEF_OUDP (0x0270) 2281054a622SSunil Goutham #define NIX_AF_RX_DEF_IUDP (0x0280) 2291054a622SSunil Goutham #define NIX_AF_RX_DEF_OSCTP (0x0290) 230c87e6b13SHarman Kalra #define NIX_AF_RX_DEF_CST_APAD0 (0x0298) 2311054a622SSunil Goutham #define NIX_AF_RX_DEF_ISCTP (0x02A0) 2321054a622SSunil Goutham #define NIX_AF_RX_DEF_IPSECX (0x02B0) 233c87e6b13SHarman Kalra #define NIX_AF_RX_DEF_CST_APAD1 (0x02A8) 234e8e095b3SSunil Goutham #define NIX_AF_RX_DEF_IIP4_DSCP (0x02E0) 235e8e095b3SSunil Goutham #define NIX_AF_RX_DEF_OIP4_DSCP (0x02E8) 236e8e095b3SSunil Goutham #define NIX_AF_RX_DEF_IIP6_DSCP (0x02F0) 237e8e095b3SSunil Goutham #define NIX_AF_RX_DEF_OIP6_DSCP (0x02F8) 2381054a622SSunil Goutham #define NIX_AF_RX_IPSEC_GEN_CFG (0x0300) 2391054a622SSunil Goutham #define NIX_AF_RX_CPTX_INST_ADDR (0x0310) 2404b5a3ab1SSrujana Challa #define NIX_AF_RX_CPTX_INST_QSEL(a) (0x0320ull | (uint64_t)(a) << 3) 2414b5a3ab1SSrujana Challa #define NIX_AF_RX_CPTX_CREDIT(a) (0x0360ull | (uint64_t)(a) << 3) 2421054a622SSunil Goutham #define NIX_AF_NDC_TX_SYNC (0x03F0) 2431054a622SSunil Goutham #define NIX_AF_AQ_CFG (0x0400) 2441054a622SSunil Goutham #define NIX_AF_AQ_BASE (0x0410) 2451054a622SSunil Goutham #define NIX_AF_AQ_STATUS (0x0420) 2461054a622SSunil Goutham #define NIX_AF_AQ_DOOR (0x0430) 2471054a622SSunil Goutham #define NIX_AF_AQ_DONE_WAIT (0x0440) 2481054a622SSunil Goutham #define NIX_AF_AQ_DONE (0x0450) 2491054a622SSunil Goutham #define NIX_AF_AQ_DONE_ACK (0x0460) 2501054a622SSunil Goutham #define NIX_AF_AQ_DONE_TIMER (0x0470) 2511054a622SSunil Goutham #define NIX_AF_AQ_DONE_INT (0x0480) 2521054a622SSunil Goutham #define NIX_AF_AQ_DONE_INT_W1S (0x0488) 2531054a622SSunil Goutham #define NIX_AF_AQ_DONE_ENA_W1S (0x0490) 2541054a622SSunil Goutham #define NIX_AF_AQ_DONE_ENA_W1C (0x0498) 2551054a622SSunil Goutham #define NIX_AF_RX_LINKX_SLX_SPKT_CNT (0x0500) 2561054a622SSunil Goutham #define NIX_AF_RX_LINKX_SLX_SXQE_CNT (0x0510) 2571054a622SSunil Goutham #define NIX_AF_RX_MCAST_JOBSX_SW_CNT (0x0520) 2581054a622SSunil Goutham #define NIX_AF_RX_MIRROR_JOBSX_SW_CNT (0x0530) 2591054a622SSunil Goutham #define NIX_AF_RX_LINKX_CFG(a) (0x0540 | (a) << 16) 2601054a622SSunil Goutham #define NIX_AF_RX_SW_SYNC (0x0550) 2611054a622SSunil Goutham #define NIX_AF_RX_SW_SYNC_DONE (0x0560) 2621054a622SSunil Goutham #define NIX_AF_SEB_ECO (0x0600) 2631054a622SSunil Goutham #define NIX_AF_SEB_TEST_BP (0x0610) 2641054a622SSunil Goutham #define NIX_AF_NORM_TX_FIFO_STATUS (0x0620) 2651054a622SSunil Goutham #define NIX_AF_EXPR_TX_FIFO_STATUS (0x0630) 2661054a622SSunil Goutham #define NIX_AF_SDP_TX_FIFO_STATUS (0x0640) 2671054a622SSunil Goutham #define NIX_AF_TX_NPC_CAPTURE_CONFIG (0x0660) 2681054a622SSunil Goutham #define NIX_AF_TX_NPC_CAPTURE_INFO (0x0670) 269a7314371SGeetha sowjanya #define NIX_AF_SEB_CFG (0x05F0) 2702958d17aSHariprasad Kelam #define NIX_PTP_1STEP_EN BIT_ULL(2) 2711054a622SSunil Goutham 2721054a622SSunil Goutham #define NIX_AF_DEBUG_NPC_RESP_DATAX(a) (0x680 | (a) << 3) 2731054a622SSunil Goutham #define NIX_AF_SMQX_CFG(a) (0x700 | (a) << 16) 2745d9b976dSSunil Goutham #define NIX_AF_SQM_DBG_CTL_STATUS (0x750) 275bbba125eSSunil Goutham #define NIX_AF_DWRR_SDP_MTU (0x790) /* All CN10K except CN10KB */ 276bbba125eSSunil Goutham #define NIX_AF_DWRR_MTUX(a) (0x790 | (a) << 16) /* Only for CN10KB */ 27776660df2SSunil Goutham #define NIX_AF_DWRR_RPM_MTU (0x7A0) 2781054a622SSunil Goutham #define NIX_AF_PSE_CHANNEL_LEVEL (0x800) 2791054a622SSunil Goutham #define NIX_AF_PSE_SHAPER_CFG (0x810) 2801054a622SSunil Goutham #define NIX_AF_TX_EXPR_CREDIT (0x830) 2811054a622SSunil Goutham #define NIX_AF_MARK_FORMATX_CTL(a) (0x900 | (a) << 18) 2821054a622SSunil Goutham #define NIX_AF_TX_LINKX_NORM_CREDIT(a) (0xA00 | (a) << 16) 2831054a622SSunil Goutham #define NIX_AF_TX_LINKX_EXPR_CREDIT(a) (0xA10 | (a) << 16) 2841054a622SSunil Goutham #define NIX_AF_TX_LINKX_SW_XOFF(a) (0xA20 | (a) << 16) 2851054a622SSunil Goutham #define NIX_AF_TX_LINKX_HW_XOFF(a) (0xA30 | (a) << 16) 2861054a622SSunil Goutham #define NIX_AF_SDP_LINK_CREDIT (0xa40) 2871054a622SSunil Goutham #define NIX_AF_SDP_SW_XOFFX(a) (0xA60 | (a) << 3) 2881054a622SSunil Goutham #define NIX_AF_SDP_HW_XOFFX(a) (0xAC0 | (a) << 3) 2891054a622SSunil Goutham #define NIX_AF_TL4X_BP_STATUS(a) (0xB00 | (a) << 16) 2901054a622SSunil Goutham #define NIX_AF_TL4X_SDP_LINK_CFG(a) (0xB10 | (a) << 16) 2911054a622SSunil Goutham #define NIX_AF_TL1X_SCHEDULE(a) (0xC00 | (a) << 16) 2921054a622SSunil Goutham #define NIX_AF_TL1X_SHAPE(a) (0xC10 | (a) << 16) 2931054a622SSunil Goutham #define NIX_AF_TL1X_CIR(a) (0xC20 | (a) << 16) 2941054a622SSunil Goutham #define NIX_AF_TL1X_SHAPE_STATE(a) (0xC50 | (a) << 16) 2951054a622SSunil Goutham #define NIX_AF_TL1X_SW_XOFF(a) (0xC70 | (a) << 16) 2961054a622SSunil Goutham #define NIX_AF_TL1X_TOPOLOGY(a) (0xC80 | (a) << 16) 2971054a622SSunil Goutham #define NIX_AF_TL1X_GREEN(a) (0xC90 | (a) << 16) 2981054a622SSunil Goutham #define NIX_AF_TL1X_YELLOW(a) (0xCA0 | (a) << 16) 2991054a622SSunil Goutham #define NIX_AF_TL1X_RED(a) (0xCB0 | (a) << 16) 3001054a622SSunil Goutham #define NIX_AF_TL1X_MD_DEBUG0(a) (0xCC0 | (a) << 16) 3011054a622SSunil Goutham #define NIX_AF_TL1X_MD_DEBUG1(a) (0xCC8 | (a) << 16) 3021054a622SSunil Goutham #define NIX_AF_TL1X_MD_DEBUG2(a) (0xCD0 | (a) << 16) 3031054a622SSunil Goutham #define NIX_AF_TL1X_MD_DEBUG3(a) (0xCD8 | (a) << 16) 3041054a622SSunil Goutham #define NIX_AF_TL1A_DEBUG (0xce0) 3051054a622SSunil Goutham #define NIX_AF_TL1B_DEBUG (0xcf0) 3061054a622SSunil Goutham #define NIX_AF_TL1_DEBUG_GREEN (0xd00) 3071054a622SSunil Goutham #define NIX_AF_TL1_DEBUG_NODE (0xd10) 3081054a622SSunil Goutham #define NIX_AF_TL1X_DROPPED_PACKETS(a) (0xD20 | (a) << 16) 3091054a622SSunil Goutham #define NIX_AF_TL1X_DROPPED_BYTES(a) (0xD30 | (a) << 16) 3101054a622SSunil Goutham #define NIX_AF_TL1X_RED_PACKETS(a) (0xD40 | (a) << 16) 3111054a622SSunil Goutham #define NIX_AF_TL1X_RED_BYTES(a) (0xD50 | (a) << 16) 3121054a622SSunil Goutham #define NIX_AF_TL1X_YELLOW_PACKETS(a) (0xD60 | (a) << 16) 3131054a622SSunil Goutham #define NIX_AF_TL1X_YELLOW_BYTES(a) (0xD70 | (a) << 16) 3141054a622SSunil Goutham #define NIX_AF_TL1X_GREEN_PACKETS(a) (0xD80 | (a) << 16) 3151054a622SSunil Goutham #define NIX_AF_TL1X_GREEN_BYTES(a) (0xD90 | (a) << 16) 3161054a622SSunil Goutham #define NIX_AF_TL2X_SCHEDULE(a) (0xE00 | (a) << 16) 3171054a622SSunil Goutham #define NIX_AF_TL2X_SHAPE(a) (0xE10 | (a) << 16) 3181054a622SSunil Goutham #define NIX_AF_TL2X_CIR(a) (0xE20 | (a) << 16) 3191054a622SSunil Goutham #define NIX_AF_TL2X_PIR(a) (0xE30 | (a) << 16) 3201054a622SSunil Goutham #define NIX_AF_TL2X_SCHED_STATE(a) (0xE40 | (a) << 16) 3211054a622SSunil Goutham #define NIX_AF_TL2X_SHAPE_STATE(a) (0xE50 | (a) << 16) 3221054a622SSunil Goutham #define NIX_AF_TL2X_POINTERS(a) (0xE60 | (a) << 16) 3231054a622SSunil Goutham #define NIX_AF_TL2X_SW_XOFF(a) (0xE70 | (a) << 16) 3241054a622SSunil Goutham #define NIX_AF_TL2X_TOPOLOGY(a) (0xE80 | (a) << 16) 3251054a622SSunil Goutham #define NIX_AF_TL2X_PARENT(a) (0xE88 | (a) << 16) 3261054a622SSunil Goutham #define NIX_AF_TL2X_GREEN(a) (0xE90 | (a) << 16) 3271054a622SSunil Goutham #define NIX_AF_TL2X_YELLOW(a) (0xEA0 | (a) << 16) 3281054a622SSunil Goutham #define NIX_AF_TL2X_RED(a) (0xEB0 | (a) << 16) 3291054a622SSunil Goutham #define NIX_AF_TL2X_MD_DEBUG0(a) (0xEC0 | (a) << 16) 3301054a622SSunil Goutham #define NIX_AF_TL2X_MD_DEBUG1(a) (0xEC8 | (a) << 16) 3311054a622SSunil Goutham #define NIX_AF_TL2X_MD_DEBUG2(a) (0xED0 | (a) << 16) 3321054a622SSunil Goutham #define NIX_AF_TL2X_MD_DEBUG3(a) (0xED8 | (a) << 16) 3331054a622SSunil Goutham #define NIX_AF_TL2A_DEBUG (0xee0) 3341054a622SSunil Goutham #define NIX_AF_TL2B_DEBUG (0xef0) 3351054a622SSunil Goutham #define NIX_AF_TL3X_SCHEDULE(a) (0x1000 | (a) << 16) 3361054a622SSunil Goutham #define NIX_AF_TL3X_SHAPE(a) (0x1010 | (a) << 16) 3371054a622SSunil Goutham #define NIX_AF_TL3X_CIR(a) (0x1020 | (a) << 16) 3381054a622SSunil Goutham #define NIX_AF_TL3X_PIR(a) (0x1030 | (a) << 16) 3391054a622SSunil Goutham #define NIX_AF_TL3X_SCHED_STATE(a) (0x1040 | (a) << 16) 3401054a622SSunil Goutham #define NIX_AF_TL3X_SHAPE_STATE(a) (0x1050 | (a) << 16) 3411054a622SSunil Goutham #define NIX_AF_TL3X_POINTERS(a) (0x1060 | (a) << 16) 3421054a622SSunil Goutham #define NIX_AF_TL3X_SW_XOFF(a) (0x1070 | (a) << 16) 3431054a622SSunil Goutham #define NIX_AF_TL3X_TOPOLOGY(a) (0x1080 | (a) << 16) 3441054a622SSunil Goutham #define NIX_AF_TL3X_PARENT(a) (0x1088 | (a) << 16) 3451054a622SSunil Goutham #define NIX_AF_TL3X_GREEN(a) (0x1090 | (a) << 16) 3461054a622SSunil Goutham #define NIX_AF_TL3X_YELLOW(a) (0x10A0 | (a) << 16) 3471054a622SSunil Goutham #define NIX_AF_TL3X_RED(a) (0x10B0 | (a) << 16) 3481054a622SSunil Goutham #define NIX_AF_TL3X_MD_DEBUG0(a) (0x10C0 | (a) << 16) 3491054a622SSunil Goutham #define NIX_AF_TL3X_MD_DEBUG1(a) (0x10C8 | (a) << 16) 3501054a622SSunil Goutham #define NIX_AF_TL3X_MD_DEBUG2(a) (0x10D0 | (a) << 16) 3511054a622SSunil Goutham #define NIX_AF_TL3X_MD_DEBUG3(a) (0x10D8 | (a) << 16) 3521054a622SSunil Goutham #define NIX_AF_TL3A_DEBUG (0x10e0) 3531054a622SSunil Goutham #define NIX_AF_TL3B_DEBUG (0x10f0) 3541054a622SSunil Goutham #define NIX_AF_TL4X_SCHEDULE(a) (0x1200 | (a) << 16) 3551054a622SSunil Goutham #define NIX_AF_TL4X_SHAPE(a) (0x1210 | (a) << 16) 3561054a622SSunil Goutham #define NIX_AF_TL4X_CIR(a) (0x1220 | (a) << 16) 3571054a622SSunil Goutham #define NIX_AF_TL4X_PIR(a) (0x1230 | (a) << 16) 3581054a622SSunil Goutham #define NIX_AF_TL4X_SCHED_STATE(a) (0x1240 | (a) << 16) 3591054a622SSunil Goutham #define NIX_AF_TL4X_SHAPE_STATE(a) (0x1250 | (a) << 16) 3601054a622SSunil Goutham #define NIX_AF_TL4X_POINTERS(a) (0x1260 | (a) << 16) 3611054a622SSunil Goutham #define NIX_AF_TL4X_SW_XOFF(a) (0x1270 | (a) << 16) 3621054a622SSunil Goutham #define NIX_AF_TL4X_TOPOLOGY(a) (0x1280 | (a) << 16) 3631054a622SSunil Goutham #define NIX_AF_TL4X_PARENT(a) (0x1288 | (a) << 16) 3641054a622SSunil Goutham #define NIX_AF_TL4X_GREEN(a) (0x1290 | (a) << 16) 3651054a622SSunil Goutham #define NIX_AF_TL4X_YELLOW(a) (0x12A0 | (a) << 16) 3661054a622SSunil Goutham #define NIX_AF_TL4X_RED(a) (0x12B0 | (a) << 16) 3671054a622SSunil Goutham #define NIX_AF_TL4X_MD_DEBUG0(a) (0x12C0 | (a) << 16) 3681054a622SSunil Goutham #define NIX_AF_TL4X_MD_DEBUG1(a) (0x12C8 | (a) << 16) 3691054a622SSunil Goutham #define NIX_AF_TL4X_MD_DEBUG2(a) (0x12D0 | (a) << 16) 3701054a622SSunil Goutham #define NIX_AF_TL4X_MD_DEBUG3(a) (0x12D8 | (a) << 16) 3711054a622SSunil Goutham #define NIX_AF_TL4A_DEBUG (0x12e0) 3721054a622SSunil Goutham #define NIX_AF_TL4B_DEBUG (0x12f0) 3731054a622SSunil Goutham #define NIX_AF_MDQX_SCHEDULE(a) (0x1400 | (a) << 16) 3741054a622SSunil Goutham #define NIX_AF_MDQX_SHAPE(a) (0x1410 | (a) << 16) 3751054a622SSunil Goutham #define NIX_AF_MDQX_CIR(a) (0x1420 | (a) << 16) 3761054a622SSunil Goutham #define NIX_AF_MDQX_PIR(a) (0x1430 | (a) << 16) 3771054a622SSunil Goutham #define NIX_AF_MDQX_SCHED_STATE(a) (0x1440 | (a) << 16) 3781054a622SSunil Goutham #define NIX_AF_MDQX_SHAPE_STATE(a) (0x1450 | (a) << 16) 3791054a622SSunil Goutham #define NIX_AF_MDQX_POINTERS(a) (0x1460 | (a) << 16) 3801054a622SSunil Goutham #define NIX_AF_MDQX_SW_XOFF(a) (0x1470 | (a) << 16) 3811054a622SSunil Goutham #define NIX_AF_MDQX_PARENT(a) (0x1480 | (a) << 16) 3821054a622SSunil Goutham #define NIX_AF_MDQX_MD_DEBUG(a) (0x14C0 | (a) << 16) 3831054a622SSunil Goutham #define NIX_AF_MDQX_PTR_FIFO(a) (0x14D0 | (a) << 16) 3841054a622SSunil Goutham #define NIX_AF_MDQA_DEBUG (0x14e0) 3851054a622SSunil Goutham #define NIX_AF_MDQB_DEBUG (0x14f0) 3861054a622SSunil Goutham #define NIX_AF_TL3_TL2X_CFG(a) (0x1600 | (a) << 18) 3871054a622SSunil Goutham #define NIX_AF_TL3_TL2X_BP_STATUS(a) (0x1610 | (a) << 16) 3881054a622SSunil Goutham #define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) (0x1700 | (a) << 16 | (b) << 3) 3891054a622SSunil Goutham #define NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(a, b) (0x1800 | (a) << 18 | (b) << 3) 3901054a622SSunil Goutham #define NIX_AF_TX_MCASTX(a) (0x1900 | (a) << 15) 3911054a622SSunil Goutham #define NIX_AF_TX_VTAG_DEFX_CTL(a) (0x1A00 | (a) << 16) 3921054a622SSunil Goutham #define NIX_AF_TX_VTAG_DEFX_DATA(a) (0x1A10 | (a) << 16) 3931054a622SSunil Goutham #define NIX_AF_RX_BPIDX_STATUS(a) (0x1A20 | (a) << 17) 3941054a622SSunil Goutham #define NIX_AF_RX_CHANX_CFG(a) (0x1A30 | (a) << 15) 3951054a622SSunil Goutham #define NIX_AF_CINT_TIMERX(a) (0x1A40 | (a) << 18) 3961054a622SSunil Goutham #define NIX_AF_LSO_FORMATX_FIELDX(a, b) (0x1B00 | (a) << 16 | (b) << 3) 3971054a622SSunil Goutham #define NIX_AF_LFX_CFG(a) (0x4000 | (a) << 17) 3981054a622SSunil Goutham #define NIX_AF_LFX_SQS_CFG(a) (0x4020 | (a) << 17) 3991054a622SSunil Goutham #define NIX_AF_LFX_TX_CFG2(a) (0x4028 | (a) << 17) 4001054a622SSunil Goutham #define NIX_AF_LFX_SQS_BASE(a) (0x4030 | (a) << 17) 4011054a622SSunil Goutham #define NIX_AF_LFX_RQS_CFG(a) (0x4040 | (a) << 17) 4021054a622SSunil Goutham #define NIX_AF_LFX_RQS_BASE(a) (0x4050 | (a) << 17) 4031054a622SSunil Goutham #define NIX_AF_LFX_CQS_CFG(a) (0x4060 | (a) << 17) 4041054a622SSunil Goutham #define NIX_AF_LFX_CQS_BASE(a) (0x4070 | (a) << 17) 4051054a622SSunil Goutham #define NIX_AF_LFX_TX_CFG(a) (0x4080 | (a) << 17) 4061054a622SSunil Goutham #define NIX_AF_LFX_TX_PARSE_CFG(a) (0x4090 | (a) << 17) 4071054a622SSunil Goutham #define NIX_AF_LFX_RX_CFG(a) (0x40A0 | (a) << 17) 4081054a622SSunil Goutham #define NIX_AF_LFX_RSS_CFG(a) (0x40C0 | (a) << 17) 4091054a622SSunil Goutham #define NIX_AF_LFX_RSS_BASE(a) (0x40D0 | (a) << 17) 4101054a622SSunil Goutham #define NIX_AF_LFX_QINTS_CFG(a) (0x4100 | (a) << 17) 4111054a622SSunil Goutham #define NIX_AF_LFX_QINTS_BASE(a) (0x4110 | (a) << 17) 4121054a622SSunil Goutham #define NIX_AF_LFX_CINTS_CFG(a) (0x4120 | (a) << 17) 4131054a622SSunil Goutham #define NIX_AF_LFX_CINTS_BASE(a) (0x4130 | (a) << 17) 4141054a622SSunil Goutham #define NIX_AF_LFX_RX_IPSEC_CFG0(a) (0x4140 | (a) << 17) 4151054a622SSunil Goutham #define NIX_AF_LFX_RX_IPSEC_CFG1(a) (0x4148 | (a) << 17) 4161054a622SSunil Goutham #define NIX_AF_LFX_RX_IPSEC_DYNO_CFG(a) (0x4150 | (a) << 17) 4171054a622SSunil Goutham #define NIX_AF_LFX_RX_IPSEC_DYNO_BASE(a) (0x4158 | (a) << 17) 4181054a622SSunil Goutham #define NIX_AF_LFX_RX_IPSEC_SA_BASE(a) (0x4170 | (a) << 17) 4191054a622SSunil Goutham #define NIX_AF_LFX_TX_STATUS(a) (0x4180 | (a) << 17) 4201054a622SSunil Goutham #define NIX_AF_LFX_RX_VTAG_TYPEX(a, b) (0x4200 | (a) << 17 | (b) << 3) 4211054a622SSunil Goutham #define NIX_AF_LFX_LOCKX(a, b) (0x4300 | (a) << 17 | (b) << 3) 4221054a622SSunil Goutham #define NIX_AF_LFX_TX_STATX(a, b) (0x4400 | (a) << 17 | (b) << 3) 4231054a622SSunil Goutham #define NIX_AF_LFX_RX_STATX(a, b) (0x4500 | (a) << 17 | (b) << 3) 4241054a622SSunil Goutham #define NIX_AF_LFX_RSS_GRPX(a, b) (0x4600 | (a) << 17 | (b) << 3) 4251054a622SSunil Goutham #define NIX_AF_RX_NPC_MC_RCV (0x4700) 4261054a622SSunil Goutham #define NIX_AF_RX_NPC_MC_DROP (0x4710) 4271054a622SSunil Goutham #define NIX_AF_RX_NPC_MIRROR_RCV (0x4720) 4281054a622SSunil Goutham #define NIX_AF_RX_NPC_MIRROR_DROP (0x4730) 4291054a622SSunil Goutham #define NIX_AF_RX_ACTIVE_CYCLES_PCX(a) (0x4800 | (a) << 16) 430242da439SSubbaraya Sundeep #define NIX_AF_LINKX_CFG(a) (0x4010 | (a) << 17) 431933a01adSGeetha sowjanya #define NIX_AF_MDQX_IN_MD_COUNT(a) (0x14e0 | (a) << 16) 4321054a622SSunil Goutham 4331054a622SSunil Goutham #define NIX_PRIV_AF_INT_CFG (0x8000000) 4341054a622SSunil Goutham #define NIX_PRIV_LFX_CFG (0x8000010) 4351054a622SSunil Goutham #define NIX_PRIV_LFX_INT_CFG (0x8000020) 4361054a622SSunil Goutham #define NIX_AF_RVU_LF_CFG_DEBUG (0x8000030) 4371054a622SSunil Goutham 438242da439SSubbaraya Sundeep #define NIX_AF_LINKX_BASE_MASK GENMASK_ULL(11, 0) 439242da439SSubbaraya Sundeep #define NIX_AF_LINKX_RANGE_MASK GENMASK_ULL(19, 16) 440*00efd99eSNithin Dabilpuram #define NIX_AF_LINKX_MCS_CNT_MASK GENMASK_ULL(33, 32) 441242da439SSubbaraya Sundeep 4421054a622SSunil Goutham /* SSO */ 4431054a622SSunil Goutham #define SSO_AF_CONST (0x1000) 4441054a622SSunil Goutham #define SSO_AF_CONST1 (0x1008) 44554d55781SSunil Goutham #define SSO_AF_BLK_RST (0x10f8) 4461054a622SSunil Goutham #define SSO_AF_LF_HWGRP_RST (0x10e0) 4471054a622SSunil Goutham #define SSO_AF_RVU_LF_CFG_DEBUG (0x3800) 4481054a622SSunil Goutham #define SSO_PRIV_LFX_HWGRP_CFG (0x10000) 4491054a622SSunil Goutham #define SSO_PRIV_LFX_HWGRP_INT_CFG (0x20000) 4501054a622SSunil Goutham 4511054a622SSunil Goutham /* SSOW */ 4521054a622SSunil Goutham #define SSOW_AF_RVU_LF_HWS_CFG_DEBUG (0x0010) 4531054a622SSunil Goutham #define SSOW_AF_LF_HWS_RST (0x0030) 4541054a622SSunil Goutham #define SSOW_PRIV_LFX_HWS_CFG (0x1000) 4551054a622SSunil Goutham #define SSOW_PRIV_LFX_HWS_INT_CFG (0x2000) 4561054a622SSunil Goutham 4571054a622SSunil Goutham /* TIM */ 4581054a622SSunil Goutham #define TIM_AF_CONST (0x90) 4591054a622SSunil Goutham #define TIM_PRIV_LFX_CFG (0x20000) 4601054a622SSunil Goutham #define TIM_PRIV_LFX_INT_CFG (0x24000) 4611054a622SSunil Goutham #define TIM_AF_RVU_LF_CFG_DEBUG (0x30000) 46254d55781SSunil Goutham #define TIM_AF_BLK_RST (0x10) 4631054a622SSunil Goutham #define TIM_AF_LF_RST (0x20) 4641054a622SSunil Goutham 4651054a622SSunil Goutham /* CPT */ 4661054a622SSunil Goutham #define CPT_AF_CONSTANTS0 (0x0000) 467ae454086SSrujana Challa #define CPT_AF_CONSTANTS1 (0x1000) 468ae454086SSrujana Challa #define CPT_AF_DIAG (0x3000) 469ae454086SSrujana Challa #define CPT_AF_ECO (0x4000) 470ae454086SSrujana Challa #define CPT_AF_FLTX_INT(a) (0xa000ull | (u64)(a) << 3) 471ae454086SSrujana Challa #define CPT_AF_FLTX_INT_W1S(a) (0xb000ull | (u64)(a) << 3) 472ae454086SSrujana Challa #define CPT_AF_FLTX_INT_ENA_W1C(a) (0xc000ull | (u64)(a) << 3) 473ae454086SSrujana Challa #define CPT_AF_FLTX_INT_ENA_W1S(a) (0xd000ull | (u64)(a) << 3) 474ae454086SSrujana Challa #define CPT_AF_PSNX_EXE(a) (0xe000ull | (u64)(a) << 3) 475ae454086SSrujana Challa #define CPT_AF_PSNX_EXE_W1S(a) (0xf000ull | (u64)(a) << 3) 476ae454086SSrujana Challa #define CPT_AF_PSNX_LF(a) (0x10000ull | (u64)(a) << 3) 477ae454086SSrujana Challa #define CPT_AF_PSNX_LF_W1S(a) (0x11000ull | (u64)(a) << 3) 478ae454086SSrujana Challa #define CPT_AF_EXEX_CTL2(a) (0x12000ull | (u64)(a) << 3) 479ae454086SSrujana Challa #define CPT_AF_EXEX_STS(a) (0x13000ull | (u64)(a) << 3) 480ae454086SSrujana Challa #define CPT_AF_EXE_ERR_INFO (0x14000) 481ae454086SSrujana Challa #define CPT_AF_EXEX_ACTIVE(a) (0x16000ull | (u64)(a) << 3) 482ae454086SSrujana Challa #define CPT_AF_INST_REQ_PC (0x17000) 483ae454086SSrujana Challa #define CPT_AF_INST_LATENCY_PC (0x18000) 484ae454086SSrujana Challa #define CPT_AF_RD_REQ_PC (0x19000) 485ae454086SSrujana Challa #define CPT_AF_RD_LATENCY_PC (0x1a000) 486ae454086SSrujana Challa #define CPT_AF_RD_UC_PC (0x1b000) 487ae454086SSrujana Challa #define CPT_AF_ACTIVE_CYCLES_PC (0x1c000) 488ae454086SSrujana Challa #define CPT_AF_EXE_DBG_CTL (0x1d000) 489ae454086SSrujana Challa #define CPT_AF_EXE_DBG_DATA (0x1e000) 490ae454086SSrujana Challa #define CPT_AF_EXE_REQ_TIMER (0x1f000) 491ae454086SSrujana Challa #define CPT_AF_EXEX_CTL(a) (0x20000ull | (u64)(a) << 3) 492ae454086SSrujana Challa #define CPT_AF_EXE_PERF_CTL (0x21000) 493ae454086SSrujana Challa #define CPT_AF_EXE_DBG_CNTX(a) (0x22000ull | (u64)(a) << 3) 494ae454086SSrujana Challa #define CPT_AF_EXE_PERF_EVENT_CNT (0x23000) 495ae454086SSrujana Challa #define CPT_AF_EXE_EPCI_INBX_CNT(a) (0x24000ull | (u64)(a) << 3) 496ae454086SSrujana Challa #define CPT_AF_EXE_EPCI_OUTBX_CNT(a) (0x25000ull | (u64)(a) << 3) 497ae454086SSrujana Challa #define CPT_AF_EXEX_UCODE_BASE(a) (0x26000ull | (u64)(a) << 3) 498ae454086SSrujana Challa #define CPT_AF_LFX_CTL(a) (0x27000ull | (u64)(a) << 3) 499ae454086SSrujana Challa #define CPT_AF_LFX_CTL2(a) (0x29000ull | (u64)(a) << 3) 500ae454086SSrujana Challa #define CPT_AF_CPTCLK_CNT (0x2a000) 501ae454086SSrujana Challa #define CPT_AF_PF_FUNC (0x2b000) 502ae454086SSrujana Challa #define CPT_AF_LFX_PTR_CTL(a) (0x2c000ull | (u64)(a) << 3) 503ae454086SSrujana Challa #define CPT_AF_GRPX_THR(a) (0x2d000ull | (u64)(a) << 3) 504ae454086SSrujana Challa #define CPT_AF_CTL (0x2e000ull) 505ae454086SSrujana Challa #define CPT_AF_XEX_THR(a) (0x2f000ull | (u64)(a) << 3) 5061054a622SSunil Goutham #define CPT_PRIV_LFX_CFG (0x41000) 507ae454086SSrujana Challa #define CPT_PRIV_AF_INT_CFG (0x42000) 5081054a622SSunil Goutham #define CPT_PRIV_LFX_INT_CFG (0x43000) 5091054a622SSunil Goutham #define CPT_AF_LF_RST (0x44000) 510ae454086SSrujana Challa #define CPT_AF_RVU_LF_CFG_DEBUG (0x45000) 51154d55781SSunil Goutham #define CPT_AF_BLK_RST (0x46000) 512ae454086SSrujana Challa #define CPT_AF_RVU_INT (0x47000) 513ae454086SSrujana Challa #define CPT_AF_RVU_INT_W1S (0x47008) 514ae454086SSrujana Challa #define CPT_AF_RVU_INT_ENA_W1S (0x47010) 515ae454086SSrujana Challa #define CPT_AF_RVU_INT_ENA_W1C (0x47018) 516ae454086SSrujana Challa #define CPT_AF_RAS_INT (0x47020) 517ae454086SSrujana Challa #define CPT_AF_RAS_INT_W1S (0x47028) 518ae454086SSrujana Challa #define CPT_AF_RAS_INT_ENA_W1S (0x47030) 519ae454086SSrujana Challa #define CPT_AF_RAS_INT_ENA_W1C (0x47038) 520e4bbc5c5SSrujana Challa #define CPT_AF_CTX_FLUSH_TIMER (0x48000ull) 521e4bbc5c5SSrujana Challa #define CPT_AF_CTX_ERR (0x48008ull) 522e4bbc5c5SSrujana Challa #define CPT_AF_CTX_ENC_ID (0x48010ull) 523e4bbc5c5SSrujana Challa #define CPT_AF_CTX_MIS_PC (0x49400ull) 524e4bbc5c5SSrujana Challa #define CPT_AF_CTX_HIT_PC (0x49408ull) 525e4bbc5c5SSrujana Challa #define CPT_AF_CTX_AOP_PC (0x49410ull) 526e4bbc5c5SSrujana Challa #define CPT_AF_CTX_AOP_LATENCY_PC (0x49418ull) 527e4bbc5c5SSrujana Challa #define CPT_AF_CTX_IFETCH_PC (0x49420ull) 528e4bbc5c5SSrujana Challa #define CPT_AF_CTX_IFETCH_LATENCY_PC (0x49428ull) 529e4bbc5c5SSrujana Challa #define CPT_AF_CTX_FFETCH_PC (0x49430ull) 530e4bbc5c5SSrujana Challa #define CPT_AF_CTX_FFETCH_LATENCY_PC (0x49438ull) 531e4bbc5c5SSrujana Challa #define CPT_AF_CTX_WBACK_PC (0x49440ull) 532e4bbc5c5SSrujana Challa #define CPT_AF_CTX_WBACK_LATENCY_PC (0x49448ull) 533e4bbc5c5SSrujana Challa #define CPT_AF_CTX_PSH_PC (0x49450ull) 534e4bbc5c5SSrujana Challa #define CPT_AF_CTX_PSH_LATENCY_PC (0x49458ull) 535149f3b73SSrujana Challa #define CPT_AF_CTX_CAM_DATA(a) (0x49800ull | (u64)(a) << 3) 536e4bbc5c5SSrujana Challa #define CPT_AF_RXC_TIME (0x50010ull) 537e4bbc5c5SSrujana Challa #define CPT_AF_RXC_TIME_CFG (0x50018ull) 538e4bbc5c5SSrujana Challa #define CPT_AF_RXC_DFRG (0x50020ull) 539e4bbc5c5SSrujana Challa #define CPT_AF_RXC_ACTIVE_STS (0x50028ull) 540e4bbc5c5SSrujana Challa #define CPT_AF_RXC_ZOMBIE_STS (0x50030ull) 541e4bbc5c5SSrujana Challa #define CPT_AF_X2PX_LINK_CFG(a) (0x51000ull | (u64)(a) << 3) 542ae454086SSrujana Challa 543c57c58fdSSrujana Challa #define AF_BAR2_ALIASX(a, b) (0x9100000ull | (a) << 12 | (b)) 544c57c58fdSSrujana Challa #define CPT_AF_BAR2_SEL 0x9000000 545c57c58fdSSrujana Challa #define CPT_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) 546c57c58fdSSrujana Challa 547ae454086SSrujana Challa #define CPT_AF_LF_CTL2_SHIFT 3 548ae454086SSrujana Challa #define CPT_AF_LF_SSO_PF_FUNC_SHIFT 32 5491054a622SSunil Goutham 550c57c58fdSSrujana Challa #define CPT_LF_CTL 0x10 551c57c58fdSSrujana Challa #define CPT_LF_INPROG 0x40 5525c22fce6SSrujana Challa #define CPT_LF_Q_SIZE 0x100 5535c22fce6SSrujana Challa #define CPT_LF_Q_INST_PTR 0x110 554c57c58fdSSrujana Challa #define CPT_LF_Q_GRP_PTR 0x120 555149f3b73SSrujana Challa #define CPT_LF_CTX_FLUSH 0x510 556c57c58fdSSrujana Challa 55754d55781SSunil Goutham #define NPC_AF_BLK_RST (0x00040) 55854d55781SSunil Goutham 55923923ea4SSunil Goutham /* NPC */ 56023923ea4SSunil Goutham #define NPC_AF_CFG (0x00000) 56123923ea4SSunil Goutham #define NPC_AF_ACTIVE_PC (0x00010) 56223923ea4SSunil Goutham #define NPC_AF_CONST (0x00020) 56323923ea4SSunil Goutham #define NPC_AF_CONST1 (0x00030) 56423923ea4SSunil Goutham #define NPC_AF_BLK_RST (0x00040) 56523923ea4SSunil Goutham #define NPC_AF_MCAM_SCRUB_CTL (0x000a0) 56623923ea4SSunil Goutham #define NPC_AF_KCAM_SCRUB_CTL (0x000b0) 5671c1935c9SSubbaraya Sundeep #define NPC_AF_CONST2 (0x00100) 5681c1935c9SSubbaraya Sundeep #define NPC_AF_CONST3 (0x00110) 56923923ea4SSunil Goutham #define NPC_AF_KPUX_CFG(a) (0x00500 | (a) << 3) 57023923ea4SSunil Goutham #define NPC_AF_PCK_CFG (0x00600) 57123923ea4SSunil Goutham #define NPC_AF_PCK_DEF_OL2 (0x00610) 57223923ea4SSunil Goutham #define NPC_AF_PCK_DEF_OIP4 (0x00620) 57323923ea4SSunil Goutham #define NPC_AF_PCK_DEF_OIP6 (0x00630) 57423923ea4SSunil Goutham #define NPC_AF_PCK_DEF_IIP4 (0x00640) 57556d9f5fdSRatheesh Kannoth #define NPC_AF_INTFX_HASHX_RESULT_CTRL(a, b) (0x006c0 | (a) << 4 | (b) << 3) 57656d9f5fdSRatheesh Kannoth #define NPC_AF_INTFX_HASHX_MASKX(a, b, c) (0x00700 | (a) << 5 | (b) << 4 | (c) << 3) 57723923ea4SSunil Goutham #define NPC_AF_KEX_LDATAX_FLAGS_CFG(a) (0x00800 | (a) << 3) 57856d9f5fdSRatheesh Kannoth #define NPC_AF_INTFX_HASHX_CFG(a, b) (0x00b00 | (a) << 6 | (b) << 4) 57956d9f5fdSRatheesh Kannoth #define NPC_AF_INTFX_SECRET_KEY0(a) (0x00e00 | (a) << 3) 58056d9f5fdSRatheesh Kannoth #define NPC_AF_INTFX_SECRET_KEY1(a) (0x00e20 | (a) << 3) 58156d9f5fdSRatheesh Kannoth #define NPC_AF_INTFX_SECRET_KEY2(a) (0x00e40 | (a) << 3) 58223923ea4SSunil Goutham #define NPC_AF_INTFX_KEX_CFG(a) (0x01010 | (a) << 8) 58323923ea4SSunil Goutham #define NPC_AF_PKINDX_ACTION0(a) (0x80000ull | (a) << 6) 58423923ea4SSunil Goutham #define NPC_AF_PKINDX_ACTION1(a) (0x80008ull | (a) << 6) 58523923ea4SSunil Goutham #define NPC_AF_PKINDX_CPI_DEFX(a, b) (0x80020ull | (a) << 6 | (b) << 3) 58623923ea4SSunil Goutham #define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \ 58723923ea4SSunil Goutham (0x100000 | (a) << 14 | (b) << 6 | (c) << 3) 58823923ea4SSunil Goutham #define NPC_AF_KPUX_ENTRYX_ACTION0(a, b) \ 58923923ea4SSunil Goutham (0x100020 | (a) << 14 | (b) << 6) 59023923ea4SSunil Goutham #define NPC_AF_KPUX_ENTRYX_ACTION1(a, b) \ 59123923ea4SSunil Goutham (0x100028 | (a) << 14 | (b) << 6) 59223923ea4SSunil Goutham #define NPC_AF_KPUX_ENTRY_DISX(a, b) (0x180000 | (a) << 6 | (b) << 3) 59323923ea4SSunil Goutham #define NPC_AF_CPIX_CFG(a) (0x200000 | (a) << 3) 59423923ea4SSunil Goutham #define NPC_AF_INTFX_LIDX_LTX_LDX_CFG(a, b, c, d) \ 59523923ea4SSunil Goutham (0x900000 | (a) << 16 | (b) << 12 | (c) << 5 | (d) << 3) 59623923ea4SSunil Goutham #define NPC_AF_INTFX_LDATAX_FLAGSX_CFG(a, b, c) \ 59723923ea4SSunil Goutham (0x980000 | (a) << 16 | (b) << 12 | (c) << 3) 59823923ea4SSunil Goutham #define NPC_AF_INTFX_MISS_STAT_ACT(a) (0x1880040 + (a) * 0x8) 59923923ea4SSunil Goutham #define NPC_AF_INTFX_MISS_ACT(a) (0x1a00000 | (a) << 4) 60023923ea4SSunil Goutham #define NPC_AF_INTFX_MISS_TAG_ACT(a) (0x1b00008 | (a) << 4) 60123923ea4SSunil Goutham #define NPC_AF_MCAM_BANKX_HITX(a, b) (0x1c80000 | (a) << 8 | (b) << 4) 60223923ea4SSunil Goutham #define NPC_AF_LKUP_CTL (0x2000000) 60323923ea4SSunil Goutham #define NPC_AF_LKUP_DATAX(a) (0x2000200 | (a) << 4) 60423923ea4SSunil Goutham #define NPC_AF_LKUP_RESULTX(a) (0x2000400 | (a) << 4) 60523923ea4SSunil Goutham #define NPC_AF_INTFX_STAT(a) (0x2000800 | (a) << 4) 60623923ea4SSunil Goutham #define NPC_AF_DBG_CTL (0x3000000) 60723923ea4SSunil Goutham #define NPC_AF_DBG_STATUS (0x3000010) 60823923ea4SSunil Goutham #define NPC_AF_KPUX_DBG(a) (0x3000020 | (a) << 8) 60923923ea4SSunil Goutham #define NPC_AF_IKPU_ERR_CTL (0x3000080) 61023923ea4SSunil Goutham #define NPC_AF_KPUX_ERR_CTL(a) (0x30000a0 | (a) << 8) 61123923ea4SSunil Goutham #define NPC_AF_MCAM_DBG (0x3001000) 61223923ea4SSunil Goutham #define NPC_AF_DBG_DATAX(a) (0x3001400 | (a) << 4) 61323923ea4SSunil Goutham #define NPC_AF_DBG_RESULTX(a) (0x3001800 | (a) << 4) 61423923ea4SSunil Goutham 615b747923aSRatheesh Kannoth #define NPC_AF_EXACT_MEM_ENTRY(a, b) (0x300000 | (a) << 15 | (b) << 3) 616b747923aSRatheesh Kannoth #define NPC_AF_EXACT_CAM_ENTRY(a) (0xC00 | (a) << 3) 617b747923aSRatheesh Kannoth #define NPC_AF_INTFX_EXACT_MASK(a) (0x660 | (a) << 3) 618b747923aSRatheesh Kannoth #define NPC_AF_INTFX_EXACT_RESULT_CTL(a)(0x680 | (a) << 3) 619b747923aSRatheesh Kannoth #define NPC_AF_INTFX_EXACT_CFG(a) (0xA00 | (a) << 3) 620b747923aSRatheesh Kannoth #define NPC_AF_INTFX_EXACT_SECRET0(a) (0xE00 | (a) << 3) 621b747923aSRatheesh Kannoth #define NPC_AF_INTFX_EXACT_SECRET1(a) (0xE20 | (a) << 3) 622b747923aSRatheesh Kannoth #define NPC_AF_INTFX_EXACT_SECRET2(a) (0xE40 | (a) << 3) 623b747923aSRatheesh Kannoth 6241c1935c9SSubbaraya Sundeep #define NPC_AF_MCAMEX_BANKX_CAMX_INTF(a, b, c) ({ \ 6251c1935c9SSubbaraya Sundeep u64 offset; \ 6261c1935c9SSubbaraya Sundeep \ 6271c1935c9SSubbaraya Sundeep offset = (0x1000000ull | (a) << 10 | (b) << 6 | (c) << 3); \ 6281c1935c9SSubbaraya Sundeep if (rvu->hw->npc_ext_set) \ 6291c1935c9SSubbaraya Sundeep offset = (0x8000000ull | (a) << 8 | (b) << 22 | (c) << 3); \ 6301c1935c9SSubbaraya Sundeep offset; }) 6311c1935c9SSubbaraya Sundeep 6321c1935c9SSubbaraya Sundeep #define NPC_AF_MCAMEX_BANKX_CAMX_W0(a, b, c) ({ \ 6331c1935c9SSubbaraya Sundeep u64 offset; \ 6341c1935c9SSubbaraya Sundeep \ 6351c1935c9SSubbaraya Sundeep offset = (0x1000010ull | (a) << 10 | (b) << 6 | (c) << 3); \ 6361c1935c9SSubbaraya Sundeep if (rvu->hw->npc_ext_set) \ 6371c1935c9SSubbaraya Sundeep offset = (0x8000010ull | (a) << 8 | (b) << 22 | (c) << 3); \ 6381c1935c9SSubbaraya Sundeep offset; }) 6391c1935c9SSubbaraya Sundeep 6401c1935c9SSubbaraya Sundeep #define NPC_AF_MCAMEX_BANKX_CAMX_W1(a, b, c) ({ \ 6411c1935c9SSubbaraya Sundeep u64 offset; \ 6421c1935c9SSubbaraya Sundeep \ 6431c1935c9SSubbaraya Sundeep offset = (0x1000020ull | (a) << 10 | (b) << 6 | (c) << 3); \ 6441c1935c9SSubbaraya Sundeep if (rvu->hw->npc_ext_set) \ 6451c1935c9SSubbaraya Sundeep offset = (0x8000020ull | (a) << 8 | (b) << 22 | (c) << 3); \ 6461c1935c9SSubbaraya Sundeep offset; }) 6471c1935c9SSubbaraya Sundeep 6481c1935c9SSubbaraya Sundeep #define NPC_AF_MCAMEX_BANKX_CFG(a, b) ({ \ 6491c1935c9SSubbaraya Sundeep u64 offset; \ 6501c1935c9SSubbaraya Sundeep \ 6511c1935c9SSubbaraya Sundeep offset = (0x1800000ull | (a) << 8 | (b) << 4); \ 6521c1935c9SSubbaraya Sundeep if (rvu->hw->npc_ext_set) \ 6531c1935c9SSubbaraya Sundeep offset = (0x8000038ull | (a) << 8 | (b) << 22); \ 6541c1935c9SSubbaraya Sundeep offset; }) 6551c1935c9SSubbaraya Sundeep 6561c1935c9SSubbaraya Sundeep #define NPC_AF_MCAMEX_BANKX_ACTION(a, b) ({ \ 6571c1935c9SSubbaraya Sundeep u64 offset; \ 6581c1935c9SSubbaraya Sundeep \ 6591c1935c9SSubbaraya Sundeep offset = (0x1900000ull | (a) << 8 | (b) << 4); \ 6601c1935c9SSubbaraya Sundeep if (rvu->hw->npc_ext_set) \ 6611c1935c9SSubbaraya Sundeep offset = (0x8000040ull | (a) << 8 | (b) << 22); \ 6621c1935c9SSubbaraya Sundeep offset; }) \ 6631c1935c9SSubbaraya Sundeep 6641c1935c9SSubbaraya Sundeep #define NPC_AF_MCAMEX_BANKX_TAG_ACT(a, b) ({ \ 6651c1935c9SSubbaraya Sundeep u64 offset; \ 6661c1935c9SSubbaraya Sundeep \ 6671c1935c9SSubbaraya Sundeep offset = (0x1900008ull | (a) << 8 | (b) << 4); \ 6681c1935c9SSubbaraya Sundeep if (rvu->hw->npc_ext_set) \ 6691c1935c9SSubbaraya Sundeep offset = (0x8000048ull | (a) << 8 | (b) << 22); \ 6701c1935c9SSubbaraya Sundeep offset; }) \ 6711c1935c9SSubbaraya Sundeep 6721c1935c9SSubbaraya Sundeep #define NPC_AF_MCAMEX_BANKX_STAT_ACT(a, b) ({ \ 6731c1935c9SSubbaraya Sundeep u64 offset; \ 6741c1935c9SSubbaraya Sundeep \ 6751c1935c9SSubbaraya Sundeep offset = (0x1880000ull | (a) << 8 | (b) << 4); \ 6761c1935c9SSubbaraya Sundeep if (rvu->hw->npc_ext_set) \ 6771c1935c9SSubbaraya Sundeep offset = (0x8000050ull | (a) << 8 | (b) << 22); \ 6781c1935c9SSubbaraya Sundeep offset; }) \ 6791c1935c9SSubbaraya Sundeep 6801c1935c9SSubbaraya Sundeep #define NPC_AF_MATCH_STATX(a) ({ \ 6811c1935c9SSubbaraya Sundeep u64 offset; \ 6821c1935c9SSubbaraya Sundeep \ 6831c1935c9SSubbaraya Sundeep offset = (0x1880008ull | (a) << 8); \ 6841c1935c9SSubbaraya Sundeep if (rvu->hw->npc_ext_set) \ 6851c1935c9SSubbaraya Sundeep offset = (0x8000078ull | (a) << 8); \ 6861c1935c9SSubbaraya Sundeep offset; }) \ 6871c1935c9SSubbaraya Sundeep 688c5a797e0SPrakash Brahmajyosyula /* NDC */ 689c5a797e0SPrakash Brahmajyosyula #define NDC_AF_CONST (0x00000) 690c5a797e0SPrakash Brahmajyosyula #define NDC_AF_CLK_EN (0x00020) 691c5a797e0SPrakash Brahmajyosyula #define NDC_AF_CTL (0x00030) 692c5a797e0SPrakash Brahmajyosyula #define NDC_AF_BANK_CTL (0x00040) 693c5a797e0SPrakash Brahmajyosyula #define NDC_AF_BANK_CTL_DONE (0x00048) 694c5a797e0SPrakash Brahmajyosyula #define NDC_AF_INTR (0x00058) 695c5a797e0SPrakash Brahmajyosyula #define NDC_AF_INTR_W1S (0x00060) 696c5a797e0SPrakash Brahmajyosyula #define NDC_AF_INTR_ENA_W1S (0x00068) 697c5a797e0SPrakash Brahmajyosyula #define NDC_AF_INTR_ENA_W1C (0x00070) 698c5a797e0SPrakash Brahmajyosyula #define NDC_AF_ACTIVE_PC (0x00078) 699ea9dd2e5SSuman Ghosh #define NDC_AF_CAMS_RD_INTERVAL (0x00080) 700c5a797e0SPrakash Brahmajyosyula #define NDC_AF_BP_TEST_ENABLE (0x001F8) 701c5a797e0SPrakash Brahmajyosyula #define NDC_AF_BP_TEST(a) (0x00200 | (a) << 3) 702c5a797e0SPrakash Brahmajyosyula #define NDC_AF_BLK_RST (0x002F0) 703c5a797e0SPrakash Brahmajyosyula #define NDC_PRIV_AF_INT_CFG (0x002F8) 704c5a797e0SPrakash Brahmajyosyula #define NDC_AF_HASHX(a) (0x00300 | (a) << 3) 705c5a797e0SPrakash Brahmajyosyula #define NDC_AF_PORTX_RTX_RWX_REQ_PC(a, b, c) \ 706c5a797e0SPrakash Brahmajyosyula (0x00C00 | (a) << 5 | (b) << 4 | (c) << 3) 707c5a797e0SPrakash Brahmajyosyula #define NDC_AF_PORTX_RTX_RWX_OSTDN_PC(a, b, c) \ 708c5a797e0SPrakash Brahmajyosyula (0x00D00 | (a) << 5 | (b) << 4 | (c) << 3) 709c5a797e0SPrakash Brahmajyosyula #define NDC_AF_PORTX_RTX_RWX_LAT_PC(a, b, c) \ 710c5a797e0SPrakash Brahmajyosyula (0x00E00 | (a) << 5 | (b) << 4 | (c) << 3) 711c5a797e0SPrakash Brahmajyosyula #define NDC_AF_PORTX_RTX_CANT_ALLOC_PC(a, b) \ 712c5a797e0SPrakash Brahmajyosyula (0x00F00 | (a) << 5 | (b) << 4) 713c5a797e0SPrakash Brahmajyosyula #define NDC_AF_BANKX_HIT_PC(a) (0x01000 | (a) << 3) 714c5a797e0SPrakash Brahmajyosyula #define NDC_AF_BANKX_MISS_PC(a) (0x01100 | (a) << 3) 715ea9dd2e5SSuman Ghosh #define NDC_AF_BANKX_LINEX_METADATA(a, b) \ 716ea9dd2e5SSuman Ghosh (0x10000 | (a) << 12 | (b) << 3) 717242da439SSubbaraya Sundeep 718242da439SSubbaraya Sundeep /* LBK */ 719242da439SSubbaraya Sundeep #define LBK_CONST (0x10ull) 720242da439SSubbaraya Sundeep #define LBK_LINK_CFG_P2X (0x400ull) 721242da439SSubbaraya Sundeep #define LBK_LINK_CFG_X2P (0x408ull) 722242da439SSubbaraya Sundeep #define LBK_CONST_CHANS GENMASK_ULL(47, 32) 723242da439SSubbaraya Sundeep #define LBK_CONST_DST GENMASK_ULL(31, 28) 724242da439SSubbaraya Sundeep #define LBK_CONST_SRC GENMASK_ULL(27, 24) 7256e54e1c5SHariprasad Kelam #define LBK_CONST_BUF_SIZE GENMASK_ULL(23, 0) 726242da439SSubbaraya Sundeep #define LBK_LINK_CFG_RANGE_MASK GENMASK_ULL(19, 16) 727242da439SSubbaraya Sundeep #define LBK_LINK_CFG_ID_MASK GENMASK_ULL(11, 6) 728242da439SSubbaraya Sundeep #define LBK_LINK_CFG_BASE_MASK GENMASK_ULL(5, 0) 729242da439SSubbaraya Sundeep 730873a1e3dSHarman Kalra /* APR */ 731873a1e3dSHarman Kalra #define APR_AF_LMT_CFG (0x000ull) 732873a1e3dSHarman Kalra #define APR_AF_LMT_MAP_BASE (0x008ull) 733873a1e3dSHarman Kalra #define APR_AF_LMT_CTL (0x010ull) 73449d6baeaSHarman Kalra #define APR_LMT_MAP_ENT_DIS_SCH_CMP_SHIFT 23 73549d6baeaSHarman Kalra #define APR_LMT_MAP_ENT_SCH_ENA_SHIFT 22 73649d6baeaSHarman Kalra #define APR_LMT_MAP_ENT_DIS_LINE_PREF_SHIFT 21 737873a1e3dSHarman Kalra 73854d55781SSunil Goutham #endif /* RVU_REG_H */ 739