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/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_reg.c30 {NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
31 {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
32 {0x1200, 0x12E0} } },
33 {NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
34 {0x1610, 0x1618}, {0x1700, 0x17C8} } },
35 {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } },
36 {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
45 if (reg & 0x07) in rvu_check_valid_reg()
62 for (idx = 0; idx < map->num_ranges; idx++) { in rvu_check_valid_reg()
/openbmc/u-boot/include/environment/ti/
H A Ddfu.h13 "boot part 0 1;" \
14 "rootfs part 0 2;" \
15 "MLO fat 0 1;" \
16 "MLO.raw raw 0x100 0x100;" \
17 "u-boot.img.raw raw 0x300 0x1000;" \
18 "u-env.raw raw 0x1300 0x200;" \
19 "spl-os-args.raw raw 0x1500 0x200;" \
20 "spl-os-image.raw raw 0x1700 0x6900;" \
21 "spl-os-args fat 0 1;" \
22 "spl-os-image fat 0 1;" \
[all …]
/openbmc/linux/drivers/gpu/host1x/hw/
H A Dhw_host1x08_hypervisor.h6 #define HOST1X_HV_SYNCPT_PROT_EN 0x1724
8 #define HOST1X_HV_CH_MLOCK_EN(x) (0x1700 + (x * 4))
9 #define HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(x) (0x1710 + (x * 4))
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbtc8822bwifionly.c9 halwifionly_phy_set_bb_reg(wifionlycfg, 0x4c, 0x01800000, 0x2); in ex_hal8822b_wifi_only_hw_config()
11 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcb4, 0xff, 0x77); in ex_hal8822b_wifi_only_hw_config()
13 halwifionly_phy_set_bb_reg(wifionlycfg, 0x974, 0x300, 0x3); in ex_hal8822b_wifi_only_hw_config()
15 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1990, 0x300, 0x0); in ex_hal8822b_wifi_only_hw_config()
17 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x80000, 0x0); in ex_hal8822b_wifi_only_hw_config()
19 halwifionly_phy_set_bb_reg(wifionlycfg, 0x70, 0xff000000, 0x0e); in ex_hal8822b_wifi_only_hw_config()
20 /*gnt_wl=1 , gnt_bt=0*/ in ex_hal8822b_wifi_only_hw_config()
21 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1704, 0xffffffff, 0x7700); in ex_hal8822b_wifi_only_hw_config()
22 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1700, 0xffffffff, 0xc00f0038); in ex_hal8822b_wifi_only_hw_config()
41 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x300, 0x1); in hal8822b_wifi_only_switch_antenna()
[all …]
/openbmc/linux/drivers/regulator/
H A Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
H A Dslg51000-regulator.h14 #define SLG51000_SYSCTL_PATN_ID_B0 0x1105
15 #define SLG51000_SYSCTL_PATN_ID_B1 0x1106
16 #define SLG51000_SYSCTL_PATN_ID_B2 0x1107
17 #define SLG51000_SYSCTL_SYS_CONF_A 0x1109
18 #define SLG51000_SYSCTL_SYS_CONF_D 0x110c
19 #define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d
20 #define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e
21 #define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111
22 #define SLG51000_SYSCTL_UVLO_CONF_A 0x1112
23 #define SLG51000_SYSCTL_FAULT_LOG1 0x1115
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dcm2_54xx.h22 #define OMAP54XX_CM_CORE_BASE 0x4a008000
28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600
31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700
32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200
33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300
34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400
35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500
36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
[all …]
H A Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
H A Dcm2_7xx.h23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
H A Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dcontregs.h12 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */
13 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
14 #define AC_M_CXR 0x0200 /* shv Context Register */
15 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
16 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
17 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
18 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
19 #define AC_M_RESET 0x0700 /* hv Reset Reg */
20 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
21 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dcontregs.h15 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
16 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
17 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
18 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
19 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
20 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
21 #define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
22 #define AC_SYNC_ERR 0x60000000 /* c fault type */
23 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
24 #define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
[all …]
/openbmc/linux/drivers/char/mwave/
H A Dsmapi.c54 static unsigned short g_usSmapiPort = 0;
72 int retval = 0; in smapi_request()
77 __asm__ __volatile__("movw $0x5380,%%ax\n\t" in smapi_request()
86 "out %%al,$0x4F\n\t" in smapi_request()
87 "cmpb $0x53,%%ah\n\t" in smapi_request()
92 "movw %%ax,%0\n\t" in smapi_request()
121 retval = (usSmapiOK == 1) ? 0 : -EIO; in smapi_request()
132 0x0030, 0x4E30, 0x8E30, 0xCE30, in smapi_query_DSP_cfg()
133 0x0130, 0x0350, 0x0070, 0x0DB0 }; in smapi_query_DSP_cfg()
135 0x03F8, 0x02F8, 0x03E8, 0x02E8 }; in smapi_query_DSP_cfg()
[all …]
/openbmc/linux/drivers/bus/
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dsg-regs.h14 #define SG_CTRL_BASE 0x5f800000
15 #define SG_DBG_BASE 0x5f900000
18 #define SG_REVISION (SG_CTRL_BASE | 0x0000)
21 #define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
23 #define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
24 #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
25 #define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
26 #define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
27 #define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
28 #define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dqcom,pmic-typec.yaml95 #size-cells = <0>;
99 reg = <0x1500>,
100 <0x1700>;
102 interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
103 <0x2 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
104 <0x2 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
105 <0x2 0x15 0x03 IRQ_TYPE_EDGE_BOTH>,
106 <0x2 0x15 0x04 IRQ_TYPE_EDGE_RISING>,
107 <0x2 0x15 0x05 IRQ_TYPE_EDGE_RISING>,
108 <0x2 0x15 0x06 IRQ_TYPE_EDGE_BOTH>,
[all …]
H A Ddwc2.yaml25 - const: ingenic,x1700-otg
192 reg = <0x10180000 0x40000>;
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_plat.h15 #define SDRAM_CS_SIZE 0xfffffff /* FIXME: implement a function for cs size for each platform */
18 #define AP_INT_REG_START_ADDR 0xd0000000
19 #define AP_INT_REG_END_ADDR 0xd0100000
26 #define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xA
35 #define TUNE_TRAINING_PARAMS_DIC 0x2
36 #define TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS 0x120012
37 #define TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS 0x10000
38 #define TUNE_TRAINING_PARAMS_RTT_NOM 0x44
40 #define TUNE_TRAINING_PARAMS_RTT_WR_1CS 0x0 /*off*/
41 #define TUNE_TRAINING_PARAMS_RTT_WR_2CS 0x0 /*off*/
[all …]
/openbmc/linux/drivers/ufs/host/
H A Dufs-qcom.h14 #define MAX_U32 (~(u32)0)
15 #define MPHY_TX_FSM_STATE 0x41
16 #define TX_FSM_HIBERN8 0x1
24 #define UFS_HW_VER_STEP_MASK GENMASK(15, 0)
34 REG_UFS_SYS1CLK_1US = 0xC0,
35 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
36 REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
37 REG_UFS_PA_ERR_CODE = 0xCC,
39 REG_UFS_PARAM0 = 0xD0,
41 REG_UFS_CFG0 = 0xD8,
[all …]
/openbmc/linux/drivers/irqchip/
H A Dirq-clps711x.c19 #define CLPS711X_INTSR1 (0x0240)
20 #define CLPS711X_INTMR1 (0x0280)
21 #define CLPS711X_BLEOI (0x0600)
22 #define CLPS711X_MCEOI (0x0640)
23 #define CLPS711X_TEOI (0x0680)
24 #define CLPS711X_TC1EOI (0x06c0)
25 #define CLPS711X_TC2EOI (0x0700)
26 #define CLPS711X_RTCEOI (0x0740)
27 #define CLPS711X_UMSEOI (0x0780)
28 #define CLPS711X_COEOI (0x07c0)
[all …]
/openbmc/linux/arch/powerpc/kernel/
H A Dkgdb.c38 { 0x0100, 0x02 /* SIGINT */ }, /* system reset */
39 { 0x0200, 0x0b /* SIGSEGV */ }, /* machine check */
40 { 0x0300, 0x0b /* SIGSEGV */ }, /* data access */
41 { 0x0400, 0x0b /* SIGSEGV */ }, /* instruction access */
42 { 0x0500, 0x02 /* SIGINT */ }, /* external interrupt */
43 { 0x0600, 0x0a /* SIGBUS */ }, /* alignment */
44 { 0x0700, 0x05 /* SIGTRAP */ }, /* program check */
45 { 0x0800, 0x08 /* SIGFPE */ }, /* fp unavailable */
46 { 0x0900, 0x0e /* SIGALRM */ }, /* decrementer */
47 { 0x0c00, 0x14 /* SIGCHLD */ }, /* system call */
[all …]
/openbmc/u-boot/include/configs/
H A Dti_armv7_common.h25 * Our DDR memory always starts at 0x80000000 and U-Boot shall have
30 #define CONFIG_SYS_LOAD_ADDR 0x82000000
42 "loadaddr=0x82000000\0" \
43 "kernel_addr_r=0x82000000\0" \
44 "fdtaddr=0x88000000\0" \
45 "fdt_addr_r=0x88000000\0" \
46 "rdaddr=0x88080000\0" \
47 "ramdisk_addr_r=0x88080000\0" \
48 "scriptaddr=0x80000000\0" \
49 "pxefile_addr_r=0x80100000\0" \
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dprom.h20 #define OF_DT_BEGIN_NODE 0x1 /* Start of node, full name */
21 #define OF_DT_END_NODE 0x2 /* End node */
22 #define OF_DT_PROP 0x3 /* Property: name off, size,
24 #define OF_DT_NOP 0x4 /* nop */
25 #define OF_DT_END 0x9
27 #define OF_DT_VERSION 0x10
41 * ends when size is 0
102 #define OV_IGNORE 0x80 /* ignore this vector */
103 #define OV_CESSATION_POLICY 0x40 /* halt if unsupported option present*/
106 #define OV1_PPC_2_00 0x80 /* set if we support PowerPC 2.00 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/openbmc/qemu/hw/display/
H A Dati_dbg.c11 {"MM_INDEX", 0x0000},
12 {"MM_DATA", 0x0004},
13 {"CLOCK_CNTL_INDEX", 0x0008},
14 {"CLOCK_CNTL_DATA", 0x000c},
15 {"BIOS_0_SCRATCH", 0x0010},
16 {"BUS_CNTL", 0x0030},
17 {"BUS_CNTL1", 0x0034},
18 {"GEN_INT_CNTL", 0x0040},
19 {"GEN_INT_STATUS", 0x0044},
20 {"CRTC_GEN_CNTL", 0x0050},
[all …]

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