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/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dpower.h13 unsigned char res1[0x8];
16 unsigned char res2[0x1ec];
20 unsigned char res4[0x1f4];
23 unsigned char res5[0x1f8];
27 unsigned char res6[0xf4];
37 unsigned char res7[0xdc];
46 unsigned char res8[0x1e0];
48 unsigned char res9[0x5fc];
50 unsigned char res10[0xc];
52 unsigned char res11[0x6c];
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Drv770_smc.c34 #define FIRST_SMC_INT_VECT_REG 0xFFD8
35 #define FIRST_INT_VECT_S19 0xFFC0
38 0x08, 0x10, 0x08, 0x10,
39 0x08, 0x10, 0x08, 0x10,
40 0x08, 0x10, 0x08, 0x10,
41 0x08, 0x10, 0x08, 0x10,
42 0x08, 0x10, 0x08, 0x10,
43 0x08, 0x10, 0x08, 0x10,
44 0x08, 0x10, 0x08, 0x10,
45 0x08, 0x10, 0x08, 0x10,
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7-colibri.dtsi15 brightness-levels = <0 45 63 88 119 158 203 255>;
20 pinctrl-0 = <&pinctrl_gpio_bl_on>;
22 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
34 pinctrl-0 = <&pinctrl_usbc_det>;
40 pinctrl-0 = <&pinctrl_gpiokeys>;
111 pinctrl-0 = <&pinctrl_usbh_reg>;
151 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
157 assigned-clock-rates = <0>, <100000000>;
170 pinctrl-0 = <&pinctrl_enet1>;
175 #size-cells = <0>;
[all …]
H A Dimx7d-pico-pi.dts14 pinctrl-0 = <&pinctrl_gpio_leds>;
41 #sound-dai-cells = <0>;
42 reg = <0x0a>;
53 reg = <0x38>;
55 pinctrl-0 = <&pinctrl_touchscreen>;
66 pinctrl-0 = <&pinctrl_hog>;
70 MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14
71 MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14
72 MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14
73 MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14
[all …]
H A Dimx7d-pico-hobbit.dts14 pinctrl-0 = <&pinctrl_gpio_leds>;
41 #sound-dai-cells = <0>;
42 reg = <0x0a>;
55 reg = <0x50>;
61 ads7846@0 {
62 reg = <0>;
65 interrupts = <7 0>;
69 ti,x-min = /bits/ 16 <0>;
71 ti,y-min = /bits/ 16 <0>;
86 pinctrl-0 = <&pinctrl_hog>;
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-jerry.dts25 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
45 #size-cells = <0>;
52 0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01
53 0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
54 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
55 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f
56 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
57 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
58 0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
59 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6ull-colibri.dts38 pinctrl-0 = <&pinctrl_snvs_reg_sd>;
43 states = <1800000 0x1 3300000 0x0>;
57 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
62 pinctrl-0 = <&pinctrl_enet2>;
69 #size-cells = <0>;
81 pinctrl-0 = <&pinctrl_gpmi_nand>;
91 pinctrl-0 = <&pinctrl_i2c1>;
100 pinctrl-0 = <&pinctrl_i2c2>;
109 pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
110 reg = <0x2c>;
[all …]
/openbmc/u-boot/drivers/net/phy/
H A Dmeson-gxl.c18 * - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
43 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_startup()
46 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_startup()
49 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_startup()
52 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_startup()
57 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x8D80); in meson_gxl_startup()
62 wol = phy_read(phydev, MDIO_DEVAD_NONE, 0x15); in meson_gxl_startup()
63 if (wol < 0) in meson_gxl_startup()
67 if (lpa < 0) in meson_gxl_startup()
71 if (exp < 0) in meson_gxl_startup()
[all …]
/openbmc/phosphor-power/phosphor-regulators/test/actions/
H A Di2c_compare_bytes_action_tests.cpp50 std::vector<uint8_t> values{0x56, 0x14, 0xDA}; in TEST()
51 I2CCompareBytesAction action{0x7C, values}; in TEST()
53 EXPECT_EQ(action.getRegister(), 0x7C); in TEST()
56 EXPECT_EQ(action.getValues()[0], 0x56); in TEST()
57 EXPECT_EQ(action.getValues()[1], 0x14); in TEST()
58 EXPECT_EQ(action.getValues()[2], 0xDA); in TEST()
61 EXPECT_EQ(action.getMasks()[0], 0xFF); in TEST()
62 EXPECT_EQ(action.getMasks()[1], 0xFF); in TEST()
63 EXPECT_EQ(action.getMasks()[2], 0xFF); in TEST()
74 I2CCompareBytesAction action{0x7C, values}; in TEST()
[all …]
H A Di2c_write_bytes_action_tests.cpp53 std::vector<uint8_t> values{0x56, 0x14, 0xDA}; in TEST()
54 I2CWriteBytesAction action{0x7C, values}; in TEST()
56 EXPECT_EQ(action.getRegister(), 0x7C); in TEST()
59 EXPECT_EQ(action.getValues()[0], 0x56); in TEST()
60 EXPECT_EQ(action.getValues()[1], 0x14); in TEST()
61 EXPECT_EQ(action.getValues()[2], 0xDA); in TEST()
63 EXPECT_EQ(action.getMasks().size(), 0); in TEST()
74 I2CWriteBytesAction action{0x7C, values}; in TEST()
95 std::vector<uint8_t> values{0x56, 0x14}; in TEST()
96 std::vector<uint8_t> masks{0x7E, 0x3C}; in TEST()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/hdp/
H A Dhdp_5_2_1_sh_mask.h29 …HUB_TLVL__HDP_WR_TLVL__SHIFT 0x0
30 …HUB_TLVL__HDP_RD_TLVL__SHIFT 0x4
31 …HUB_TLVL__XDP_WR_TLVL__SHIFT 0x8
32 …HUB_TLVL__XDP_RD_TLVL__SHIFT 0xc
33 …UB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
34 …__HDP_WR_TLVL_MASK 0x0000000FL
35 …__HDP_RD_TLVL_MASK 0x000000F0L
36 …__XDP_WR_TLVL_MASK 0x00000F00L
37 …__XDP_RD_TLVL_MASK 0x0000F000L
38 …__XDP_MBX_WR_TLVL_MASK 0x000F0000L
[all …]
H A Dhdp_4_4_2_sh_mask.h29 …HUB_TLVL__HDP_WR_TLVL__SHIFT 0x0
30 …HUB_TLVL__HDP_RD_TLVL__SHIFT 0x4
31 …HUB_TLVL__XDP_WR_TLVL__SHIFT 0x8
32 …HUB_TLVL__XDP_RD_TLVL__SHIFT 0xc
33 …UB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
34 …__HDP_WR_TLVL_MASK 0x0000000FL
35 …__HDP_RD_TLVL_MASK 0x000000F0L
36 …__XDP_WR_TLVL_MASK 0x00000F00L
37 …__XDP_RD_TLVL_MASK 0x0000F000L
38 …__XDP_MBX_WR_TLVL_MASK 0x000F0000L
[all …]
H A Dhdp_6_0_0_sh_mask.h29 …NSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0
30 …_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL
32 …NSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4
33 …NSURFACE_INFO__NONSURF_VMID__SHIFT 0x8
34 …_INFO__NONSURF_SWAP_MASK 0x00000030L
35 …_INFO__NONSURF_VMID_MASK 0x00000F00L
37 …NSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0
38 …_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL
40 …RFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT 0x0
41 …RFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT 0x1
[all …]
H A Dhdp_4_0_sh_mask.h27 #define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0
28 #define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4
29 #define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8
30 #define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc
31 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
32 #define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L
33 #define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L
34 #define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L
35 #define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L
36 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L
[all …]
H A Dhdp_5_0_0_sh_mask.h27 …HUB_TLVL__HDP_WR_TLVL__SHIFT 0x0
28 …HUB_TLVL__HDP_RD_TLVL__SHIFT 0x4
29 …HUB_TLVL__XDP_WR_TLVL__SHIFT 0x8
30 …HUB_TLVL__XDP_RD_TLVL__SHIFT 0xc
31 …UB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
32 …__HDP_WR_TLVL_MASK 0x00000007L
33 …__HDP_RD_TLVL_MASK 0x00000070L
34 …__XDP_WR_TLVL_MASK 0x00000700L
35 …__XDP_RD_TLVL_MASK 0x00007000L
36 …__XDP_MBX_WR_TLVL_MASK 0x00070000L
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_0_0_sh_mask.h14 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
15 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
16 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
17 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
18 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
19 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
20 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
21 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
23 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
24 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
H A Ddpcs_2_1_0_sh_mask.h27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
30 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
34 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
37 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
H A Ddpcs_2_0_0_sh_mask.h27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
30 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
34 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
37 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
H A Ddpcs_3_0_3_sh_mask.h14 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
15 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
16 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
17 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
18 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
19 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
20 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
21 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
23 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
24 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
H A Ddpcs_2_0_3_sh_mask.h26 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
30 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
35 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/umc/
H A Dumc_6_7_0_sh_mask.h29 …C_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
30 …_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
31 …_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16
32 …_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18
33 …_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e
34 …_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
35 …_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26
36 …_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
37 …_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29
38 …_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
[all …]
/openbmc/linux/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param()
48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
[all …]
/openbmc/linux/arch/mips/alchemy/common/
H A Dsleeper.S46 sw k0, 0x20(sp)
48 sw k0, 0x1c(sp)
50 sw k0, 0x18(sp)
52 sw k0, 0x14(sp)
56 lw t0, 0(t1)
65 lui t3, 0xb190 /* sys_xxx */
66 sw sp, 0x0018(t3)
68 sw k0, 0x001c(t3)
73 sw zero, 0x0078(t3) /* sys_slppwr */
75 sw zero, 0x007c(t3) /* sys_sleep */
[all …]
/openbmc/linux/include/linux/regulator/
H A Dpca9450.h10 PCA9450_TYPE_PCA9450A = 0,
16 PCA9450_BUCK1 = 0,
31 PCA9450_DVS_LEVEL_RUN = 0,
36 #define PCA9450_BUCK1_VOLTAGE_NUM 0x80
37 #define PCA9450_BUCK2_VOLTAGE_NUM 0x80
38 #define PCA9450_BUCK3_VOLTAGE_NUM 0x80
39 #define PCA9450_BUCK4_VOLTAGE_NUM 0x80
41 #define PCA9450_BUCK5_VOLTAGE_NUM 0x80
42 #define PCA9450_BUCK6_VOLTAGE_NUM 0x80
44 #define PCA9450_LDO1_VOLTAGE_NUM 0x08
[all …]
/openbmc/qemu/target/ppc/translate/
H A Dvsx-ops.c.inc1 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
2 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
3 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
5 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
6 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
7 GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
8 GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
9 GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
13 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
14 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
[all …]

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