12a3196f1SHawking Zhang /* 22a3196f1SHawking Zhang * Copyright (C) 2019 Advanced Micro Devices, Inc. 32a3196f1SHawking Zhang * 42a3196f1SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 52a3196f1SHawking Zhang * copy of this software and associated documentation files (the "Software"), 62a3196f1SHawking Zhang * to deal in the Software without restriction, including without limitation 72a3196f1SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 82a3196f1SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 92a3196f1SHawking Zhang * Software is furnished to do so, subject to the following conditions: 102a3196f1SHawking Zhang * 112a3196f1SHawking Zhang * The above copyright notice and this permission notice shall be included 122a3196f1SHawking Zhang * in all copies or substantial portions of the Software. 132a3196f1SHawking Zhang * 142a3196f1SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 152a3196f1SHawking Zhang * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 162a3196f1SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 172a3196f1SHawking Zhang * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 182a3196f1SHawking Zhang * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 192a3196f1SHawking Zhang * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 202a3196f1SHawking Zhang */ 212a3196f1SHawking Zhang #ifndef _hdp_5_0_0_SH_MASK_HEADER 222a3196f1SHawking Zhang #define _hdp_5_0_0_SH_MASK_HEADER 232a3196f1SHawking Zhang 242a3196f1SHawking Zhang 252a3196f1SHawking Zhang // addressBlock: hdp_hdpdec 262a3196f1SHawking Zhang //HDP_MMHUB_TLVL 272a3196f1SHawking Zhang #define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0 282a3196f1SHawking Zhang #define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4 292a3196f1SHawking Zhang #define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8 302a3196f1SHawking Zhang #define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc 312a3196f1SHawking Zhang #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10 322a3196f1SHawking Zhang #define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L 332a3196f1SHawking Zhang #define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L 342a3196f1SHawking Zhang #define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L 352a3196f1SHawking Zhang #define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L 362a3196f1SHawking Zhang #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L 372a3196f1SHawking Zhang //HDP_MMHUB_UNITID 382a3196f1SHawking Zhang #define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0 392a3196f1SHawking Zhang #define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8 402a3196f1SHawking Zhang #define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10 412a3196f1SHawking Zhang #define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL 422a3196f1SHawking Zhang #define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L 432a3196f1SHawking Zhang #define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L 442a3196f1SHawking Zhang //HDP_NONSURFACE_BASE 452a3196f1SHawking Zhang #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0 462a3196f1SHawking Zhang #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL 472a3196f1SHawking Zhang //HDP_NONSURFACE_INFO 482a3196f1SHawking Zhang #define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4 492a3196f1SHawking Zhang #define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8 502a3196f1SHawking Zhang #define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L 512a3196f1SHawking Zhang #define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L 522a3196f1SHawking Zhang //HDP_NONSURFACE_BASE_HI 532a3196f1SHawking Zhang #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0 542a3196f1SHawking Zhang #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL 552a3196f1SHawking Zhang //HDP_SURFACE_WRITE_FLAGS 562a3196f1SHawking Zhang #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT 0x0 572a3196f1SHawking Zhang #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT 0x1 582a3196f1SHawking Zhang #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK 0x00000001L 592a3196f1SHawking Zhang #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK 0x00000002L 602a3196f1SHawking Zhang //HDP_SURFACE_READ_FLAGS 612a3196f1SHawking Zhang #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT 0x0 622a3196f1SHawking Zhang #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT 0x1 632a3196f1SHawking Zhang #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK 0x00000001L 642a3196f1SHawking Zhang #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK 0x00000002L 652a3196f1SHawking Zhang //HDP_SURFACE_WRITE_FLAGS_CLR 662a3196f1SHawking Zhang #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT 0x0 672a3196f1SHawking Zhang #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT 0x1 682a3196f1SHawking Zhang #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK 0x00000001L 692a3196f1SHawking Zhang #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK 0x00000002L 702a3196f1SHawking Zhang //HDP_SURFACE_READ_FLAGS_CLR 712a3196f1SHawking Zhang #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT 0x0 722a3196f1SHawking Zhang #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT 0x1 732a3196f1SHawking Zhang #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK 0x00000001L 742a3196f1SHawking Zhang #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK 0x00000002L 752a3196f1SHawking Zhang //HDP_NONSURF_FLAGS 762a3196f1SHawking Zhang #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 772a3196f1SHawking Zhang #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 782a3196f1SHawking Zhang #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L 792a3196f1SHawking Zhang #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L 802a3196f1SHawking Zhang //HDP_NONSURF_FLAGS_CLR 812a3196f1SHawking Zhang #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 822a3196f1SHawking Zhang #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 832a3196f1SHawking Zhang #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L 842a3196f1SHawking Zhang #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L 852a3196f1SHawking Zhang //HDP_HOST_PATH_CNTL 862a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 872a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb 882a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12 892a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 902a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 912a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16 922a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__RD_CPL_BUF_EN__SHIFT 0x17 932a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d 942a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e 952a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f 962a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L 972a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L 982a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L 992a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L 1002a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L 1012a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L 1022a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__RD_CPL_BUF_EN_MASK 0x00800000L 1032a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L 1042a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L 1052a3196f1SHawking Zhang #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L 1062a3196f1SHawking Zhang //HDP_SW_SEMAPHORE 1072a3196f1SHawking Zhang #define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 1082a3196f1SHawking Zhang #define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL 1092a3196f1SHawking Zhang //HDP_LAST_SURFACE_HIT 1102a3196f1SHawking Zhang #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 1112a3196f1SHawking Zhang #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L 1122a3196f1SHawking Zhang //HDP_READ_CACHE_INVALIDATE 1132a3196f1SHawking Zhang #define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT 0x0 1142a3196f1SHawking Zhang #define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK 0x00000001L 1152a3196f1SHawking Zhang //HDP_OUTSTANDING_REQ 1162a3196f1SHawking Zhang #define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 1172a3196f1SHawking Zhang #define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 1182a3196f1SHawking Zhang #define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL 1192a3196f1SHawking Zhang #define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L 1202a3196f1SHawking Zhang //HDP_MISC_CNTL 1212a3196f1SHawking Zhang #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 1222a3196f1SHawking Zhang #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2 1232a3196f1SHawking Zhang #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 1242a3196f1SHawking Zhang #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 1252a3196f1SHawking Zhang #define HDP_MISC_CNTL__RAW_ADDR_CAM_ENABLE__SHIFT 0x7 1262a3196f1SHawking Zhang #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT 0x8 1272a3196f1SHawking Zhang #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb 1282a3196f1SHawking Zhang #define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 1292a3196f1SHawking Zhang #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT 0x16 1302a3196f1SHawking Zhang #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17 1312a3196f1SHawking Zhang #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18 1322a3196f1SHawking Zhang #define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT 0x19 1332a3196f1SHawking Zhang #define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1a 1342a3196f1SHawking Zhang #define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1b 1352a3196f1SHawking Zhang #define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT 0x1c 1362a3196f1SHawking Zhang #define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT 0x1d 1372a3196f1SHawking Zhang #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e 1382a3196f1SHawking Zhang #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L 1392a3196f1SHawking Zhang #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL 1402a3196f1SHawking Zhang #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L 1412a3196f1SHawking Zhang #define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L 1422a3196f1SHawking Zhang #define HDP_MISC_CNTL__RAW_ADDR_CAM_ENABLE_MASK 0x00000080L 1432a3196f1SHawking Zhang #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK 0x00000100L 1442a3196f1SHawking Zhang #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L 1452a3196f1SHawking Zhang #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L 1462a3196f1SHawking Zhang #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK 0x00400000L 1472a3196f1SHawking Zhang #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L 1482a3196f1SHawking Zhang #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L 1492a3196f1SHawking Zhang #define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK 0x02000000L 1502a3196f1SHawking Zhang #define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x04000000L 1512a3196f1SHawking Zhang #define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x08000000L 1522a3196f1SHawking Zhang #define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK 0x10000000L 1532a3196f1SHawking Zhang #define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK 0x20000000L 1542a3196f1SHawking Zhang #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L 1552a3196f1SHawking Zhang //HDP_MEM_POWER_CTRL 1562a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN__SHIFT 0x0 1572a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN__SHIFT 0x1 1582a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN__SHIFT 0x2 1592a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN__SHIFT 0x3 1602a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_IDLE_HYSTERESIS__SHIFT 0x4 1612a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 1622a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0xe 1632a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT 0x10 1642a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT 0x11 1652a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT 0x12 1662a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT 0x13 1672a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14 1682a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18 1692a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0x1e 1702a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L 1712a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L 1722a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK 0x00000004L 1732a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK 0x00000008L 1742a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_IDLE_HYSTERESIS_MASK 0x00000070L 1752a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L 1762a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0x0000C000L 1772a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 1782a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 1792a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK 0x00040000L 1802a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK 0x00080000L 1812a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK 0x00700000L 1822a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L 1832a3196f1SHawking Zhang #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0xC0000000L 1842a3196f1SHawking Zhang //HDP_MMHUB_CNTL 1852a3196f1SHawking Zhang #define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0 1862a3196f1SHawking Zhang #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1 1872a3196f1SHawking Zhang #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2 1882a3196f1SHawking Zhang #define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L 1892a3196f1SHawking Zhang #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L 1902a3196f1SHawking Zhang #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L 1912a3196f1SHawking Zhang //HDP_EDC_CNT 1922a3196f1SHawking Zhang #define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT 0x0 1932a3196f1SHawking Zhang #define HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT 0x2 1942a3196f1SHawking Zhang #define HDP_EDC_CNT__MEM2_SED_COUNT__SHIFT 0x4 1952a3196f1SHawking Zhang #define HDP_EDC_CNT__MEM3_SED_COUNT__SHIFT 0x6 1962a3196f1SHawking Zhang #define HDP_EDC_CNT__MEM0_SED_COUNT_MASK 0x00000003L 1972a3196f1SHawking Zhang #define HDP_EDC_CNT__MEM1_SED_COUNT_MASK 0x0000000CL 1982a3196f1SHawking Zhang #define HDP_EDC_CNT__MEM2_SED_COUNT_MASK 0x00000030L 1992a3196f1SHawking Zhang #define HDP_EDC_CNT__MEM3_SED_COUNT_MASK 0x000000C0L 2002a3196f1SHawking Zhang //HDP_VERSION 2012a3196f1SHawking Zhang #define HDP_VERSION__MINVER__SHIFT 0x0 2022a3196f1SHawking Zhang #define HDP_VERSION__MAJVER__SHIFT 0x8 2032a3196f1SHawking Zhang #define HDP_VERSION__REV__SHIFT 0x10 2042a3196f1SHawking Zhang #define HDP_VERSION__MINVER_MASK 0x000000FFL 2052a3196f1SHawking Zhang #define HDP_VERSION__MAJVER_MASK 0x0000FF00L 2062a3196f1SHawking Zhang #define HDP_VERSION__REV_MASK 0x00FF0000L 2072a3196f1SHawking Zhang //HDP_CLK_CNTL 2082a3196f1SHawking Zhang #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0 2092a3196f1SHawking Zhang #define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT 0x4 2102a3196f1SHawking Zhang #define HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a 2112a3196f1SHawking Zhang #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1b 2122a3196f1SHawking Zhang #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c 2132a3196f1SHawking Zhang #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d 2142a3196f1SHawking Zhang #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e 2152a3196f1SHawking Zhang #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f 2162a3196f1SHawking Zhang #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL 2172a3196f1SHawking Zhang #define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK 0x00000010L 2182a3196f1SHawking Zhang #define HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L 2192a3196f1SHawking Zhang #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK 0x08000000L 2202a3196f1SHawking Zhang #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L 2212a3196f1SHawking Zhang #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L 2222a3196f1SHawking Zhang #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L 2232a3196f1SHawking Zhang #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L 2242a3196f1SHawking Zhang //HDP_MEMIO_CNTL 2252a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 2262a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 2272a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 2282a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 2292a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 2302a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 2312a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe 2322a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf 2332a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 2342a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 2352a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L 2362a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L 2372a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL 2382a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L 2392a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L 2402a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L 2412a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L 2422a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L 2432a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L 2442a3196f1SHawking Zhang #define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L 2452a3196f1SHawking Zhang //HDP_MEMIO_ADDR 2462a3196f1SHawking Zhang #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 2472a3196f1SHawking Zhang #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL 2482a3196f1SHawking Zhang //HDP_MEMIO_STATUS 2492a3196f1SHawking Zhang #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 2502a3196f1SHawking Zhang #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 2512a3196f1SHawking Zhang #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 2522a3196f1SHawking Zhang #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 2532a3196f1SHawking Zhang #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L 2542a3196f1SHawking Zhang #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L 2552a3196f1SHawking Zhang #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L 2562a3196f1SHawking Zhang #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L 2572a3196f1SHawking Zhang //HDP_MEMIO_WR_DATA 2582a3196f1SHawking Zhang #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 2592a3196f1SHawking Zhang #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL 2602a3196f1SHawking Zhang //HDP_MEMIO_RD_DATA 2612a3196f1SHawking Zhang #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 2622a3196f1SHawking Zhang #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL 2632a3196f1SHawking Zhang //HDP_XDP_DIRECT2HDP_FIRST 2642a3196f1SHawking Zhang #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 2652a3196f1SHawking Zhang #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL 2662a3196f1SHawking Zhang //HDP_XDP_D2H_FLUSH 2672a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 2682a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 2692a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 2702a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb 2712a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 2722a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 2732a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 2742a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 2752a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL 2762a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L 2772a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L 2782a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L 2792a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L 2802a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L 2812a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L 2822a3196f1SHawking Zhang #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L 2832a3196f1SHawking Zhang //HDP_XDP_D2H_BAR_UPDATE 2842a3196f1SHawking Zhang #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 2852a3196f1SHawking Zhang #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 2862a3196f1SHawking Zhang #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 2872a3196f1SHawking Zhang #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL 2882a3196f1SHawking Zhang #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L 2892a3196f1SHawking Zhang #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L 2902a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_3 2912a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 2922a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL 2932a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_4 2942a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 2952a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL 2962a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_5 2972a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 2982a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL 2992a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_6 3002a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 3012a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL 3022a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_7 3032a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 3042a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL 3052a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_8 3062a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 3072a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL 3082a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_9 3092a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 3102a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL 3112a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_10 3122a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 3132a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL 3142a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_11 3152a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 3162a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL 3172a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_12 3182a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 3192a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL 3202a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_13 3212a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 3222a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL 3232a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_14 3242a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 3252a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL 3262a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_15 3272a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 3282a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL 3292a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_16 3302a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 3312a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL 3322a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_17 3332a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 3342a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL 3352a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_18 3362a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 3372a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL 3382a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_19 3392a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 3402a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL 3412a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_20 3422a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 3432a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL 3442a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_21 3452a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 3462a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL 3472a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_22 3482a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 3492a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL 3502a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_23 3512a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 3522a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL 3532a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_24 3542a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 3552a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL 3562a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_25 3572a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 3582a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL 3592a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_26 3602a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 3612a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL 3622a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_27 3632a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 3642a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL 3652a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_28 3662a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 3672a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL 3682a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_29 3692a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 3702a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL 3712a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_30 3722a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 3732a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL 3742a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_31 3752a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 3762a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL 3772a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_32 3782a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 3792a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL 3802a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_33 3812a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 3822a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL 3832a3196f1SHawking Zhang //HDP_XDP_D2H_RSVD_34 3842a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 3852a3196f1SHawking Zhang #define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL 3862a3196f1SHawking Zhang //HDP_XDP_DIRECT2HDP_LAST 3872a3196f1SHawking Zhang #define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 3882a3196f1SHawking Zhang #define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL 3892a3196f1SHawking Zhang //HDP_XDP_P2P_BAR_CFG 3902a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 3912a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 3922a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL 3932a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L 3942a3196f1SHawking Zhang //HDP_XDP_P2P_MBX_OFFSET 3952a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 3962a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL 3972a3196f1SHawking Zhang //HDP_XDP_P2P_MBX_ADDR0 3982a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 3992a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3 4002a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14 4012a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18 4022a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L 4032a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L 4042a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L 4052a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L 4062a3196f1SHawking Zhang //HDP_XDP_P2P_MBX_ADDR1 4072a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 4082a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3 4092a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14 4102a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18 4112a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L 4122a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L 4132a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L 4142a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L 4152a3196f1SHawking Zhang //HDP_XDP_P2P_MBX_ADDR2 4162a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 4172a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3 4182a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14 4192a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18 4202a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L 4212a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L 4222a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L 4232a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L 4242a3196f1SHawking Zhang //HDP_XDP_P2P_MBX_ADDR3 4252a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 4262a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3 4272a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14 4282a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18 4292a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L 4302a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L 4312a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L 4322a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L 4332a3196f1SHawking Zhang //HDP_XDP_P2P_MBX_ADDR4 4342a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 4352a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3 4362a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14 4372a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18 4382a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L 4392a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L 4402a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L 4412a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L 4422a3196f1SHawking Zhang //HDP_XDP_P2P_MBX_ADDR5 4432a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 4442a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3 4452a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14 4462a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18 4472a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L 4482a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L 4492a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L 4502a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L 4512a3196f1SHawking Zhang //HDP_XDP_P2P_MBX_ADDR6 4522a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 4532a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3 4542a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14 4552a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18 4562a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L 4572a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L 4582a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L 4592a3196f1SHawking Zhang #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L 4602a3196f1SHawking Zhang //HDP_XDP_HDP_MBX_MC_CFG 4612a3196f1SHawking Zhang #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0 4622a3196f1SHawking Zhang #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4 4632a3196f1SHawking Zhang #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8 4642a3196f1SHawking Zhang #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc 4652a3196f1SHawking Zhang #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd 4662a3196f1SHawking Zhang #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe 4672a3196f1SHawking Zhang #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL 4682a3196f1SHawking Zhang #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L 4692a3196f1SHawking Zhang #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L 4702a3196f1SHawking Zhang #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L 4712a3196f1SHawking Zhang #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L 4722a3196f1SHawking Zhang #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L 4732a3196f1SHawking Zhang //HDP_XDP_HDP_MC_CFG 4742a3196f1SHawking Zhang #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3 4752a3196f1SHawking Zhang #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4 4762a3196f1SHawking Zhang #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8 4772a3196f1SHawking Zhang #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc 4782a3196f1SHawking Zhang #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd 4792a3196f1SHawking Zhang #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe 4802a3196f1SHawking Zhang #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L 4812a3196f1SHawking Zhang #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L 4822a3196f1SHawking Zhang #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L 4832a3196f1SHawking Zhang #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L 4842a3196f1SHawking Zhang #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L 4852a3196f1SHawking Zhang #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L 4862a3196f1SHawking Zhang //HDP_XDP_HST_CFG 4872a3196f1SHawking Zhang #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 4882a3196f1SHawking Zhang #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 4892a3196f1SHawking Zhang #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3 4902a3196f1SHawking Zhang #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4 4912a3196f1SHawking Zhang #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5 4922a3196f1SHawking Zhang #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L 4932a3196f1SHawking Zhang #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L 4942a3196f1SHawking Zhang #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L 4952a3196f1SHawking Zhang #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L 4962a3196f1SHawking Zhang #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L 4972a3196f1SHawking Zhang //HDP_XDP_HDP_IPH_CFG 4982a3196f1SHawking Zhang #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 4992a3196f1SHawking Zhang #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 5002a3196f1SHawking Zhang #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc 5012a3196f1SHawking Zhang #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd 5022a3196f1SHawking Zhang #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003FL 5032a3196f1SHawking Zhang #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000FC0L 5042a3196f1SHawking Zhang #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L 5052a3196f1SHawking Zhang #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L 5062a3196f1SHawking Zhang //HDP_XDP_P2P_BAR0 5072a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 5082a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 5092a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 5102a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL 5112a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L 5122a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L 5132a3196f1SHawking Zhang //HDP_XDP_P2P_BAR1 5142a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 5152a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 5162a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 5172a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL 5182a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L 5192a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L 5202a3196f1SHawking Zhang //HDP_XDP_P2P_BAR2 5212a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 5222a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 5232a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 5242a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL 5252a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L 5262a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L 5272a3196f1SHawking Zhang //HDP_XDP_P2P_BAR3 5282a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 5292a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 5302a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 5312a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL 5322a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L 5332a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L 5342a3196f1SHawking Zhang //HDP_XDP_P2P_BAR4 5352a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 5362a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 5372a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 5382a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL 5392a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L 5402a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L 5412a3196f1SHawking Zhang //HDP_XDP_P2P_BAR5 5422a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 5432a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 5442a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 5452a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL 5462a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L 5472a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L 5482a3196f1SHawking Zhang //HDP_XDP_P2P_BAR6 5492a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 5502a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 5512a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 5522a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL 5532a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L 5542a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L 5552a3196f1SHawking Zhang //HDP_XDP_P2P_BAR7 5562a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 5572a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 5582a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 5592a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL 5602a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L 5612a3196f1SHawking Zhang #define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L 5622a3196f1SHawking Zhang //HDP_XDP_FLUSH_ARMED_STS 5632a3196f1SHawking Zhang #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 5642a3196f1SHawking Zhang #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL 5652a3196f1SHawking Zhang //HDP_XDP_FLUSH_CNTR0_STS 5662a3196f1SHawking Zhang #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 5672a3196f1SHawking Zhang #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL 5682a3196f1SHawking Zhang //HDP_XDP_BUSY_STS 5692a3196f1SHawking Zhang #define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 5702a3196f1SHawking Zhang #define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x00FFFFFFL 5712a3196f1SHawking Zhang //HDP_XDP_STICKY 5722a3196f1SHawking Zhang #define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 5732a3196f1SHawking Zhang #define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 5742a3196f1SHawking Zhang #define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL 5752a3196f1SHawking Zhang #define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L 5762a3196f1SHawking Zhang //HDP_XDP_CHKN 5772a3196f1SHawking Zhang #define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 5782a3196f1SHawking Zhang #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 5792a3196f1SHawking Zhang #define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 5802a3196f1SHawking Zhang #define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 5812a3196f1SHawking Zhang #define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL 5822a3196f1SHawking Zhang #define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L 5832a3196f1SHawking Zhang #define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L 5842a3196f1SHawking Zhang #define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L 5852a3196f1SHawking Zhang //HDP_XDP_BARS_ADDR_39_36 5862a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 5872a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 5882a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 5892a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc 5902a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 5912a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 5922a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 5932a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c 5942a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL 5952a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L 5962a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L 5972a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L 5982a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L 5992a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L 6002a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L 6012a3196f1SHawking Zhang #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L 6022a3196f1SHawking Zhang //HDP_XDP_MC_VM_FB_LOCATION_BASE 6032a3196f1SHawking Zhang #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 6042a3196f1SHawking Zhang #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL 6052a3196f1SHawking Zhang //HDP_XDP_GPU_IOV_VIOLATION_LOG 6062a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 6072a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 6082a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 6092a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 6102a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 6112a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 6122a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 6132a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 6142a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 6152a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L 6162a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 6172a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x01F00000L 6182a3196f1SHawking Zhang //HDP_XDP_GPU_IOV_VIOLATION_LOG2 6192a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 6202a3196f1SHawking Zhang #define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL 6212a3196f1SHawking Zhang //HDP_XDP_MMHUB_ERROR 6222a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1 6232a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2 6242a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3 6252a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5 6262a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6 6272a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7 6282a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9 6292a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa 6302a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb 6312a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd 6322a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe 6332a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf 6342a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11 6352a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12 6362a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13 6372a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15 6382a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16 6392a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17 6402a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L 6412a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L 6422a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L 6432a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L 6442a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L 6452a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L 6462a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L 6472a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L 6482a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L 6492a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L 6502a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L 6512a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L 6522a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L 6532a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L 6542a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L 6552a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L 6562a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L 6572a3196f1SHawking Zhang #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L 6582a3196f1SHawking Zhang 6592a3196f1SHawking Zhang #endif 660