1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2018 Toradex AG 4 */ 5 6/dts-v1/; 7#include <dt-bindings/gpio/gpio.h> 8#include "imx6ull.dtsi" 9 10/ { 11 model = "Toradex Colibri iMX6ULL"; 12 compatible = "toradex,imx6ull-colibri", "fsl,imx6ull"; 13 14 chosen { 15 stdout-path = &uart1; 16 }; 17 18 reg_module_3v3: regulator-module-3v3 { 19 compatible = "regulator-fixed"; 20 regulator-always-on; 21 regulator-name = "+V3.3"; 22 regulator-min-microvolt = <3300000>; 23 regulator-max-microvolt = <3300000>; 24 }; 25 26 reg_module_3v3_avdd: regulator-module-3v3-avdd { 27 compatible = "regulator-fixed"; 28 regulator-always-on; 29 regulator-name = "+V3.3_AVDD_AUDIO"; 30 regulator-min-microvolt = <3300000>; 31 regulator-max-microvolt = <3300000>; 32 }; 33 34 reg_sd1_vmmc: regulator-sd1-vmmc { 35 compatible = "regulator-gpio"; 36 gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; 37 pinctrl-names = "default"; 38 pinctrl-0 = <&pinctrl_snvs_reg_sd>; 39 regulator-always-on; 40 regulator-name = "+V3.3_1.8_SD"; 41 regulator-min-microvolt = <1800000>; 42 regulator-max-microvolt = <3300000>; 43 states = <1800000 0x1 3300000 0x0>; 44 vin-supply = <®_module_3v3>; 45 }; 46}; 47 48&adc1 { 49 num-channels = <10>; 50 vref-supply = <®_module_3v3_avdd>; 51}; 52 53/* Colibri SPI */ 54&ecspi1 { 55 cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; 56 pinctrl-names = "default"; 57 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 58}; 59 60&fec2 { 61 pinctrl-names = "default"; 62 pinctrl-0 = <&pinctrl_enet2>; 63 phy-mode = "rmii"; 64 phy-handle = <ðphy1>; 65 status = "okay"; 66 67 mdio { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 ethphy1: ethernet-phy@2 { 72 compatible = "ethernet-phy-ieee802.3-c22"; 73 max-speed = <100>; 74 reg = <2>; 75 }; 76 }; 77}; 78 79&gpmi { 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_gpmi_nand>; 82 nand-on-flash-bbt; 83 nand-ecc-mode = "hw"; 84 nand-ecc-strength = <8>; 85 nand-ecc-step-size = <512>; 86 status = "okay"; 87}; 88 89&i2c1 { 90 pinctrl-names = "default", "gpio"; 91 pinctrl-0 = <&pinctrl_i2c1>; 92 pinctrl-1 = <&pinctrl_i2c1_gpio>; 93 sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; 94 scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; 95 status = "okay"; 96}; 97 98&i2c2 { 99 pinctrl-names = "default", "gpio"; 100 pinctrl-0 = <&pinctrl_i2c2>; 101 pinctrl-1 = <&pinctrl_i2c2_gpio>; 102 sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; 103 scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 104 status = "okay"; 105 106 ad7879@2c { 107 compatible = "adi,ad7879-1"; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_snvs_ad7879_int>; 110 reg = <0x2c>; 111 interrupt-parent = <&gpio5>; 112 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 113 touchscreen-max-pressure = <4096>; 114 adi,resistance-plate-x = <120>; 115 adi,first-conversion-delay = /bits/ 8 <3>; 116 adi,acquisition-time = /bits/ 8 <1>; 117 adi,median-filter-size = /bits/ 8 <2>; 118 adi,averaging = /bits/ 8 <1>; 119 adi,conversion-interval = /bits/ 8 <255>; 120 }; 121}; 122 123&lcdif { 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_lcdif_dat 126 &pinctrl_lcdif_ctrl>; 127}; 128 129&pwm4 { 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_pwm4>; 132 #pwm-cells = <3>; 133}; 134 135&pwm5 { 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_pwm5>; 138 #pwm-cells = <3>; 139}; 140 141&pwm6 { 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_pwm6>; 144 #pwm-cells = <3>; 145}; 146 147&pwm7 { 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_pwm7>; 150 #pwm-cells = <3>; 151}; 152 153&sdma { 154 status = "okay"; 155}; 156 157&snvs_pwrkey { 158 status = "disabled"; 159}; 160 161&uart1 { 162 pinctrl-names = "default"; 163 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; 164 fsl,uart-has-rtscts; 165 fsl,dte-mode; 166 status = "okay"; 167}; 168 169&uart2 { 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_uart2>; 172 fsl,uart-has-rtscts; 173 fsl,dte-mode; 174}; 175 176&uart5 { 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_uart5>; 179 fsl,dte-mode; 180}; 181 182&usbotg1 { 183 dr_mode = "otg"; 184 srp-disable; 185 hnp-disable; 186 adp-disable; 187}; 188 189&usbotg2 { 190 dr_mode = "host"; 191}; 192 193&usdhc1 { 194 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; 195 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; 196 assigned-clock-rates = <0>, <198000000>; 197}; 198 199&iomuxc { 200 pinctrl_gpio1: gpio1-grp { 201 fsl,pins = < 202 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */ 203 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */ 204 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */ 205 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */ 206 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */ 207 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */ 208 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */ 209 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */ 210 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */ 211 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */ 212 >; 213 }; 214 215 pinctrl_gpio2: gpio2-grp { /* Camera */ 216 fsl,pins = < 217 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */ 218 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */ 219 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */ 220 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */ 221 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */ 222 >; 223 }; 224 225 pinctrl_gpio3: gpio3-grp { /* CAN2 */ 226 fsl,pins = < 227 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */ 228 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */ 229 >; 230 }; 231 232 pinctrl_gpio4: gpio4-grp { 233 fsl,pins = < 234 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */ 235 >; 236 }; 237 238 pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */ 239 fsl,pins = < 240 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */ 241 >; 242 }; 243 244 pinctrl_gpio6: gpio6-grp { /* Wifi pins */ 245 fsl,pins = < 246 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */ 247 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */ 248 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */ 249 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */ 250 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */ 251 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */ 252 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */ 253 >; 254 }; 255 256 pinctrl_can_int: canint-grp { 257 fsl,pins = < 258 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 /* SODIMM 73 */ 259 >; 260 }; 261 262 pinctrl_enet2: enet2-grp { 263 fsl,pins = < 264 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 265 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 266 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 267 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 268 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 269 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 270 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 271 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 272 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 273 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 274 >; 275 }; 276 277 pinctrl_ecspi1_cs: ecspi1-cs-grp { 278 fsl,pins = < 279 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0 280 >; 281 }; 282 283 pinctrl_ecspi1: ecspi1-grp { 284 fsl,pins = < 285 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 286 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 287 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 288 >; 289 }; 290 291 pinctrl_flexcan2: flexcan2-grp { 292 fsl,pins = < 293 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 294 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 295 >; 296 }; 297 298 pinctrl_gpio_bl_on: gpio-bl-on-grp { 299 fsl,pins = < 300 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0 301 >; 302 }; 303 304 pinctrl_gpmi_nand: gpmi-nand-grp { 305 fsl,pins = < 306 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 307 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 308 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 309 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 310 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 311 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 312 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 313 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 314 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 315 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 316 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 317 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 318 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 319 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 320 >; 321 }; 322 323 pinctrl_i2c1: i2c1-grp { 324 fsl,pins = < 325 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 326 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 327 >; 328 }; 329 330 pinctrl_i2c1_gpio: i2c1-gpio-grp { 331 fsl,pins = < 332 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 333 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 334 >; 335 }; 336 337 pinctrl_i2c2: i2c2-grp { 338 fsl,pins = < 339 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 340 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 341 >; 342 }; 343 344 pinctrl_i2c2_gpio: i2c2-gpio-grp { 345 fsl,pins = < 346 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 347 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 348 >; 349 }; 350 351 pinctrl_lcdif_dat: lcdif-dat-grp { 352 fsl,pins = < 353 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 354 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 355 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 356 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 357 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 358 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 359 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 360 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 361 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 362 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 363 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 364 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 365 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 366 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 367 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 368 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 369 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 370 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 371 >; 372 }; 373 374 pinctrl_lcdif_ctrl: lcdif-ctrl-grp { 375 fsl,pins = < 376 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 377 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 378 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 379 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 380 >; 381 }; 382 383 pinctrl_pwm4: pwm4-grp { 384 fsl,pins = < 385 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 386 >; 387 }; 388 389 pinctrl_pwm5: pwm5-grp { 390 fsl,pins = < 391 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 392 >; 393 }; 394 395 pinctrl_pwm6: pwm6-grp { 396 fsl,pins = < 397 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 398 >; 399 }; 400 401 pinctrl_pwm7: pwm7-grp { 402 fsl,pins = < 403 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 404 >; 405 }; 406 407 pinctrl_uart1: uart1-grp { 408 fsl,pins = < 409 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 410 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 411 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 412 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 413 >; 414 }; 415 416 pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ 417 fsl,pins = < 418 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */ 419 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */ 420 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */ 421 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */ 422 >; 423 }; 424 425 pinctrl_uart2: uart2-grp { 426 fsl,pins = < 427 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 428 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 429 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 430 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 431 >; 432 }; 433 pinctrl_uart5: uart5-grp { 434 fsl,pins = < 435 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 436 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 437 >; 438 }; 439 440 pinctrl_usbh_reg: gpio-usbh-reg { 441 fsl,pins = < 442 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */ 443 >; 444 }; 445 446 pinctrl_usdhc1: usdhc1-grp { 447 fsl,pins = < 448 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 449 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 450 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 451 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 452 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 453 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 454 >; 455 }; 456 457 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { 458 fsl,pins = < 459 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 460 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 461 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 462 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 463 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 464 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 465 >; 466 }; 467 468 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 469 fsl,pins = < 470 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 471 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 472 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 473 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 474 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 475 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 476 >; 477 }; 478 479 pinctrl_usdhc2: usdhc2-grp { 480 fsl,pins = < 481 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 482 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 483 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 484 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 485 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 486 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059 487 >; 488 }; 489}; 490 491&iomuxc_snvs { 492 pinctrl_snvs_gpio1: snvs-gpio1-grp { 493 fsl,pins = < 494 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */ 495 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */ 496 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */ 497 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */ 498 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */ 499 >; 500 }; 501 502 pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */ 503 fsl,pins = < 504 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */ 505 >; 506 }; 507 508 pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ 509 fsl,pins = < 510 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */ 511 >; 512 }; 513 514 pinctrl_snvs_ad7879_int: snvs-ad7879-int { /* TOUCH Interrupt */ 515 fsl,pins = < 516 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 517 >; 518 }; 519 520 pinctrl_snvs_reg_sd: snvs-reg-sd-grp { 521 fsl,pins = < 522 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0 523 >; 524 }; 525 526 pinctrl_snvs_usbc_det: snvs-usbc-det-grp { 527 fsl,pins = < 528 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 529 >; 530 }; 531 532 pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { 533 fsl,pins = < 534 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0 535 >; 536 }; 537 538 pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { 539 fsl,pins = < 540 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */ 541 >; 542 }; 543 544 pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { 545 fsl,pins = < 546 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 547 >; 548 }; 549}; 550 551