1*c4d1c905SHuang Rui /* 2*c4d1c905SHuang Rui * Copyright 2021 Advanced Micro Devices, Inc. 3*c4d1c905SHuang Rui * 4*c4d1c905SHuang Rui * Permission is hereby granted, free of charge, to any person obtaining a 5*c4d1c905SHuang Rui * copy of this software and associated documentation files (the "Software"), 6*c4d1c905SHuang Rui * to deal in the Software without restriction, including without limitation 7*c4d1c905SHuang Rui * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*c4d1c905SHuang Rui * and/or sell copies of the Software, and to permit persons to whom the 9*c4d1c905SHuang Rui * Software is furnished to do so, subject to the following conditions: 10*c4d1c905SHuang Rui * 11*c4d1c905SHuang Rui * The above copyright notice and this permission notice shall be included in 12*c4d1c905SHuang Rui * all copies or substantial portions of the Software. 13*c4d1c905SHuang Rui * 14*c4d1c905SHuang Rui * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*c4d1c905SHuang Rui * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*c4d1c905SHuang Rui * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*c4d1c905SHuang Rui * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*c4d1c905SHuang Rui * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*c4d1c905SHuang Rui * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*c4d1c905SHuang Rui * OTHER DEALINGS IN THE SOFTWARE. 21*c4d1c905SHuang Rui * 22*c4d1c905SHuang Rui */ 23*c4d1c905SHuang Rui #ifndef _hdp_5_2_1_SH_MASK_HEADER 24*c4d1c905SHuang Rui #define _hdp_5_2_1_SH_MASK_HEADER 25*c4d1c905SHuang Rui 26*c4d1c905SHuang Rui 27*c4d1c905SHuang Rui // addressBlock: hdp_hdpdec 28*c4d1c905SHuang Rui //HDP_MMHUB_TLVL 29*c4d1c905SHuang Rui #define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0 30*c4d1c905SHuang Rui #define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4 31*c4d1c905SHuang Rui #define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8 32*c4d1c905SHuang Rui #define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc 33*c4d1c905SHuang Rui #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10 34*c4d1c905SHuang Rui #define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x0000000FL 35*c4d1c905SHuang Rui #define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x000000F0L 36*c4d1c905SHuang Rui #define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000F00L 37*c4d1c905SHuang Rui #define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x0000F000L 38*c4d1c905SHuang Rui #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x000F0000L 39*c4d1c905SHuang Rui //HDP_MMHUB_UNITID 40*c4d1c905SHuang Rui #define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0 41*c4d1c905SHuang Rui #define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8 42*c4d1c905SHuang Rui #define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10 43*c4d1c905SHuang Rui #define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL 44*c4d1c905SHuang Rui #define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L 45*c4d1c905SHuang Rui #define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L 46*c4d1c905SHuang Rui //HDP_NONSURFACE_BASE 47*c4d1c905SHuang Rui #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0 48*c4d1c905SHuang Rui #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL 49*c4d1c905SHuang Rui //HDP_NONSURFACE_INFO 50*c4d1c905SHuang Rui #define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4 51*c4d1c905SHuang Rui #define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8 52*c4d1c905SHuang Rui #define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L 53*c4d1c905SHuang Rui #define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L 54*c4d1c905SHuang Rui //HDP_NONSURFACE_BASE_HI 55*c4d1c905SHuang Rui #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0 56*c4d1c905SHuang Rui #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL 57*c4d1c905SHuang Rui //HDP_SURFACE_WRITE_FLAGS 58*c4d1c905SHuang Rui #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT 0x0 59*c4d1c905SHuang Rui #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT 0x1 60*c4d1c905SHuang Rui #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK 0x00000001L 61*c4d1c905SHuang Rui #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK 0x00000002L 62*c4d1c905SHuang Rui //HDP_SURFACE_READ_FLAGS 63*c4d1c905SHuang Rui #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT 0x0 64*c4d1c905SHuang Rui #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT 0x1 65*c4d1c905SHuang Rui #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK 0x00000001L 66*c4d1c905SHuang Rui #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK 0x00000002L 67*c4d1c905SHuang Rui //HDP_SURFACE_WRITE_FLAGS_CLR 68*c4d1c905SHuang Rui #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT 0x0 69*c4d1c905SHuang Rui #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT 0x1 70*c4d1c905SHuang Rui #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK 0x00000001L 71*c4d1c905SHuang Rui #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK 0x00000002L 72*c4d1c905SHuang Rui //HDP_SURFACE_READ_FLAGS_CLR 73*c4d1c905SHuang Rui #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT 0x0 74*c4d1c905SHuang Rui #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT 0x1 75*c4d1c905SHuang Rui #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK 0x00000001L 76*c4d1c905SHuang Rui #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK 0x00000002L 77*c4d1c905SHuang Rui //HDP_NONSURF_FLAGS 78*c4d1c905SHuang Rui #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 79*c4d1c905SHuang Rui #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 80*c4d1c905SHuang Rui #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L 81*c4d1c905SHuang Rui #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L 82*c4d1c905SHuang Rui //HDP_NONSURF_FLAGS_CLR 83*c4d1c905SHuang Rui #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 84*c4d1c905SHuang Rui #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 85*c4d1c905SHuang Rui #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L 86*c4d1c905SHuang Rui #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L 87*c4d1c905SHuang Rui //HDP_HOST_PATH_CNTL 88*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 89*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb 90*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12 91*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 92*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 93*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16 94*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d 95*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L 96*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L 97*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L 98*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L 99*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L 100*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L 101*c4d1c905SHuang Rui #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L 102*c4d1c905SHuang Rui //HDP_SW_SEMAPHORE 103*c4d1c905SHuang Rui #define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 104*c4d1c905SHuang Rui #define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL 105*c4d1c905SHuang Rui //HDP_DEBUG0 106*c4d1c905SHuang Rui #define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 107*c4d1c905SHuang Rui #define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL 108*c4d1c905SHuang Rui //HDP_LAST_SURFACE_HIT 109*c4d1c905SHuang Rui #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 110*c4d1c905SHuang Rui #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L 111*c4d1c905SHuang Rui //HDP_OUTSTANDING_REQ 112*c4d1c905SHuang Rui #define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 113*c4d1c905SHuang Rui #define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 114*c4d1c905SHuang Rui #define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL 115*c4d1c905SHuang Rui #define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L 116*c4d1c905SHuang Rui //HDP_MISC_CNTL 117*c4d1c905SHuang Rui #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2 118*c4d1c905SHuang Rui #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 119*c4d1c905SHuang Rui #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT 0x8 120*c4d1c905SHuang Rui #define HDP_MISC_CNTL__EARLY_WRACK_MISSING_PROTECT_ENABLE__SHIFT 0x9 121*c4d1c905SHuang Rui #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb 122*c4d1c905SHuang Rui #define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe 123*c4d1c905SHuang Rui #define HDP_MISC_CNTL__NACK_ENABLE__SHIFT 0x13 124*c4d1c905SHuang Rui #define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT 0x14 125*c4d1c905SHuang Rui #define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 126*c4d1c905SHuang Rui #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT 0x16 127*c4d1c905SHuang Rui #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17 128*c4d1c905SHuang Rui #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18 129*c4d1c905SHuang Rui #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e 130*c4d1c905SHuang Rui #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL 131*c4d1c905SHuang Rui #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L 132*c4d1c905SHuang Rui #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK 0x00000100L 133*c4d1c905SHuang Rui #define HDP_MISC_CNTL__EARLY_WRACK_MISSING_PROTECT_ENABLE_MASK 0x00000200L 134*c4d1c905SHuang Rui #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L 135*c4d1c905SHuang Rui #define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK 0x0000C000L 136*c4d1c905SHuang Rui #define HDP_MISC_CNTL__NACK_ENABLE_MASK 0x00080000L 137*c4d1c905SHuang Rui #define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE_MASK 0x00100000L 138*c4d1c905SHuang Rui #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L 139*c4d1c905SHuang Rui #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK 0x00400000L 140*c4d1c905SHuang Rui #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L 141*c4d1c905SHuang Rui #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L 142*c4d1c905SHuang Rui #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L 143*c4d1c905SHuang Rui //HDP_MEM_POWER_CTRL 144*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN__SHIFT 0x0 145*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN__SHIFT 0x1 146*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN__SHIFT 0x2 147*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN__SHIFT 0x3 148*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS__SHIFT 0x4 149*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 150*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe 151*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT 0x10 152*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT 0x11 153*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT 0x12 154*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT 0x13 155*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14 156*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18 157*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0x1e 158*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN_MASK 0x00000001L 159*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK 0x00000002L 160*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK 0x00000004L 161*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK 0x00000008L 162*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS_MASK 0x00000070L 163*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L 164*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L 165*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 166*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 167*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK 0x00040000L 168*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK 0x00080000L 169*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK 0x00700000L 170*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L 171*c4d1c905SHuang Rui #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY_MASK 0xC0000000L 172*c4d1c905SHuang Rui //HDP_MMHUB_CNTL 173*c4d1c905SHuang Rui #define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0 174*c4d1c905SHuang Rui #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1 175*c4d1c905SHuang Rui #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2 176*c4d1c905SHuang Rui #define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L 177*c4d1c905SHuang Rui #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L 178*c4d1c905SHuang Rui #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L 179*c4d1c905SHuang Rui //HDP_VERSION 180*c4d1c905SHuang Rui #define HDP_VERSION__MINVER__SHIFT 0x0 181*c4d1c905SHuang Rui #define HDP_VERSION__MAJVER__SHIFT 0x8 182*c4d1c905SHuang Rui #define HDP_VERSION__REV__SHIFT 0x10 183*c4d1c905SHuang Rui #define HDP_VERSION__MINVER_MASK 0x000000FFL 184*c4d1c905SHuang Rui #define HDP_VERSION__MAJVER_MASK 0x0000FF00L 185*c4d1c905SHuang Rui #define HDP_VERSION__REV_MASK 0x00FF0000L 186*c4d1c905SHuang Rui //HDP_CLK_CNTL 187*c4d1c905SHuang Rui #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0 188*c4d1c905SHuang Rui #define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a 189*c4d1c905SHuang Rui #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1b 190*c4d1c905SHuang Rui #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c 191*c4d1c905SHuang Rui #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d 192*c4d1c905SHuang Rui #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e 193*c4d1c905SHuang Rui #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f 194*c4d1c905SHuang Rui #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL 195*c4d1c905SHuang Rui #define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L 196*c4d1c905SHuang Rui #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK 0x08000000L 197*c4d1c905SHuang Rui #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L 198*c4d1c905SHuang Rui #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L 199*c4d1c905SHuang Rui #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L 200*c4d1c905SHuang Rui #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L 201*c4d1c905SHuang Rui //HDP_MEMIO_CNTL 202*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 203*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 204*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 205*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 206*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 207*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 208*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe 209*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf 210*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 211*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 212*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L 213*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L 214*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL 215*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L 216*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L 217*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L 218*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L 219*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L 220*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L 221*c4d1c905SHuang Rui #define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L 222*c4d1c905SHuang Rui //HDP_MEMIO_ADDR 223*c4d1c905SHuang Rui #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 224*c4d1c905SHuang Rui #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL 225*c4d1c905SHuang Rui //HDP_MEMIO_STATUS 226*c4d1c905SHuang Rui #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 227*c4d1c905SHuang Rui #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 228*c4d1c905SHuang Rui #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 229*c4d1c905SHuang Rui #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 230*c4d1c905SHuang Rui #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L 231*c4d1c905SHuang Rui #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L 232*c4d1c905SHuang Rui #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L 233*c4d1c905SHuang Rui #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L 234*c4d1c905SHuang Rui //HDP_MEMIO_WR_DATA 235*c4d1c905SHuang Rui #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 236*c4d1c905SHuang Rui #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL 237*c4d1c905SHuang Rui //HDP_MEMIO_RD_DATA 238*c4d1c905SHuang Rui #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 239*c4d1c905SHuang Rui #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL 240*c4d1c905SHuang Rui //HDP_XDP_DIRECT2HDP_FIRST 241*c4d1c905SHuang Rui #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 242*c4d1c905SHuang Rui #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL 243*c4d1c905SHuang Rui //HDP_XDP_D2H_FLUSH 244*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 245*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 246*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 247*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb 248*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 249*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 250*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 251*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 252*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL 253*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L 254*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L 255*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L 256*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L 257*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L 258*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L 259*c4d1c905SHuang Rui #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L 260*c4d1c905SHuang Rui //HDP_XDP_D2H_BAR_UPDATE 261*c4d1c905SHuang Rui #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 262*c4d1c905SHuang Rui #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 263*c4d1c905SHuang Rui #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 264*c4d1c905SHuang Rui #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL 265*c4d1c905SHuang Rui #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L 266*c4d1c905SHuang Rui #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L 267*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_3 268*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 269*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL 270*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_4 271*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 272*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL 273*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_5 274*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 275*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL 276*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_6 277*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 278*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL 279*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_7 280*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 281*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL 282*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_8 283*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 284*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL 285*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_9 286*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 287*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL 288*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_10 289*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 290*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL 291*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_11 292*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 293*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL 294*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_12 295*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 296*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL 297*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_13 298*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 299*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL 300*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_14 301*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 302*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL 303*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_15 304*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 305*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL 306*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_16 307*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 308*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL 309*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_17 310*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 311*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL 312*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_18 313*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 314*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL 315*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_19 316*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 317*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL 318*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_20 319*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 320*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL 321*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_21 322*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 323*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL 324*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_22 325*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 326*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL 327*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_23 328*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 329*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL 330*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_24 331*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 332*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL 333*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_25 334*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 335*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL 336*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_26 337*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 338*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL 339*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_27 340*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 341*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL 342*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_28 343*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 344*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL 345*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_29 346*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 347*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL 348*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_30 349*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 350*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL 351*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_31 352*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 353*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL 354*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_32 355*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 356*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL 357*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_33 358*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 359*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL 360*c4d1c905SHuang Rui //HDP_XDP_D2H_RSVD_34 361*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 362*c4d1c905SHuang Rui #define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL 363*c4d1c905SHuang Rui //HDP_XDP_DIRECT2HDP_LAST 364*c4d1c905SHuang Rui #define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 365*c4d1c905SHuang Rui #define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL 366*c4d1c905SHuang Rui //HDP_XDP_P2P_BAR_CFG 367*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 368*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 369*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL 370*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L 371*c4d1c905SHuang Rui //HDP_XDP_P2P_MBX_OFFSET 372*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 373*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL 374*c4d1c905SHuang Rui //HDP_XDP_P2P_MBX_ADDR0 375*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 376*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3 377*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14 378*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18 379*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L 380*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L 381*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L 382*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L 383*c4d1c905SHuang Rui //HDP_XDP_P2P_MBX_ADDR1 384*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 385*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3 386*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14 387*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18 388*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L 389*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L 390*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L 391*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L 392*c4d1c905SHuang Rui //HDP_XDP_P2P_MBX_ADDR2 393*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 394*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3 395*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14 396*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18 397*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L 398*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L 399*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L 400*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L 401*c4d1c905SHuang Rui //HDP_XDP_P2P_MBX_ADDR3 402*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 403*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3 404*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14 405*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18 406*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L 407*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L 408*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L 409*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L 410*c4d1c905SHuang Rui //HDP_XDP_P2P_MBX_ADDR4 411*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 412*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3 413*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14 414*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18 415*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L 416*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L 417*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L 418*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L 419*c4d1c905SHuang Rui //HDP_XDP_P2P_MBX_ADDR5 420*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 421*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3 422*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14 423*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18 424*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L 425*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L 426*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L 427*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L 428*c4d1c905SHuang Rui //HDP_XDP_P2P_MBX_ADDR6 429*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 430*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3 431*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14 432*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18 433*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L 434*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L 435*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L 436*c4d1c905SHuang Rui #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L 437*c4d1c905SHuang Rui //HDP_XDP_HDP_MBX_MC_CFG 438*c4d1c905SHuang Rui #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0 439*c4d1c905SHuang Rui #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4 440*c4d1c905SHuang Rui #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8 441*c4d1c905SHuang Rui #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc 442*c4d1c905SHuang Rui #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd 443*c4d1c905SHuang Rui #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe 444*c4d1c905SHuang Rui #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL 445*c4d1c905SHuang Rui #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L 446*c4d1c905SHuang Rui #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L 447*c4d1c905SHuang Rui #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L 448*c4d1c905SHuang Rui #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L 449*c4d1c905SHuang Rui #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L 450*c4d1c905SHuang Rui //HDP_XDP_HDP_MC_CFG 451*c4d1c905SHuang Rui #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3 452*c4d1c905SHuang Rui #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4 453*c4d1c905SHuang Rui #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8 454*c4d1c905SHuang Rui #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc 455*c4d1c905SHuang Rui #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd 456*c4d1c905SHuang Rui #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe 457*c4d1c905SHuang Rui #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L 458*c4d1c905SHuang Rui #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L 459*c4d1c905SHuang Rui #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L 460*c4d1c905SHuang Rui #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L 461*c4d1c905SHuang Rui #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L 462*c4d1c905SHuang Rui #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L 463*c4d1c905SHuang Rui //HDP_XDP_HST_CFG 464*c4d1c905SHuang Rui #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 465*c4d1c905SHuang Rui #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 466*c4d1c905SHuang Rui #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3 467*c4d1c905SHuang Rui #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4 468*c4d1c905SHuang Rui #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5 469*c4d1c905SHuang Rui #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L 470*c4d1c905SHuang Rui #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L 471*c4d1c905SHuang Rui #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L 472*c4d1c905SHuang Rui #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L 473*c4d1c905SHuang Rui #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L 474*c4d1c905SHuang Rui //HDP_XDP_HDP_IPH_CFG 475*c4d1c905SHuang Rui #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc 476*c4d1c905SHuang Rui #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd 477*c4d1c905SHuang Rui #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L 478*c4d1c905SHuang Rui #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L 479*c4d1c905SHuang Rui //HDP_XDP_P2P_BAR0 480*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 481*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 482*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 483*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL 484*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L 485*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L 486*c4d1c905SHuang Rui //HDP_XDP_P2P_BAR1 487*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 488*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 489*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 490*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL 491*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L 492*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L 493*c4d1c905SHuang Rui //HDP_XDP_P2P_BAR2 494*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 495*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 496*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 497*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL 498*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L 499*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L 500*c4d1c905SHuang Rui //HDP_XDP_P2P_BAR3 501*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 502*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 503*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 504*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL 505*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L 506*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L 507*c4d1c905SHuang Rui //HDP_XDP_P2P_BAR4 508*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 509*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 510*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 511*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL 512*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L 513*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L 514*c4d1c905SHuang Rui //HDP_XDP_P2P_BAR5 515*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 516*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 517*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 518*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL 519*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L 520*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L 521*c4d1c905SHuang Rui //HDP_XDP_P2P_BAR6 522*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 523*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 524*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 525*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL 526*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L 527*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L 528*c4d1c905SHuang Rui //HDP_XDP_P2P_BAR7 529*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 530*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 531*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 532*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL 533*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L 534*c4d1c905SHuang Rui #define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L 535*c4d1c905SHuang Rui //HDP_XDP_FLUSH_ARMED_STS 536*c4d1c905SHuang Rui #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 537*c4d1c905SHuang Rui #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL 538*c4d1c905SHuang Rui //HDP_XDP_FLUSH_CNTR0_STS 539*c4d1c905SHuang Rui #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 540*c4d1c905SHuang Rui #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL 541*c4d1c905SHuang Rui //HDP_XDP_BUSY_STS 542*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_0__SHIFT 0x0 543*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_1__SHIFT 0x1 544*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_2__SHIFT 0x2 545*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_3__SHIFT 0x3 546*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_4__SHIFT 0x4 547*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_5__SHIFT 0x5 548*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_6__SHIFT 0x6 549*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_7__SHIFT 0x7 550*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_8__SHIFT 0x8 551*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_9__SHIFT 0x9 552*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_10__SHIFT 0xa 553*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_11__SHIFT 0xb 554*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_12__SHIFT 0xc 555*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_13__SHIFT 0xd 556*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_14__SHIFT 0xe 557*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_15__SHIFT 0xf 558*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_16__SHIFT 0x10 559*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_17__SHIFT 0x11 560*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_18__SHIFT 0x12 561*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_19__SHIFT 0x13 562*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_20__SHIFT 0x14 563*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_21__SHIFT 0x15 564*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_22__SHIFT 0x16 565*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_23__SHIFT 0x17 566*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__Z_FENCE_BIT__SHIFT 0x18 567*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_0_MASK 0x00000001L 568*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_1_MASK 0x00000002L 569*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_2_MASK 0x00000004L 570*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_3_MASK 0x00000008L 571*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_4_MASK 0x00000010L 572*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_5_MASK 0x00000020L 573*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_6_MASK 0x00000040L 574*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_7_MASK 0x00000080L 575*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_8_MASK 0x00000100L 576*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_9_MASK 0x00000200L 577*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_10_MASK 0x00000400L 578*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_11_MASK 0x00000800L 579*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_12_MASK 0x00001000L 580*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_13_MASK 0x00002000L 581*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_14_MASK 0x00004000L 582*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_15_MASK 0x00008000L 583*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_16_MASK 0x00010000L 584*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_17_MASK 0x00020000L 585*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_18_MASK 0x00040000L 586*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_19_MASK 0x00080000L 587*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_20_MASK 0x00100000L 588*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_21_MASK 0x00200000L 589*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_22_MASK 0x00400000L 590*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__BUSY_BITS_23_MASK 0x00800000L 591*c4d1c905SHuang Rui #define HDP_XDP_BUSY_STS__Z_FENCE_BIT_MASK 0x01000000L 592*c4d1c905SHuang Rui //HDP_XDP_STICKY 593*c4d1c905SHuang Rui #define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 594*c4d1c905SHuang Rui #define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 595*c4d1c905SHuang Rui #define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL 596*c4d1c905SHuang Rui #define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L 597*c4d1c905SHuang Rui //HDP_XDP_CHKN 598*c4d1c905SHuang Rui #define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 599*c4d1c905SHuang Rui #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 600*c4d1c905SHuang Rui #define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 601*c4d1c905SHuang Rui #define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 602*c4d1c905SHuang Rui #define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL 603*c4d1c905SHuang Rui #define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L 604*c4d1c905SHuang Rui #define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L 605*c4d1c905SHuang Rui #define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L 606*c4d1c905SHuang Rui //HDP_XDP_BARS_ADDR_39_36 607*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 608*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 609*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 610*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc 611*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 612*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 613*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 614*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c 615*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL 616*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L 617*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L 618*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L 619*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L 620*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L 621*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L 622*c4d1c905SHuang Rui #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L 623*c4d1c905SHuang Rui //HDP_XDP_MC_VM_FB_LOCATION_BASE 624*c4d1c905SHuang Rui #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 625*c4d1c905SHuang Rui #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL 626*c4d1c905SHuang Rui //HDP_XDP_GPU_IOV_VIOLATION_LOG 627*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 628*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 629*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 630*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 631*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 632*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 633*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 634*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 635*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 636*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L 637*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 638*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 639*c4d1c905SHuang Rui //HDP_XDP_GPU_IOV_VIOLATION_LOG2 640*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 641*c4d1c905SHuang Rui #define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL 642*c4d1c905SHuang Rui //HDP_XDP_MMHUB_ERROR 643*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1 644*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2 645*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3 646*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED__SHIFT 0x4 647*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5 648*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6 649*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7 650*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9 651*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa 652*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb 653*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED__SHIFT 0xc 654*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd 655*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe 656*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf 657*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11 658*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12 659*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13 660*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15 661*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16 662*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17 663*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L 664*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L 665*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L 666*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED_MASK 0x00000010L 667*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L 668*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L 669*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L 670*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L 671*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L 672*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L 673*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED_MASK 0x00001000L 674*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L 675*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L 676*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L 677*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L 678*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L 679*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L 680*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L 681*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L 682*c4d1c905SHuang Rui #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L 683*c4d1c905SHuang Rui 684*c4d1c905SHuang Rui #endif 685