Home
last modified time | relevance | path

Searched +full:0 +full:x11000000 (Results 1 – 25 of 118) sorted by relevance

12345

/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dcpu.h10 #define DEVICE_NOT_AVAILABLE 0
13 #define EXYNOS4_ADDR_BASE 0x10000000
16 #define EXYNOS4_I2C_SPACING 0x10000
18 #define EXYNOS4_GPIO_PART3_BASE 0x03860000
19 #define EXYNOS4_PRO_ID 0x10000000
20 #define EXYNOS4_SYSREG_BASE 0x10010000
21 #define EXYNOS4_POWER_BASE 0x10020000
22 #define EXYNOS4_SWRESET 0x10020400
23 #define EXYNOS4_CLOCK_BASE 0x10030000
24 #define EXYNOS4_SYSTIMER_BASE 0x10050000
[all …]
/openbmc/u-boot/include/configs/
H A DP1022DS.h16 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
17 #define CONFIG_SPL_PAD_TO 0x20000
20 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
21 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
35 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
36 #define CONFIG_SPL_PAD_TO 0x20000
39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
61 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
64 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
[all …]
H A DP1010RDB.h19 #define CONFIG_SPL_TEXT_BASE 0xD0001000
20 #define CONFIG_SPL_PAD_TO 0x18000
23 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
24 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
37 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
42 #define CONFIG_SPL_TEXT_BASE 0xD0001000
43 #define CONFIG_SPL_PAD_TO 0x18000
46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
65 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
[all …]
H A Dp1_p2_rdb_pc.h16 #define __SW_BOOT_MASK 0x03
17 #define __SW_BOOT_NOR 0xe4
18 #define __SW_BOOT_SD 0x54
24 #define __SW_BOOT_MASK 0x03
25 #define __SW_BOOT_NOR 0xe0
26 #define __SW_BOOT_SD 0x50
35 #define __SW_BOOT_MASK 0x03
36 #define __SW_BOOT_NOR 0x5c
37 #define __SW_BOOT_SPI 0x1c
38 #define __SW_BOOT_SD 0x9c
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_2_3_default.h26 #define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000
27 #define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000
28 #define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000
32 #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
33 #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
34 #define mmPCIE_INDEX_DEFAULT 0x00000000
35 #define mmPCIE_DATA_DEFAULT 0x00000000
36 #define mmPCIE_INDEX2_DEFAULT 0x00000000
37 #define mmPCIE_DATA2_DEFAULT 0x00000000
38 #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
[all …]
H A Dnbio_7_0_default.h26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000
29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000
30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000
31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000
32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000
34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000
[all …]
/openbmc/u-boot/configs/
H A Dbubblegum_96_defconfig3 CONFIG_SYS_TEXT_BASE=0x11000000
H A DC29XPCIE_SPIFLASH_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
30 CONFIG_SF_DEFAULT_MODE=0
H A Dadp-ag101p_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
H A DC29XPCIE_SPIFLASH_SECBOOT_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
31 CONFIG_SF_DEFAULT_MODE=0
H A DBSC9131RDB_SPIFLASH_SYSCLK100_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
30 CONFIG_SF_DEFAULT_MODE=0
H A DBSC9131RDB_SPIFLASH_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
30 CONFIG_SF_DEFAULT_MODE=0
H A Dcontrolcenterd_36BIT_SDCARD_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
42 CONFIG_SF_DEFAULT_MODE=0
H A DP1010RDB-PB_SPIFLASH_SECBOOT_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
36 CONFIG_SF_DEFAULT_MODE=0
H A Dcontrolcenterd_36BIT_SDCARD_DEVELOP_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
42 CONFIG_SF_DEFAULT_MODE=0
H A DP1010RDB-PA_SPIFLASH_SECBOOT_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
36 CONFIG_SF_DEFAULT_MODE=0
H A DP1010RDB-PA_NAND_SECBOOT_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
36 CONFIG_SF_DEFAULT_MODE=0
H A DP1010RDB-PB_NAND_SECBOOT_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
36 CONFIG_SF_DEFAULT_MODE=0
H A DP1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
37 CONFIG_SF_DEFAULT_MODE=0
H A DUCP1020_SPIFLASH_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
44 CONFIG_SF_DEFAULT_MODE=0
H A DP1010RDB-PB_36BIT_NAND_SECBOOT_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
37 CONFIG_SF_DEFAULT_MODE=0
H A DP1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
37 CONFIG_SF_DEFAULT_MODE=0
H A DP1010RDB-PA_36BIT_NAND_SECBOOT_defconfig2 CONFIG_SYS_TEXT_BASE=0x11000000
37 CONFIG_SF_DEFAULT_MODE=0
/openbmc/linux/arch/mips/include/asm/sibyte/
H A Dbigsur.h19 #define LEDS_PHYS 0x100a0000
23 #define IDE_PHYS 0x100b0000
30 #define PCMCIA_PHYS 0x11000000
H A Dswarm.h18 #define SIBYTE_HAVE_PCMCIA 0
24 #define SIBYTE_HAVE_PCMCIA 0
25 #define SIBYTE_HAVE_IDE 0
30 #define LEDS_PHYS 0x100a0000
34 #define IDE_PHYS 0x100b0000
41 #define PCMCIA_PHYS 0x11000000

12345