Lines Matching +full:0 +full:x11000000
16 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
17 #define CONFIG_SPL_PAD_TO 0x20000
20 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
21 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
35 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
36 #define CONFIG_SPL_PAD_TO 0x20000
39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
61 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
64 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
65 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
70 #define CONFIG_SPL_TEXT_BASE 0xff800000
73 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
74 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
77 #define CONFIG_SPL_PAD_TO 0x20000
78 #define CONFIG_TPL_PAD_TO 0x20000
86 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
113 #define CONFIG_SYS_MEMTEST_START 0x00000000
114 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
116 #define CONFIG_SYS_CCSRBAR 0xffe00000
131 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
134 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
142 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
147 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
148 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
149 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
150 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
151 #define CONFIG_SYS_DDR_TIMING_3 0x00010000
152 #define CONFIG_SYS_DDR_TIMING_0 0x40110104
153 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
154 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
155 #define CONFIG_SYS_DDR_MODE_1 0x00441221
156 #define CONFIG_SYS_DDR_MODE_2 0x00000000
157 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100
158 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
159 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
160 #define CONFIG_SYS_DDR_CONTROL 0xc7000008
161 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041
162 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
163 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
164 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
165 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
170 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
171 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
172 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
175 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
178 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
179 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
180 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
181 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
182 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
183 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
189 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
191 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
198 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
229 #define CONFIG_SYS_NAND_BASE 0xff800000
231 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
268 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
270 #define PIXIS_BASE_PHYS 0xfffdf0000ull
276 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
279 #define PIXIS_LBMAP_MASK 0xF0
280 #define PIXIS_LBMAP_ALTBANK 0x20
281 #define PIXIS_SPD 0x07
282 #define PIXIS_SPD_SYSCLK_MASK 0x07
283 #define PIXIS_ELBC_SPI_MASK 0xc0
284 #define PIXIS_SPI 0x80
287 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
288 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
302 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
306 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
313 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
317 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
323 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
327 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
328 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
338 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
346 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
347 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
352 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
375 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
376 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
378 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
379 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
380 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
387 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
393 * Memory space is mapped 1-1, but I/O space must start from 0.
397 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
399 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
400 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
402 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
403 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
405 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
406 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
407 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
409 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
411 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
413 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
416 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
418 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
419 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
421 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
422 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
424 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
425 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
426 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
428 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
430 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
432 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
435 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
437 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
438 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
440 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
441 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
443 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
444 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
445 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
447 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
449 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
451 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
492 #define TSEC1_PHYIDX 0
493 #define TSEC2_PHYIDX 0
506 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
507 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
508 #define CONFIG_ENV_SECT_SIZE 0x10000
511 #define CONFIG_ENV_SIZE 0x2000
512 #define CONFIG_SYS_MMC_ENV_DEV 0
515 #define CONFIG_ENV_SIZE 0x2000
523 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
524 #define CONFIG_ENV_SIZE 0x2000
527 #define CONFIG_ENV_SIZE 0x2000
528 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
548 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
574 "netdev=eth0\0" \
575 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
576 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
582 "cmp.b $loadaddr $ubootaddr $filesize\0" \
583 "consoledev=ttyS0\0" \
584 "ramdiskaddr=2000000\0" \
585 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
586 "fdtaddr=1e00000\0" \
587 "fdtfile=p1022ds.dtb\0" \
588 "bdev=sda3\0" \
589 "hwconfig=esdhc;audclk:12\0"