Lines Matching +full:0 +full:x11000000
19 #define CONFIG_SPL_TEXT_BASE 0xD0001000
20 #define CONFIG_SPL_PAD_TO 0x18000
23 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
24 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
37 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
42 #define CONFIG_SPL_TEXT_BASE 0xD0001000
43 #define CONFIG_SPL_PAD_TO 0x18000
46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
65 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
67 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
68 #define CONFIG_SPL_RELOC_STACK 0x00100000
69 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
70 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
71 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
72 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
81 #define CONFIG_TPL_TEXT_BASE 0xD0001000
84 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
85 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
91 #define CONFIG_SPL_TEXT_BASE 0xff800000
94 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
95 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
98 #define CONFIG_SPL_PAD_TO 0x20000
99 #define CONFIG_TPL_PAD_TO 0x20000
107 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
111 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
135 * Memory space is mapped 1-1, but I/O space must start from 0.
139 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
141 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
142 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
144 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
145 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
147 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
148 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
149 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
150 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
152 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
154 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
163 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
165 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
166 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
168 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
169 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
171 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
172 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
173 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
174 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
176 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
178 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
204 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
205 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
211 #define SPD_EEPROM_ADDRESS 0x52
213 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
219 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
226 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
227 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
228 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
229 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
230 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
231 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
232 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
233 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
234 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
235 #define CONFIG_SYS_DDR_RCW_1 0x00000000
236 #define CONFIG_SYS_DDR_RCW_2 0x00000000
237 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
238 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
239 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
240 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
242 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
243 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
244 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
245 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
246 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
247 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
248 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
249 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
250 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
253 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
254 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
255 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
256 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
257 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
258 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
259 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
260 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
261 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
263 #define CONFIG_SYS_CCSRBAR 0xffe00000
274 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
275 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
276 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
279 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
280 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
281 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
282 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
290 #define CONFIG_SYS_FLASH_BASE 0xee000000
294 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
306 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
307 FTIM0_NOR_TEADC(0x5) | \
308 FTIM0_NOR_TEAHC(0x5)
309 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
310 FTIM1_NOR_TRAD_NOR(0x0f)
311 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
312 FTIM2_NOR_TCH(0x4) | \
313 FTIM2_NOR_TWP(0x1c)
314 #define CONFIG_SYS_NOR_FTIM3 0x0
329 #define CONFIG_SYS_NAND_BASE 0xff800000
331 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
371 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
372 FTIM0_NAND_TWP(0x0C) | \
373 FTIM0_NAND_TWCHT(0x04) | \
374 FTIM0_NAND_TWH(0x05)
375 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
376 FTIM1_NAND_TWBE(0x1d) | \
377 FTIM1_NAND_TRR(0x07) | \
378 FTIM1_NAND_TRP(0x0c)
379 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
380 FTIM2_NAND_TREH(0x05) | \
381 FTIM2_NAND_TWHRE(0x0f)
382 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
387 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
388 FTIM0_NAND_TWP(0x18) | \
389 FTIM0_NAND_TWCHT(0x07) | \
390 FTIM0_NAND_TWH(0x0a))
391 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
392 FTIM1_NAND_TWBE(0x39) | \
393 FTIM1_NAND_TRR(0x0e) | \
394 FTIM1_NAND_TRP(0x18))
395 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
396 FTIM2_NAND_TREH(0x0a) | \
397 FTIM2_NAND_TWHRE(0x1e))
398 #define CONFIG_SYS_NAND_FTIM3 0x0
437 #define CONFIG_SYS_CPLD_BASE 0xffb00000
440 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
450 #define CONFIG_SYS_CSOR3 0x0
452 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
453 FTIM0_GPCM_TEADC(0x0e) | \
454 FTIM0_GPCM_TEAHC(0x0e))
455 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
456 FTIM1_GPCM_TRAD(0x1f))
457 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
458 FTIM2_GPCM_TCH(0x8) | \
459 FTIM2_GPCM_TWP(0x1f))
460 #define CONFIG_SYS_CS3_FTIM3 0x0
476 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
477 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
491 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
495 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
502 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
506 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
512 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
516 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
517 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
526 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
534 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
535 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
541 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
542 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
544 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
545 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
546 #define I2C_PCA9557_ADDR1 0x18
547 #define I2C_PCA9557_ADDR2 0x19
548 #define I2C_PCA9557_BUS_NUM 0
557 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
558 #define CONFIG_SYS_EEPROM_BUS_NUM 0
568 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
588 #define TSEC2_PHY_ADDR 0
595 #define TSEC1_PHYIDX 0
596 #define TSEC2_PHYIDX 0
597 #define TSEC3_PHYIDX 0
644 #define CONFIG_SYS_MMC_ENV_DEV 0
645 #define CONFIG_ENV_SIZE 0x2000
647 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
648 #define CONFIG_ENV_SECT_SIZE 0x10000
649 #define CONFIG_ENV_SIZE 0x2000
652 #define CONFIG_ENV_SIZE 0x2000
665 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
666 #define CONFIG_ENV_SIZE 0x2000
669 #define CONFIG_ENV_SIZE 0x2000
670 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
685 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
717 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
718 "netdev=eth0\0" \
719 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
720 "loadaddr=1000000\0" \
721 "consoledev=ttyS0\0" \
722 "ramdiskaddr=2000000\0" \
723 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
724 "fdtaddr=1e00000\0" \
725 "fdtfile=p1010rdb.dtb\0" \
726 "bdev=sda1\0" \
727 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
728 "othbootargs=ramdisk_size=600000\0" \
732 "fatload usb 0:2 $loadaddr $bootfile;" \
733 "fatload usb 0:2 $fdtaddr $fdtfile;" \
734 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
735 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
739 "ext2load usb 0:4 $loadaddr $bootfile;" \
740 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
741 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
742 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
747 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
748 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
749 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
750 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
751 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
752 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
756 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
757 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
758 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
759 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
760 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
761 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
762 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
763 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
764 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
765 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"