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/openbmc/qemu/hw/misc/
H A Dallwinner-h3-ccu.c30 REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */
31 REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */
32 REG_PLL_VIDEO = 0x0010, /* PLL Video Control */
33 REG_PLL_VE = 0x0018, /* PLL VE Control */
34 REG_PLL_DDR = 0x0020, /* PLL DDR Control */
35 REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */
36 REG_PLL_GPU = 0x0038, /* PLL GPU Control */
37 REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */
38 REG_PLL_DE = 0x0048, /* PLL Display Engine Control */
39 REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/uw-imap/uw-imap/
H A D0001-Support-OpenSSL-1.1.patch28 +#if OPENSSL_VERSION_NUMBER >= 0x10100000
31 + X509_VERIFY_PARAM_set1_host(param, host, 0);
41 if (SSL_write (stream->con,"",0) < 0)
44 +#if OPENSSL_VERSION_NUMBER < 0x10100000
60 +#if OPENSSL_VERSION_NUMBER < 0x10100000
H A Duw-imap-newer-tls.patch10 +#if OPENSSL_VERSION_NUMBER >= 0x10100000
17 SSL_CTX_set_options (stream->context,0);
22 +#if OPENSSL_VERSION_NUMBER >= 0x10100000
/openbmc/openbmc/meta-security/meta-tpm/recipes-tpm2/tpm2-tss-engine/files/
H A D0002-Fix-mismatch-of-OpenSSL-function-signatures-that-cau.patch37 #endif /* OPENSSL_VERSION_NUMBER < 0x10100000 */
53 return 0;
59 #endif /* OPENSSL_VERSION_NUMBER < 0x10100000 */
75 return 0;
77 2.43.0
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dmediatek,mt7628-eth.txt13 reg = <0x10100000 0x10000
14 0x10110000 0x8000>;
/openbmc/u-boot/configs/
H A Dbcm7260_defconfig3 CONFIG_SYS_TEXT_BASE=0x10100000
/openbmc/u-boot/include/configs/
H A Dbcm7260.h13 #define CONFIG_SYS_NS16550_COM1 0xf040c000
15 #define CONFIG_SYS_TEXT_BASE 0x10100000
16 #define CONFIG_SYS_INIT_RAM_ADDR 0x10200000
22 #define BCMSTB_SDHCI_BASE 0xf0200300
23 #define BCMSTB_TIMER_LOW 0xf0412008
24 #define BCMSTB_TIMER_HIGH 0xf041200c
25 #define BCMSTB_TIMER_FREQUENCY 0xf0412020
26 #define BCMSTB_HIF_MSPI_BASE 0xf0203c00
27 #define BCMSTB_BSPI_BASE 0xf0203a00
28 #define BCMSTB_HIF_SPI_INTR2 0xf0201a00
[all …]
H A Dtegra20-common.h19 #define CONFIG_STACKBASE 0x03800000 /* 56MB */
36 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
49 #define CONFIG_LOADADDR 0x01000000
51 "scriptaddr=0x10000000\0" \
52 "pxefile_addr_r=0x10100000\0" \
53 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
54 "fdt_addr_r=0x03000000\0" \
55 "ramdisk_addr_r=0x03100000\0"
58 #define CONFIG_SPL_TEXT_BASE 0x00108000
59 #define CONFIG_SYS_SPL_MALLOC_START 0x00090000
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_4_0_smn.h26 // base address: 0x10100000
27 #define smnBIFL_RAS_CENTRAL_STATUS 0x10139040
29 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
30 #define smnCPM_CONTROL 0x11180460
31 #define smnPCIE_CNTL2 0x11180070
32 #define smnPCIE_CI_CNTL 0x11180080
34 #define smnPCIE_PERF_COUNT_CNTL 0x11180200
35 #define smnPCIE_PERF_CNTL_TXCLK1 0x11180204
36 #define smnPCIE_PERF_COUNT0_TXCLK1 0x11180208
37 #define smnPCIE_PERF_COUNT1_TXCLK1 0x1118020c
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Darm-realview-eb-11mp-ctrevb.dts38 reg = <0x10101000 0x1000>,
39 <0x10100100 0x100>;
43 reg = <0x10102000 0x1000>;
47 reg = <0x10100000 0x100>;
51 reg = <0x10100600 0x20>;
55 reg = <0x10100620 0x20>;
/openbmc/linux/arch/mips/boot/dts/mscc/
H A Dluton.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x60000000 0x20000000>;
56 reg = <0x10000000 0x2c>;
61 reg = <0x10000084 0x70>;
69 pinctrl-0 = <&uart_pins>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dstarfive,jh7110-usb.yaml68 "^usb@[0-9a-f]+$":
88 ranges = <0x0 0x10100000 0x100000>;
91 starfive,stg-syscon = <&stg_syscon 0x4>;
105 usb@0 {
107 reg = <0x0 0x10000>,
108 <0x10000 0x10000>,
109 <0x20000 0x10000>;
/openbmc/linux/arch/arm/mach-nomadik/
H A Dcpu-8815.c17 #define NOMADIK_FSMC_BASE 0x10100000 /* FSMC registers */
18 #define NOMADIK_SDRAMC_BASE 0x10110000 /* SDRAM Controller */
19 #define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */
20 #define NOMADIK_MDIF_BASE 0x10120000 /* MDIF */
21 #define NOMADIK_DMA0_BASE 0x10130000 /* DMA0 Controller */
22 #define NOMADIK_IC_BASE 0x10140000 /* Vectored Irq Controller */
23 #define NOMADIK_DMA1_BASE 0x10150000 /* DMA1 Controller */
24 #define NOMADIK_USB_BASE 0x10170000 /* USB-OTG conf reg base */
25 #define NOMADIK_CRYP_BASE 0x10180000 /* Crypto processor */
26 #define NOMADIK_SHA1_BASE 0x10190000 /* SHA-1 Processor */
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dserdes.c19 #define FSL_SRDSCR0_OFFS 0x0
20 #define FSL_SRDSCR0_DPP_1V2 0x00008800
21 #define FSL_SRDSCR0_TXEQA_MASK 0x00007000
22 #define FSL_SRDSCR0_TXEQA_SATA 0x00001000
23 #define FSL_SRDSCR0_TXEQE_MASK 0x00000700
24 #define FSL_SRDSCR0_TXEQE_SATA 0x00000100
25 #define FSL_SRDSCR1_OFFS 0x4
26 #define FSL_SRDSCR1_PLLBW 0x00000040
27 #define FSL_SRDSCR2_OFFS 0x8
28 #define FSL_SRDSCR2_VDD_1V2 0x00800000
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dmt7628a.dtsi10 #size-cells = <0>;
12 cpu@0 {
15 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>;
39 sysc: system-controller@0 {
41 reg = <0x0 0x100>;
47 offset = <0x34>;
48 mask = <0x1>;
[all …]
H A Dmscc,luton.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
30 #clock-cells = <0>;
35 #clock-cells = <0>;
43 ranges = <0 0x60000000 0x10200000>;
46 pinctrl-0 = <&uart_pins>;
50 reg = <0x10100000 0x20>;
60 reg = <0x70068 0x68>;
63 gpio-ranges = <&gpio 0 0 32>;
[all …]
/openbmc/linux/arch/mips/include/asm/mach-ralink/
H A Drt3883.h15 #define RT3883_SDRAM_BASE 0x00000000
16 #define RT3883_SYSC_BASE IOMEM(0x10000000)
17 #define RT3883_TIMER_BASE 0x10000100
18 #define RT3883_INTC_BASE 0x10000200
19 #define RT3883_MEMC_BASE 0x10000300
20 #define RT3883_UART0_BASE 0x10000500
21 #define RT3883_PIO_BASE 0x10000600
22 #define RT3883_FSCC_BASE 0x10000700
23 #define RT3883_NANDC_BASE 0x10000810
24 #define RT3883_I2C_BASE 0x10000900
[all …]
/openbmc/linux/arch/arm64/boot/dts/realtek/
H A Drtd129x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000001f000;
9 /memreserve/ 0x000000000001f000 0x00000000000e1000;
10 /memreserve/ 0x0000000001b00000 0x00000000004be000;
26 reg = <0x1f000 0x1000>;
30 reg = <0x1ffe000 0x4000>;
34 reg = <0x10100000 0xf00000>;
47 #clock-cells = <0>;
55 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
57 <0x80000000 0x80000000 0x80000000>;
61 reg = <0x98000000 0x200000>;
[all …]
H A Drtd139x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000002f000;
9 /memreserve/ 0x000000000002f000 0x00000000000d1000;
25 reg = <0x2f000 0x1000>;
29 reg = <0x1ffe000 0x4000>;
33 reg = <0x10100000 0xf00000>;
46 #clock-cells = <0>;
54 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
55 <0x98000000 0x98000000 0x68000000>;
59 reg = <0x98000000 0x200000>;
62 ranges = <0x0 0x98000000 0x200000>;
[all …]
H A Drtd16xx.dtsi23 reg = <0x2f000 0x1000>;
27 reg = <0x1ffe000 0x4000>;
31 reg = <0x10100000 0xf00000>;
38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
51 reg = <0x100>;
59 reg = <0x200>;
67 reg = <0x300>;
75 reg = <0x400>;
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/liboauth/liboauth/
H A D0001-Support-OpenSSL-1.1.0.patch4 Subject: [PATCH] Support OpenSSL 1.1.0
22 +#if OPENSSL_VERSION_NUMBER < 0x10100000
33 unsigned int len=0;
58 sig[len] = '\0';
104 size_t len=0;
116 while (!feof(F) && (len=fread(fb,sizeof(char),BUFSIZ, F))>0) {
121 len=0;
133 size_t len=0;
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dcpu.h10 #define DEVICE_NOT_AVAILABLE 0
13 #define EXYNOS4_ADDR_BASE 0x10000000
16 #define EXYNOS4_I2C_SPACING 0x10000
18 #define EXYNOS4_GPIO_PART3_BASE 0x03860000
19 #define EXYNOS4_PRO_ID 0x10000000
20 #define EXYNOS4_SYSREG_BASE 0x10010000
21 #define EXYNOS4_POWER_BASE 0x10020000
22 #define EXYNOS4_SWRESET 0x10020400
23 #define EXYNOS4_CLOCK_BASE 0x10030000
24 #define EXYNOS4_SYSTIMER_BASE 0x10050000
[all …]
/openbmc/linux/drivers/staging/rtl8712/
H A Drtl871x_pwrctrl.c23 #define RTL8712_SDIO_LOCAL_BASE 0X10100000
24 #define SDIO_HCPWM (RTL8712_SDIO_LOCAL_BASE + 0x0081)
32 if (pwrpriv->rpwm_retry == 0) in r8712_set_rpwm()
52 pwrpriv->rpwm_retry = 0; in r8712_set_rpwm()
54 r8712_write8(padapter, 0x1025FE58, rpwm); in r8712_set_rpwm()
55 pwrpriv->tog += 0x80; in r8712_set_rpwm()
66 smart_ps = 0; in r8712_set_ps_mode()
92 if (pwrpriv->cpwm_tog == ((preportpwrstate->state) & 0x80)) in r8712_cpwm_int_hdl()
96 pwrpriv->cpwm = (preportpwrstate->state) & 0xf; in r8712_cpwm_int_hdl()
101 pwrpriv->cpwm_tog = (preportpwrstate->state) & 0x80; in r8712_cpwm_int_hdl()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h26 // base address: 0x0
27 … 0x0000 // duplicate
28 … 0x0002 // duplicate
29 … 0x0004 // duplicate
30 … 0x0006 // duplicate
31 … 0x0008 // duplicate
32 … 0x0009 // duplicate
33 … 0x000a // duplicate
34 … 0x000b // duplicate
35 … 0x000c // duplicate
[all …]
/openbmc/linux/arch/mips/ath25/
H A Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
29 #define AR2315_MISC_IRQ_UART0 0
43 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
44 #define AR2315_SPI_READ_SIZE 0x01000000
45 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
[all …]

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