Lines Matching +full:0 +full:x10100000

19 #define FSL_SRDSCR0_OFFS		0x0
20 #define FSL_SRDSCR0_DPP_1V2		0x00008800
21 #define FSL_SRDSCR0_TXEQA_MASK		0x00007000
22 #define FSL_SRDSCR0_TXEQA_SATA		0x00001000
23 #define FSL_SRDSCR0_TXEQE_MASK		0x00000700
24 #define FSL_SRDSCR0_TXEQE_SATA		0x00000100
25 #define FSL_SRDSCR1_OFFS		0x4
26 #define FSL_SRDSCR1_PLLBW		0x00000040
27 #define FSL_SRDSCR2_OFFS		0x8
28 #define FSL_SRDSCR2_VDD_1V2		0x00800000
29 #define FSL_SRDSCR2_SEIC_MASK		0x00001c1c
30 #define FSL_SRDSCR2_SEIC_SATA		0x00001414
31 #define FSL_SRDSCR2_SEIC_PEX		0x00001010
32 #define FSL_SRDSCR2_SEIC_SGMII		0x00000101
33 #define FSL_SRDSCR3_OFFS		0xc
34 #define FSL_SRDSCR3_KFR_SATA		0x10100000
35 #define FSL_SRDSCR3_KPH_SATA		0x04040000
36 #define FSL_SRDSCR3_SDFM_SATA_PEX	0x01010000
37 #define FSL_SRDSCR3_SDTXL_SATA		0x00000505
38 #define FSL_SRDSCR4_OFFS		0x10
39 #define FSL_SRDSCR4_PROT_SATA		0x00000808
40 #define FSL_SRDSCR4_PROT_PEX		0x00000101
41 #define FSL_SRDSCR4_PROT_SGMII		0x00000505
42 #define FSL_SRDSCR4_PLANE_X2		0x01000000
43 #define FSL_SRDSRSTCTL_OFFS		0x20
44 #define FSL_SRDSRSTCTL_RST		0x80000000
45 #define FSL_SRDSRSTCTL_SATA_RESET	0xf
54 		/* DPPE/DPPA = 0 */  in fsl_setup_serdes()
59 		/* VDD = 0 */  in fsl_setup_serdes()
138 		out_be32(regs + FSL_SRDSCR3_OFFS, 0);  in fsl_setup_serdes()