1daad67b5SFeifei Xu /*
2daad67b5SFeifei Xu  * Copyright (C) 2017  Advanced Micro Devices, Inc.
3daad67b5SFeifei Xu  *
4daad67b5SFeifei Xu  * Permission is hereby granted, free of charge, to any person obtaining a
5daad67b5SFeifei Xu  * copy of this software and associated documentation files (the "Software"),
6daad67b5SFeifei Xu  * to deal in the Software without restriction, including without limitation
7daad67b5SFeifei Xu  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8daad67b5SFeifei Xu  * and/or sell copies of the Software, and to permit persons to whom the
9daad67b5SFeifei Xu  * Software is furnished to do so, subject to the following conditions:
10daad67b5SFeifei Xu  *
11daad67b5SFeifei Xu  * The above copyright notice and this permission notice shall be included
12daad67b5SFeifei Xu  * in all copies or substantial portions of the Software.
13daad67b5SFeifei Xu  *
14daad67b5SFeifei Xu  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15daad67b5SFeifei Xu  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16daad67b5SFeifei Xu  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17daad67b5SFeifei Xu  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18daad67b5SFeifei Xu  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19daad67b5SFeifei Xu  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20daad67b5SFeifei Xu  */
21daad67b5SFeifei Xu #ifndef _nbif_6_1_OFFSET_HEADER
22daad67b5SFeifei Xu #define _nbif_6_1_OFFSET_HEADER
23daad67b5SFeifei Xu 
24daad67b5SFeifei Xu 
25daad67b5SFeifei Xu // addressBlock: bif_cfg_dev0_epf0_bifcfgdecp
26daad67b5SFeifei Xu // base address: 0x0
27daad67b5SFeifei Xu #define cfgVENDOR_ID                                                                                    0x0000 // duplicate
28daad67b5SFeifei Xu #define cfgDEVICE_ID                                                                                    0x0002 // duplicate
29daad67b5SFeifei Xu #define cfgCOMMAND                                                                                      0x0004 // duplicate
30daad67b5SFeifei Xu #define cfgSTATUS                                                                                       0x0006 // duplicate
31daad67b5SFeifei Xu #define cfgREVISION_ID                                                                                  0x0008 // duplicate
32daad67b5SFeifei Xu #define cfgPROG_INTERFACE                                                                               0x0009 // duplicate
33daad67b5SFeifei Xu #define cfgSUB_CLASS                                                                                    0x000a // duplicate
34daad67b5SFeifei Xu #define cfgBASE_CLASS                                                                                   0x000b // duplicate
35daad67b5SFeifei Xu #define cfgCACHE_LINE                                                                                   0x000c // duplicate
36daad67b5SFeifei Xu #define cfgLATENCY                                                                                      0x000d // duplicate
37daad67b5SFeifei Xu #define cfgHEADER                                                                                       0x000e // duplicate
38daad67b5SFeifei Xu #define cfgBIST                                                                                         0x000f // duplicate
39daad67b5SFeifei Xu #define cfgBASE_ADDR_1                                                                                  0x0010 // duplicate
40daad67b5SFeifei Xu #define cfgBASE_ADDR_2                                                                                  0x0014 // duplicate
41daad67b5SFeifei Xu #define cfgBASE_ADDR_3                                                                                  0x0018 // duplicate
42daad67b5SFeifei Xu #define cfgBASE_ADDR_4                                                                                  0x001c // duplicate
43daad67b5SFeifei Xu #define cfgBASE_ADDR_5                                                                                  0x0020 // duplicate
44daad67b5SFeifei Xu #define cfgBASE_ADDR_6                                                                                  0x0024 // duplicate
45daad67b5SFeifei Xu #define cfgADAPTER_ID                                                                                   0x002c // duplicate
46daad67b5SFeifei Xu #define cfgROM_BASE_ADDR                                                                                0x0030 // duplicate
47daad67b5SFeifei Xu #define cfgCAP_PTR                                                                                      0x0034 // duplicate
48daad67b5SFeifei Xu #define cfgINTERRUPT_LINE                                                                               0x003c // duplicate
49daad67b5SFeifei Xu #define cfgINTERRUPT_PIN                                                                                0x003d // duplicate
50daad67b5SFeifei Xu #define cfgMIN_GRANT                                                                                    0x003e // duplicate
51daad67b5SFeifei Xu #define cfgMAX_LATENCY                                                                                  0x003f // duplicate
52daad67b5SFeifei Xu #define cfgVENDOR_CAP_LIST                                                                              0x0048 // duplicate
53daad67b5SFeifei Xu #define cfgADAPTER_ID_W                                                                                 0x004c // duplicate
54daad67b5SFeifei Xu #define cfgPMI_CAP_LIST                                                                                 0x0050 // duplicate
55daad67b5SFeifei Xu #define cfgPMI_CAP                                                                                      0x0052 // duplicate
56daad67b5SFeifei Xu #define cfgPMI_STATUS_CNTL                                                                              0x0054 // duplicate
57daad67b5SFeifei Xu #define cfgPCIE_CAP_LIST                                                                                0x0064 // duplicate
58daad67b5SFeifei Xu #define cfgPCIE_CAP                                                                                     0x0066 // duplicate
59daad67b5SFeifei Xu #define cfgDEVICE_CAP                                                                                   0x0068 // duplicate
60daad67b5SFeifei Xu #define cfgDEVICE_CNTL                                                                                  0x006c // duplicate
61daad67b5SFeifei Xu #define cfgDEVICE_STATUS                                                                                0x006e // duplicate
62daad67b5SFeifei Xu #define cfgLINK_CAP                                                                                     0x0070 // duplicate
63daad67b5SFeifei Xu #define cfgLINK_CNTL                                                                                    0x0074 // duplicate
64daad67b5SFeifei Xu #define cfgLINK_STATUS                                                                                  0x0076 // duplicate
65daad67b5SFeifei Xu #define cfgDEVICE_CAP2                                                                                  0x0088 // duplicate
66daad67b5SFeifei Xu #define cfgDEVICE_CNTL2                                                                                 0x008c // duplicate
67daad67b5SFeifei Xu #define cfgDEVICE_STATUS2                                                                               0x008e // duplicate
68daad67b5SFeifei Xu #define cfgLINK_CAP2                                                                                    0x0090 // duplicate
69daad67b5SFeifei Xu #define cfgLINK_CNTL2                                                                                   0x0094 // duplicate
70daad67b5SFeifei Xu #define cfgLINK_STATUS2                                                                                 0x0096 // duplicate
71daad67b5SFeifei Xu #define cfgSLOT_CAP2                                                                                    0x0098 // duplicate
72daad67b5SFeifei Xu #define cfgSLOT_CNTL2                                                                                   0x009c // duplicate
73daad67b5SFeifei Xu #define cfgSLOT_STATUS2                                                                                 0x009e // duplicate
74daad67b5SFeifei Xu #define cfgMSI_CAP_LIST                                                                                 0x00a0 // duplicate
75daad67b5SFeifei Xu #define cfgMSI_MSG_CNTL                                                                                 0x00a2 // duplicate
76daad67b5SFeifei Xu #define cfgMSI_MSG_ADDR_LO                                                                              0x00a4 // duplicate
77daad67b5SFeifei Xu #define cfgMSI_MSG_ADDR_HI                                                                              0x00a8 // duplicate
78daad67b5SFeifei Xu #define cfgMSI_MSG_DATA                                                                                 0x00a8 // duplicate
79daad67b5SFeifei Xu #define cfgMSI_MSG_DATA_64                                                                              0x00ac // duplicate
80daad67b5SFeifei Xu #define cfgMSI_MASK                                                                                     0x00ac // duplicate
81daad67b5SFeifei Xu #define cfgMSI_PENDING                                                                                  0x00b0 // duplicate
82daad67b5SFeifei Xu #define cfgMSI_MASK_64                                                                                  0x00b0 // duplicate
83daad67b5SFeifei Xu #define cfgMSI_PENDING_64                                                                               0x00b4 // duplicate
84daad67b5SFeifei Xu #define cfgMSIX_CAP_LIST                                                                                0x00c0 // duplicate
85daad67b5SFeifei Xu #define cfgMSIX_MSG_CNTL                                                                                0x00c2 // duplicate
86daad67b5SFeifei Xu #define cfgMSIX_TABLE                                                                                   0x00c4 // duplicate
87daad67b5SFeifei Xu #define cfgMSIX_PBA                                                                                     0x00c8 // duplicate
88daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                            0x0100 // duplicate
89daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR                                                                     0x0104 // duplicate
90daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC1                                                                        0x0108 // duplicate
91daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC2                                                                        0x010c // duplicate
92daad67b5SFeifei Xu #define cfgPCIE_VC_ENH_CAP_LIST                                                                         0x0110 // duplicate
93daad67b5SFeifei Xu #define cfgPCIE_PORT_VC_CAP_REG1                                                                        0x0114 // duplicate
94daad67b5SFeifei Xu #define cfgPCIE_PORT_VC_CAP_REG2                                                                        0x0118 // duplicate
95daad67b5SFeifei Xu #define cfgPCIE_PORT_VC_CNTL                                                                            0x011c // duplicate
96daad67b5SFeifei Xu #define cfgPCIE_PORT_VC_STATUS                                                                          0x011e // duplicate
97daad67b5SFeifei Xu #define cfgPCIE_VC0_RESOURCE_CAP                                                                        0x0120 // duplicate
98daad67b5SFeifei Xu #define cfgPCIE_VC0_RESOURCE_CNTL                                                                       0x0124 // duplicate
99daad67b5SFeifei Xu #define cfgPCIE_VC0_RESOURCE_STATUS                                                                     0x012a // duplicate
100daad67b5SFeifei Xu #define cfgPCIE_VC1_RESOURCE_CAP                                                                        0x012c // duplicate
101daad67b5SFeifei Xu #define cfgPCIE_VC1_RESOURCE_CNTL                                                                       0x0130 // duplicate
102daad67b5SFeifei Xu #define cfgPCIE_VC1_RESOURCE_STATUS                                                                     0x0136 // duplicate
103daad67b5SFeifei Xu #define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                             0x0140 // duplicate
104daad67b5SFeifei Xu #define cfgPCIE_DEV_SERIAL_NUM_DW1                                                                      0x0144 // duplicate
105daad67b5SFeifei Xu #define cfgPCIE_DEV_SERIAL_NUM_DW2                                                                      0x0148 // duplicate
106daad67b5SFeifei Xu #define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                                0x0150 // duplicate
107daad67b5SFeifei Xu #define cfgPCIE_UNCORR_ERR_STATUS                                                                       0x0154 // duplicate
108daad67b5SFeifei Xu #define cfgPCIE_UNCORR_ERR_MASK                                                                         0x0158 // duplicate
109daad67b5SFeifei Xu #define cfgPCIE_UNCORR_ERR_SEVERITY                                                                     0x015c // duplicate
110daad67b5SFeifei Xu #define cfgPCIE_CORR_ERR_STATUS                                                                         0x0160 // duplicate
111daad67b5SFeifei Xu #define cfgPCIE_CORR_ERR_MASK                                                                           0x0164 // duplicate
112daad67b5SFeifei Xu #define cfgPCIE_ADV_ERR_CAP_CNTL                                                                        0x0168 // duplicate
113daad67b5SFeifei Xu #define cfgPCIE_HDR_LOG0                                                                                0x016c // duplicate
114daad67b5SFeifei Xu #define cfgPCIE_HDR_LOG1                                                                                0x0170 // duplicate
115daad67b5SFeifei Xu #define cfgPCIE_HDR_LOG2                                                                                0x0174 // duplicate
116daad67b5SFeifei Xu #define cfgPCIE_HDR_LOG3                                                                                0x0178 // duplicate
117daad67b5SFeifei Xu #define cfgPCIE_ROOT_ERR_CMD                                                                            0x017c // duplicate
118daad67b5SFeifei Xu #define cfgPCIE_ROOT_ERR_STATUS                                                                         0x0180 // duplicate
119daad67b5SFeifei Xu #define cfgPCIE_ERR_SRC_ID                                                                              0x0184 // duplicate
120daad67b5SFeifei Xu #define cfgPCIE_TLP_PREFIX_LOG0                                                                         0x0188 // duplicate
121daad67b5SFeifei Xu #define cfgPCIE_TLP_PREFIX_LOG1                                                                         0x018c // duplicate
122daad67b5SFeifei Xu #define cfgPCIE_TLP_PREFIX_LOG2                                                                         0x0190 // duplicate
123daad67b5SFeifei Xu #define cfgPCIE_TLP_PREFIX_LOG3                                                                         0x0194 // duplicate
124daad67b5SFeifei Xu #define cfgPCIE_BAR_ENH_CAP_LIST                                                                        0x0200 // duplicate
125daad67b5SFeifei Xu #define cfgPCIE_BAR1_CAP                                                                                0x0204 // duplicate
126daad67b5SFeifei Xu #define cfgPCIE_BAR1_CNTL                                                                               0x0208 // duplicate
127daad67b5SFeifei Xu #define cfgPCIE_BAR2_CAP                                                                                0x020c // duplicate
128daad67b5SFeifei Xu #define cfgPCIE_BAR2_CNTL                                                                               0x0210 // duplicate
129daad67b5SFeifei Xu #define cfgPCIE_BAR3_CAP                                                                                0x0214 // duplicate
130daad67b5SFeifei Xu #define cfgPCIE_BAR3_CNTL                                                                               0x0218 // duplicate
131daad67b5SFeifei Xu #define cfgPCIE_BAR4_CAP                                                                                0x021c // duplicate
132daad67b5SFeifei Xu #define cfgPCIE_BAR4_CNTL                                                                               0x0220 // duplicate
133daad67b5SFeifei Xu #define cfgPCIE_BAR5_CAP                                                                                0x0224 // duplicate
134daad67b5SFeifei Xu #define cfgPCIE_BAR5_CNTL                                                                               0x0228 // duplicate
135daad67b5SFeifei Xu #define cfgPCIE_BAR6_CAP                                                                                0x022c // duplicate
136daad67b5SFeifei Xu #define cfgPCIE_BAR6_CNTL                                                                               0x0230 // duplicate
137daad67b5SFeifei Xu #define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST                                                                 0x0240 // duplicate
138daad67b5SFeifei Xu #define cfgPCIE_PWR_BUDGET_DATA_SELECT                                                                  0x0244 // duplicate
139daad67b5SFeifei Xu #define cfgPCIE_PWR_BUDGET_DATA                                                                         0x0248 // duplicate
140daad67b5SFeifei Xu #define cfgPCIE_PWR_BUDGET_CAP                                                                          0x024c // duplicate
141daad67b5SFeifei Xu #define cfgPCIE_DPA_ENH_CAP_LIST                                                                        0x0250 // duplicate
142daad67b5SFeifei Xu #define cfgPCIE_DPA_CAP                                                                                 0x0254 // duplicate
143daad67b5SFeifei Xu #define cfgPCIE_DPA_LATENCY_INDICATOR                                                                   0x0258 // duplicate
144daad67b5SFeifei Xu #define cfgPCIE_DPA_STATUS                                                                              0x025c // duplicate
145daad67b5SFeifei Xu #define cfgPCIE_DPA_CNTL                                                                                0x025e // duplicate
146daad67b5SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0                                                                0x0260 // duplicate
147daad67b5SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1                                                                0x0261 // duplicate
148daad67b5SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2                                                                0x0262 // duplicate
149daad67b5SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3                                                                0x0263 // duplicate
150daad67b5SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4                                                                0x0264 // duplicate
151daad67b5SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5                                                                0x0265 // duplicate
152daad67b5SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6                                                                0x0266 // duplicate
153daad67b5SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7                                                                0x0267 // duplicate
154daad67b5SFeifei Xu #define cfgPCIE_SECONDARY_ENH_CAP_LIST                                                                  0x0270 // duplicate
155daad67b5SFeifei Xu #define cfgPCIE_LINK_CNTL3                                                                              0x0274 // duplicate
156daad67b5SFeifei Xu #define cfgPCIE_LANE_ERROR_STATUS                                                                       0x0278 // duplicate
157daad67b5SFeifei Xu #define cfgPCIE_LANE_0_EQUALIZATION_CNTL                                                                0x027c // duplicate
158daad67b5SFeifei Xu #define cfgPCIE_LANE_1_EQUALIZATION_CNTL                                                                0x027e // duplicate
159daad67b5SFeifei Xu #define cfgPCIE_LANE_2_EQUALIZATION_CNTL                                                                0x0280 // duplicate
160daad67b5SFeifei Xu #define cfgPCIE_LANE_3_EQUALIZATION_CNTL                                                                0x0282 // duplicate
161daad67b5SFeifei Xu #define cfgPCIE_LANE_4_EQUALIZATION_CNTL                                                                0x0284 // duplicate
162daad67b5SFeifei Xu #define cfgPCIE_LANE_5_EQUALIZATION_CNTL                                                                0x0286 // duplicate
163daad67b5SFeifei Xu #define cfgPCIE_LANE_6_EQUALIZATION_CNTL                                                                0x0288 // duplicate
164daad67b5SFeifei Xu #define cfgPCIE_LANE_7_EQUALIZATION_CNTL                                                                0x028a // duplicate
165daad67b5SFeifei Xu #define cfgPCIE_LANE_8_EQUALIZATION_CNTL                                                                0x028c // duplicate
166daad67b5SFeifei Xu #define cfgPCIE_LANE_9_EQUALIZATION_CNTL                                                                0x028e // duplicate
167daad67b5SFeifei Xu #define cfgPCIE_LANE_10_EQUALIZATION_CNTL                                                               0x0290 // duplicate
168daad67b5SFeifei Xu #define cfgPCIE_LANE_11_EQUALIZATION_CNTL                                                               0x0292 // duplicate
169daad67b5SFeifei Xu #define cfgPCIE_LANE_12_EQUALIZATION_CNTL                                                               0x0294 // duplicate
170daad67b5SFeifei Xu #define cfgPCIE_LANE_13_EQUALIZATION_CNTL                                                               0x0296 // duplicate
171daad67b5SFeifei Xu #define cfgPCIE_LANE_14_EQUALIZATION_CNTL                                                               0x0298 // duplicate
172daad67b5SFeifei Xu #define cfgPCIE_LANE_15_EQUALIZATION_CNTL                                                               0x029a // duplicate
173daad67b5SFeifei Xu #define cfgPCIE_ACS_ENH_CAP_LIST                                                                        0x02a0 // duplicate
174daad67b5SFeifei Xu #define cfgPCIE_ACS_CAP                                                                                 0x02a4 // duplicate
175daad67b5SFeifei Xu #define cfgPCIE_ACS_CNTL                                                                                0x02a6 // duplicate
176daad67b5SFeifei Xu #define cfgPCIE_ATS_ENH_CAP_LIST                                                                        0x02b0 // duplicate
177daad67b5SFeifei Xu #define cfgPCIE_ATS_CAP                                                                                 0x02b4 // duplicate
178daad67b5SFeifei Xu #define cfgPCIE_ATS_CNTL                                                                                0x02b6 // duplicate
179daad67b5SFeifei Xu #define cfgPCIE_PAGE_REQ_ENH_CAP_LIST                                                                   0x02c0 // duplicate
180daad67b5SFeifei Xu #define cfgPCIE_PAGE_REQ_CNTL                                                                           0x02c4 // duplicate
181daad67b5SFeifei Xu #define cfgPCIE_PAGE_REQ_STATUS                                                                         0x02c6 // duplicate
182daad67b5SFeifei Xu #define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY                                                              0x02c8 // duplicate
183daad67b5SFeifei Xu #define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC                                                                 0x02cc // duplicate
184daad67b5SFeifei Xu #define cfgPCIE_PASID_ENH_CAP_LIST                                                                      0x02d0 // duplicate
185daad67b5SFeifei Xu #define cfgPCIE_PASID_CAP                                                                               0x02d4 // duplicate
186daad67b5SFeifei Xu #define cfgPCIE_PASID_CNTL                                                                              0x02d6 // duplicate
187daad67b5SFeifei Xu #define cfgPCIE_TPH_REQR_ENH_CAP_LIST                                                                   0x02e0 // duplicate
188daad67b5SFeifei Xu #define cfgPCIE_TPH_REQR_CAP                                                                            0x02e4 // duplicate
189daad67b5SFeifei Xu #define cfgPCIE_TPH_REQR_CNTL                                                                           0x02e8 // duplicate
190daad67b5SFeifei Xu #define cfgPCIE_MC_ENH_CAP_LIST                                                                         0x02f0 // duplicate
191daad67b5SFeifei Xu #define cfgPCIE_MC_CAP                                                                                  0x02f4 // duplicate
192daad67b5SFeifei Xu #define cfgPCIE_MC_CNTL                                                                                 0x02f6 // duplicate
193daad67b5SFeifei Xu #define cfgPCIE_MC_ADDR0                                                                                0x02f8 // duplicate
194daad67b5SFeifei Xu #define cfgPCIE_MC_ADDR1                                                                                0x02fc // duplicate
195daad67b5SFeifei Xu #define cfgPCIE_MC_RCV0                                                                                 0x0300 // duplicate
196daad67b5SFeifei Xu #define cfgPCIE_MC_RCV1                                                                                 0x0304 // duplicate
197daad67b5SFeifei Xu #define cfgPCIE_MC_BLOCK_ALL0                                                                           0x0308 // duplicate
198daad67b5SFeifei Xu #define cfgPCIE_MC_BLOCK_ALL1                                                                           0x030c // duplicate
199daad67b5SFeifei Xu #define cfgPCIE_MC_BLOCK_UNTRANSLATED_0                                                                 0x0310 // duplicate
200daad67b5SFeifei Xu #define cfgPCIE_MC_BLOCK_UNTRANSLATED_1                                                                 0x0314 // duplicate
201daad67b5SFeifei Xu #define cfgPCIE_LTR_ENH_CAP_LIST                                                                        0x0320 // duplicate
202daad67b5SFeifei Xu #define cfgPCIE_LTR_CAP                                                                                 0x0324 // duplicate
203daad67b5SFeifei Xu #define cfgPCIE_ARI_ENH_CAP_LIST                                                                        0x0328 // duplicate
204daad67b5SFeifei Xu #define cfgPCIE_ARI_CAP                                                                                 0x032c // duplicate
205daad67b5SFeifei Xu #define cfgPCIE_ARI_CNTL                                                                                0x032e // duplicate
206daad67b5SFeifei Xu #define cfgPCIE_SRIOV_ENH_CAP_LIST                                                                      0x0330 // duplicate
207daad67b5SFeifei Xu #define cfgPCIE_SRIOV_CAP                                                                               0x0334 // duplicate
208daad67b5SFeifei Xu #define cfgPCIE_SRIOV_CONTROL                                                                           0x0338 // duplicate
209daad67b5SFeifei Xu #define cfgPCIE_SRIOV_STATUS                                                                            0x033a // duplicate
210daad67b5SFeifei Xu #define cfgPCIE_SRIOV_INITIAL_VFS                                                                       0x033c // duplicate
211daad67b5SFeifei Xu #define cfgPCIE_SRIOV_TOTAL_VFS                                                                         0x033e // duplicate
212daad67b5SFeifei Xu #define cfgPCIE_SRIOV_NUM_VFS                                                                           0x0340 // duplicate
213daad67b5SFeifei Xu #define cfgPCIE_SRIOV_FUNC_DEP_LINK                                                                     0x0342 // duplicate
214daad67b5SFeifei Xu #define cfgPCIE_SRIOV_FIRST_VF_OFFSET                                                                   0x0344 // duplicate
215daad67b5SFeifei Xu #define cfgPCIE_SRIOV_VF_STRIDE                                                                         0x0346 // duplicate
216daad67b5SFeifei Xu #define cfgPCIE_SRIOV_VF_DEVICE_ID                                                                      0x034a // duplicate
217daad67b5SFeifei Xu #define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE                                                               0x034c // duplicate
218daad67b5SFeifei Xu #define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE                                                                  0x0350 // duplicate
219daad67b5SFeifei Xu #define cfgPCIE_SRIOV_VF_BASE_ADDR_0                                                                    0x0354 // duplicate
220daad67b5SFeifei Xu #define cfgPCIE_SRIOV_VF_BASE_ADDR_1                                                                    0x0358 // duplicate
221daad67b5SFeifei Xu #define cfgPCIE_SRIOV_VF_BASE_ADDR_2                                                                    0x035c // duplicate
222daad67b5SFeifei Xu #define cfgPCIE_SRIOV_VF_BASE_ADDR_3                                                                    0x0360 // duplicate
223daad67b5SFeifei Xu #define cfgPCIE_SRIOV_VF_BASE_ADDR_4                                                                    0x0364 // duplicate
224daad67b5SFeifei Xu #define cfgPCIE_SRIOV_VF_BASE_ADDR_5                                                                    0x0368 // duplicate
225daad67b5SFeifei Xu #define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                                                   0x036c // duplicate
226daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                                                     0x0400 // duplicate
227daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                                              0x0404 // duplicate
228daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                                                 0x0408 // duplicate
229daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE                                                  0x040c // duplicate
230daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS                                                  0x0410 // duplicate
231daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                                                0x0414 // duplicate
232daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0                                                0x0418 // duplicate
233daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1                                                0x041c // duplicate
234daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2                                                0x0420 // duplicate
235daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT                                                      0x0424 // duplicate
236daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                                                     0x0428 // duplicate
237daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS                                                      0x042c // duplicate
238daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB                                                       0x0430 // duplicate
239daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB                                                       0x0434 // duplicate
240daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB                                                       0x0438 // duplicate
241daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB                                                       0x043c // duplicate
242daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB                                                       0x0440 // duplicate
243daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB                                                       0x0444 // duplicate
244daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB                                                       0x0448 // duplicate
245daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB                                                       0x044c // duplicate
246daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB                                                       0x0450 // duplicate
247daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB                                                       0x0454 // duplicate
248daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB                                                      0x0458 // duplicate
249daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB                                                      0x045c // duplicate
250daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB                                                      0x0460 // duplicate
251daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB                                                      0x0464 // duplicate
252daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB                                                      0x0468 // duplicate
253daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB                                                      0x046c // duplicate
254daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0                                                   0x0470 // duplicate
255daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1                                                   0x0474 // duplicate
256daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2                                                   0x0478 // duplicate
257daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3                                                   0x047c // duplicate
258daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4                                                   0x0480 // duplicate
259daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5                                                   0x0484 // duplicate
260daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6                                                   0x0488 // duplicate
261daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7                                                   0x048c // duplicate
262daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0                                                   0x0490 // duplicate
263daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1                                                   0x0494 // duplicate
264daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2                                                   0x0498 // duplicate
265daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3                                                   0x049c // duplicate
266daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4                                                   0x04a0 // duplicate
267daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5                                                   0x04a4 // duplicate
268daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6                                                   0x04a8 // duplicate
269daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7                                                   0x04ac // duplicate
270daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0                                                   0x04b0 // duplicate
271daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1                                                   0x04b4 // duplicate
272daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2                                                   0x04b8 // duplicate
273daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3                                                   0x04bc // duplicate
274daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4                                                   0x04c0 // duplicate
275daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5                                                   0x04c4 // duplicate
276daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6                                                   0x04c8 // duplicate
277daad67b5SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7                                                   0x04cc // duplicate
278daad67b5SFeifei Xu 
279daad67b5SFeifei Xu 
280daad67b5SFeifei Xu // addressBlock: bif_cfg_dev0_swds_bifcfgdecp
281daad67b5SFeifei Xu // base address: 0x0
282daad67b5SFeifei Xu #define mmSUB_BUS_NUMBER_LATENCY                                                                       0x0006 // duplicate
283daad67b5SFeifei Xu #define mmSUB_BUS_NUMBER_LATENCY_BASE_IDX                                                              0
284daad67b5SFeifei Xu #define mmIO_BASE_LIMIT                                                                                0x0007 // duplicate
285daad67b5SFeifei Xu #define mmIO_BASE_LIMIT_BASE_IDX                                                                       0
286daad67b5SFeifei Xu #define mmSECONDARY_STATUS                                                                             0x0007 // duplicate
287daad67b5SFeifei Xu #define mmSECONDARY_STATUS_BASE_IDX                                                                    0
288daad67b5SFeifei Xu #define mmMEM_BASE_LIMIT                                                                               0x0008 // duplicate
289daad67b5SFeifei Xu #define mmMEM_BASE_LIMIT_BASE_IDX                                                                      0
290daad67b5SFeifei Xu #define mmPREF_BASE_LIMIT                                                                              0x0009 // duplicate
291daad67b5SFeifei Xu #define mmPREF_BASE_LIMIT_BASE_IDX                                                                     0
292daad67b5SFeifei Xu #define mmPREF_BASE_UPPER                                                                              0x000a // duplicate
293daad67b5SFeifei Xu #define mmPREF_BASE_UPPER_BASE_IDX                                                                     0
294daad67b5SFeifei Xu #define mmPREF_LIMIT_UPPER                                                                             0x000b // duplicate
295daad67b5SFeifei Xu #define mmPREF_LIMIT_UPPER_BASE_IDX                                                                    0
296daad67b5SFeifei Xu #define mmIO_BASE_LIMIT_HI                                                                             0x000c // duplicate
297daad67b5SFeifei Xu #define mmIO_BASE_LIMIT_HI_BASE_IDX                                                                    0
298daad67b5SFeifei Xu #define mmIRQ_BRIDGE_CNTL                                                                              0x000f // duplicate
299daad67b5SFeifei Xu #define mmIRQ_BRIDGE_CNTL_BASE_IDX                                                                     0
300daad67b5SFeifei Xu #define mmSLOT_CAP                                                                                     0x001b // duplicate
301daad67b5SFeifei Xu #define mmSLOT_CAP_BASE_IDX                                                                            0
302daad67b5SFeifei Xu #define mmSLOT_CNTL                                                                                    0x001c // duplicate
303daad67b5SFeifei Xu #define mmSLOT_CNTL_BASE_IDX                                                                           0
304daad67b5SFeifei Xu #define mmSLOT_STATUS                                                                                  0x001c // duplicate
305daad67b5SFeifei Xu #define mmSLOT_STATUS_BASE_IDX                                                                         0
306daad67b5SFeifei Xu #define mmSSID_CAP_LIST                                                                                0x0030 // duplicate
307daad67b5SFeifei Xu #define mmSSID_CAP_LIST_BASE_IDX                                                                       0
308daad67b5SFeifei Xu #define mmSSID_CAP                                                                                     0x0031 // duplicate
309daad67b5SFeifei Xu #define mmSSID_CAP_BASE_IDX                                                                            0
310daad67b5SFeifei Xu 
311daad67b5SFeifei Xu 
312daad67b5SFeifei Xu // addressBlock: rcc_shadow_reg_shadowdec
313daad67b5SFeifei Xu // base address: 0x0
314daad67b5SFeifei Xu #define ixSHADOW_COMMAND                                                                               0x0004 // duplicate
315daad67b5SFeifei Xu #define ixSHADOW_BASE_ADDR_1                                                                           0x0010 // duplicate
316daad67b5SFeifei Xu #define ixSHADOW_BASE_ADDR_2                                                                           0x0014 // duplicate
317daad67b5SFeifei Xu #define ixSHADOW_SUB_BUS_NUMBER_LATENCY                                                                0x0018 // duplicate
318daad67b5SFeifei Xu #define ixSHADOW_IO_BASE_LIMIT                                                                         0x001c // duplicate
319daad67b5SFeifei Xu #define ixSHADOW_MEM_BASE_LIMIT                                                                        0x0020 // duplicate
320daad67b5SFeifei Xu #define ixSHADOW_PREF_BASE_LIMIT                                                                       0x0024 // duplicate
321daad67b5SFeifei Xu #define ixSHADOW_PREF_BASE_UPPER                                                                       0x0028 // duplicate
322daad67b5SFeifei Xu #define ixSHADOW_PREF_LIMIT_UPPER                                                                      0x002c // duplicate
323daad67b5SFeifei Xu #define ixSHADOW_IO_BASE_LIMIT_HI                                                                      0x0030 // duplicate
324daad67b5SFeifei Xu #define ixSHADOW_IRQ_BRIDGE_CNTL                                                                       0x003e // duplicate
325daad67b5SFeifei Xu #define ixSUC_INDEX                                                                                    0x00e0 // duplicate
326daad67b5SFeifei Xu #define ixSUC_DATA                                                                                     0x00e4 // duplicate
327daad67b5SFeifei Xu 
328daad67b5SFeifei Xu 
329daad67b5SFeifei Xu // addressBlock: bif_bx_pf_SUMDEC
330daad67b5SFeifei Xu // base address: 0x0
331daad67b5SFeifei Xu #define ixSUM_INDEX                                                                                    0x00e0 // duplicate
332daad67b5SFeifei Xu #define ixSUM_DATA                                                                                     0x00e4 // duplicate
333daad67b5SFeifei Xu 
334daad67b5SFeifei Xu 
335daad67b5SFeifei Xu // addressBlock: gdc_GDCDEC
336daad67b5SFeifei Xu // base address: 0x1400000
337daad67b5SFeifei Xu #define mmA2S_CNTL_CL0                                                                                 0x4f0ab0 // duplicate
338daad67b5SFeifei Xu #define mmA2S_CNTL_CL0_BASE_IDX                                                                        3
339daad67b5SFeifei Xu #define mmA2S_CNTL_CL1                                                                                 0x4f0ab1 // duplicate
340daad67b5SFeifei Xu #define mmA2S_CNTL_CL1_BASE_IDX                                                                        3
341daad67b5SFeifei Xu #define mmA2S_CNTL_CL2                                                                                 0x4f0ab2 // duplicate
342daad67b5SFeifei Xu #define mmA2S_CNTL_CL2_BASE_IDX                                                                        3
343daad67b5SFeifei Xu #define mmA2S_CNTL_CL3                                                                                 0x4f0ab3 // duplicate
344daad67b5SFeifei Xu #define mmA2S_CNTL_CL3_BASE_IDX                                                                        3
345daad67b5SFeifei Xu #define mmA2S_CNTL_CL4                                                                                 0x4f0ab4 // duplicate
346daad67b5SFeifei Xu #define mmA2S_CNTL_CL4_BASE_IDX                                                                        3
347daad67b5SFeifei Xu #define mmA2S_CNTL_SW0                                                                                 0x4f0ad0 // duplicate
348daad67b5SFeifei Xu #define mmA2S_CNTL_SW0_BASE_IDX                                                                        3
349daad67b5SFeifei Xu #define mmA2S_CNTL_SW1                                                                                 0x4f0ad1 // duplicate
350daad67b5SFeifei Xu #define mmA2S_CNTL_SW1_BASE_IDX                                                                        3
351daad67b5SFeifei Xu #define mmA2S_CNTL_SW2                                                                                 0x4f0ad2 // duplicate
352daad67b5SFeifei Xu #define mmA2S_CNTL_SW2_BASE_IDX                                                                        3
353daad67b5SFeifei Xu #define mmNGDC_MGCG_CTRL                                                                               0x4f0ae0 // duplicate
354daad67b5SFeifei Xu #define mmNGDC_MGCG_CTRL_BASE_IDX                                                                      3
355daad67b5SFeifei Xu #define mmA2S_MISC_CNTL                                                                                0x4f0ae1 // duplicate
356daad67b5SFeifei Xu #define mmA2S_MISC_CNTL_BASE_IDX                                                                       3
357daad67b5SFeifei Xu #define mmNGDC_SDP_PORT_CTRL                                                                           0x4f0ae2 // duplicate
358daad67b5SFeifei Xu #define mmNGDC_SDP_PORT_CTRL_BASE_IDX                                                                  3
359daad67b5SFeifei Xu #define mmNGDC_RESERVED_0                                                                              0x4f0aeb // duplicate
360daad67b5SFeifei Xu #define mmNGDC_RESERVED_0_BASE_IDX                                                                     3
361daad67b5SFeifei Xu #define mmNGDC_RESERVED_1                                                                              0x4f0aec // duplicate
362daad67b5SFeifei Xu #define mmNGDC_RESERVED_1_BASE_IDX                                                                     3
363daad67b5SFeifei Xu #define mmBIF_SDMA0_DOORBELL_RANGE                                                                     0x4f0af0 // duplicate
364daad67b5SFeifei Xu #define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX                                                            3
365daad67b5SFeifei Xu #define mmBIF_SDMA1_DOORBELL_RANGE                                                                     0x4f0af1 // duplicate
366daad67b5SFeifei Xu #define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX                                                            3
367daad67b5SFeifei Xu #define mmBIF_IH_DOORBELL_RANGE                                                                        0x4f0af2 // duplicate
368daad67b5SFeifei Xu #define mmBIF_IH_DOORBELL_RANGE_BASE_IDX                                                               3
369daad67b5SFeifei Xu #define mmBIF_MMSCH0_DOORBELL_RANGE                                                                    0x4f0af3 // duplicate
370daad67b5SFeifei Xu #define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX                                                           3
371daad67b5SFeifei Xu #define mmBIF_DOORBELL_FENCE_CNTL                                                                      0x4f0afe // duplicate
372daad67b5SFeifei Xu #define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX                                                             3
373daad67b5SFeifei Xu #define mmS2A_MISC_CNTL                                                                                0x4f0aff // duplicate
374daad67b5SFeifei Xu #define mmS2A_MISC_CNTL_BASE_IDX                                                                       3
375daad67b5SFeifei Xu #define mmA2S_CNTL2_SEC_CL0                                                                            0x4f0b00 // duplicate
376daad67b5SFeifei Xu #define mmA2S_CNTL2_SEC_CL0_BASE_IDX                                                                   3
377daad67b5SFeifei Xu #define mmA2S_CNTL2_SEC_CL1                                                                            0x4f0b01 // duplicate
378daad67b5SFeifei Xu #define mmA2S_CNTL2_SEC_CL1_BASE_IDX                                                                   3
379daad67b5SFeifei Xu #define mmA2S_CNTL2_SEC_CL2                                                                            0x4f0b02 // duplicate
380daad67b5SFeifei Xu #define mmA2S_CNTL2_SEC_CL2_BASE_IDX                                                                   3
381daad67b5SFeifei Xu #define mmA2S_CNTL2_SEC_CL3                                                                            0x4f0b03 // duplicate
382daad67b5SFeifei Xu #define mmA2S_CNTL2_SEC_CL3_BASE_IDX                                                                   3
383daad67b5SFeifei Xu #define mmA2S_CNTL2_SEC_CL4                                                                            0x4f0b04 // duplicate
384daad67b5SFeifei Xu #define mmA2S_CNTL2_SEC_CL4_BASE_IDX                                                                   3
385daad67b5SFeifei Xu 
386daad67b5SFeifei Xu 
387daad67b5SFeifei Xu // addressBlock: nbif_sion_SIONDEC
388daad67b5SFeifei Xu // base address: 0x1400000
389daad67b5SFeifei Xu #define ixSION_CL0_RdRsp_BurstTarget_REG0                                                              0x1e000
390daad67b5SFeifei Xu #define ixSION_CL0_RdRsp_BurstTarget_REG1                                                              0x1e004
391daad67b5SFeifei Xu #define ixSION_CL0_RdRsp_TimeSlot_REG0                                                                 0x1e008
392daad67b5SFeifei Xu #define ixSION_CL0_RdRsp_TimeSlot_REG1                                                                 0x1e00c
393daad67b5SFeifei Xu #define ixSION_CL0_WrRsp_BurstTarget_REG0                                                              0x1e010
394daad67b5SFeifei Xu #define ixSION_CL0_WrRsp_BurstTarget_REG1                                                              0x1e014
395daad67b5SFeifei Xu #define ixSION_CL0_WrRsp_TimeSlot_REG0                                                                 0x1e018
396daad67b5SFeifei Xu #define ixSION_CL0_WrRsp_TimeSlot_REG1                                                                 0x1e01c
397daad67b5SFeifei Xu #define ixSION_CL0_Req_BurstTarget_REG0                                                                0x1e020
398daad67b5SFeifei Xu #define ixSION_CL0_Req_BurstTarget_REG1                                                                0x1e024
399daad67b5SFeifei Xu #define ixSION_CL0_Req_TimeSlot_REG0                                                                   0x1e028
400daad67b5SFeifei Xu #define ixSION_CL0_Req_TimeSlot_REG1                                                                   0x1e02c
401daad67b5SFeifei Xu #define ixSION_CL0_ReqPoolCredit_Alloc_REG0                                                            0x1e030
402daad67b5SFeifei Xu #define ixSION_CL0_ReqPoolCredit_Alloc_REG1                                                            0x1e034
403daad67b5SFeifei Xu #define ixSION_CL0_DataPoolCredit_Alloc_REG0                                                           0x1e038
404daad67b5SFeifei Xu #define ixSION_CL0_DataPoolCredit_Alloc_REG1                                                           0x1e03c
405daad67b5SFeifei Xu #define ixSION_CL0_RdRspPoolCredit_Alloc_REG0                                                          0x1e040
406daad67b5SFeifei Xu #define ixSION_CL0_RdRspPoolCredit_Alloc_REG1                                                          0x1e044
407daad67b5SFeifei Xu #define ixSION_CL0_WrRspPoolCredit_Alloc_REG0                                                          0x1e048
408daad67b5SFeifei Xu #define ixSION_CL0_WrRspPoolCredit_Alloc_REG1                                                          0x1e04c
409daad67b5SFeifei Xu #define ixSION_CL1_RdRsp_BurstTarget_REG0                                                              0x1e050
410daad67b5SFeifei Xu #define ixSION_CL1_RdRsp_BurstTarget_REG1                                                              0x1e054
411daad67b5SFeifei Xu #define ixSION_CL1_RdRsp_TimeSlot_REG0                                                                 0x1e058
412daad67b5SFeifei Xu #define ixSION_CL1_RdRsp_TimeSlot_REG1                                                                 0x1e05c
413daad67b5SFeifei Xu #define ixSION_CL1_WrRsp_BurstTarget_REG0                                                              0x1e060
414daad67b5SFeifei Xu #define ixSION_CL1_WrRsp_BurstTarget_REG1                                                              0x1e064
415daad67b5SFeifei Xu #define ixSION_CL1_WrRsp_TimeSlot_REG0                                                                 0x1e068
416daad67b5SFeifei Xu #define ixSION_CL1_WrRsp_TimeSlot_REG1                                                                 0x1e06c
417daad67b5SFeifei Xu #define ixSION_CL1_Req_BurstTarget_REG0                                                                0x1e070
418daad67b5SFeifei Xu #define ixSION_CL1_Req_BurstTarget_REG1                                                                0x1e074
419daad67b5SFeifei Xu #define ixSION_CL1_Req_TimeSlot_REG0                                                                   0x1e078
420daad67b5SFeifei Xu #define ixSION_CL1_Req_TimeSlot_REG1                                                                   0x1e07c
421daad67b5SFeifei Xu #define ixSION_CL1_ReqPoolCredit_Alloc_REG0                                                            0x1e080
422daad67b5SFeifei Xu #define ixSION_CL1_ReqPoolCredit_Alloc_REG1                                                            0x1e084
423daad67b5SFeifei Xu #define ixSION_CL1_DataPoolCredit_Alloc_REG0                                                           0x1e088
424daad67b5SFeifei Xu #define ixSION_CL1_DataPoolCredit_Alloc_REG1                                                           0x1e08c
425daad67b5SFeifei Xu #define ixSION_CL1_RdRspPoolCredit_Alloc_REG0                                                          0x1e090
426daad67b5SFeifei Xu #define ixSION_CL1_RdRspPoolCredit_Alloc_REG1                                                          0x1e094
427daad67b5SFeifei Xu #define ixSION_CL1_WrRspPoolCredit_Alloc_REG0                                                          0x1e098
428daad67b5SFeifei Xu #define ixSION_CL1_WrRspPoolCredit_Alloc_REG1                                                          0x1e09c
429daad67b5SFeifei Xu #define ixSION_CL2_RdRsp_BurstTarget_REG0                                                              0x1e0a0
430daad67b5SFeifei Xu #define ixSION_CL2_RdRsp_BurstTarget_REG1                                                              0x1e0a4
431daad67b5SFeifei Xu #define ixSION_CL2_RdRsp_TimeSlot_REG0                                                                 0x1e0a8
432daad67b5SFeifei Xu #define ixSION_CL2_RdRsp_TimeSlot_REG1                                                                 0x1e0ac
433daad67b5SFeifei Xu #define ixSION_CL2_WrRsp_BurstTarget_REG0                                                              0x1e0b0
434daad67b5SFeifei Xu #define ixSION_CL2_WrRsp_BurstTarget_REG1                                                              0x1e0b4
435daad67b5SFeifei Xu #define ixSION_CL2_WrRsp_TimeSlot_REG0                                                                 0x1e0b8
436daad67b5SFeifei Xu #define ixSION_CL2_WrRsp_TimeSlot_REG1                                                                 0x1e0bc
437daad67b5SFeifei Xu #define ixSION_CL2_Req_BurstTarget_REG0                                                                0x1e0c0
438daad67b5SFeifei Xu #define ixSION_CL2_Req_BurstTarget_REG1                                                                0x1e0c4
439daad67b5SFeifei Xu #define ixSION_CL2_Req_TimeSlot_REG0                                                                   0x1e0c8
440daad67b5SFeifei Xu #define ixSION_CL2_Req_TimeSlot_REG1                                                                   0x1e0cc
441daad67b5SFeifei Xu #define ixSION_CL2_ReqPoolCredit_Alloc_REG0                                                            0x1e0d0
442daad67b5SFeifei Xu #define ixSION_CL2_ReqPoolCredit_Alloc_REG1                                                            0x1e0d4
443daad67b5SFeifei Xu #define ixSION_CL2_DataPoolCredit_Alloc_REG0                                                           0x1e0d8
444daad67b5SFeifei Xu #define ixSION_CL2_DataPoolCredit_Alloc_REG1                                                           0x1e0dc
445daad67b5SFeifei Xu #define ixSION_CL2_RdRspPoolCredit_Alloc_REG0                                                          0x1e0e0
446daad67b5SFeifei Xu #define ixSION_CL2_RdRspPoolCredit_Alloc_REG1                                                          0x1e0e4
447daad67b5SFeifei Xu #define ixSION_CL2_WrRspPoolCredit_Alloc_REG0                                                          0x1e0e8
448daad67b5SFeifei Xu #define ixSION_CL2_WrRspPoolCredit_Alloc_REG1                                                          0x1e0ec
449daad67b5SFeifei Xu #define ixSION_CL3_RdRsp_BurstTarget_REG0                                                              0x1e0f0
450daad67b5SFeifei Xu #define ixSION_CL3_RdRsp_BurstTarget_REG1                                                              0x1e0f4
451daad67b5SFeifei Xu #define ixSION_CL3_RdRsp_TimeSlot_REG0                                                                 0x1e0f8
452daad67b5SFeifei Xu #define ixSION_CL3_RdRsp_TimeSlot_REG1                                                                 0x1e0fc
453daad67b5SFeifei Xu #define ixSION_CL3_WrRsp_BurstTarget_REG0                                                              0x1e100
454daad67b5SFeifei Xu #define ixSION_CL3_WrRsp_BurstTarget_REG1                                                              0x1e104
455daad67b5SFeifei Xu #define ixSION_CL3_WrRsp_TimeSlot_REG0                                                                 0x1e108
456daad67b5SFeifei Xu #define ixSION_CL3_WrRsp_TimeSlot_REG1                                                                 0x1e10c
457daad67b5SFeifei Xu #define ixSION_CL3_Req_BurstTarget_REG0                                                                0x1e110
458daad67b5SFeifei Xu #define ixSION_CL3_Req_BurstTarget_REG1                                                                0x1e114
459daad67b5SFeifei Xu #define ixSION_CL3_Req_TimeSlot_REG0                                                                   0x1e118
460daad67b5SFeifei Xu #define ixSION_CL3_Req_TimeSlot_REG1                                                                   0x1e11c
461daad67b5SFeifei Xu #define ixSION_CL3_ReqPoolCredit_Alloc_REG0                                                            0x1e120
462daad67b5SFeifei Xu #define ixSION_CL3_ReqPoolCredit_Alloc_REG1                                                            0x1e124
463daad67b5SFeifei Xu #define ixSION_CL3_DataPoolCredit_Alloc_REG0                                                           0x1e128
464daad67b5SFeifei Xu #define ixSION_CL3_DataPoolCredit_Alloc_REG1                                                           0x1e12c
465daad67b5SFeifei Xu #define ixSION_CL3_RdRspPoolCredit_Alloc_REG0                                                          0x1e130
466daad67b5SFeifei Xu #define ixSION_CL3_RdRspPoolCredit_Alloc_REG1                                                          0x1e134
467daad67b5SFeifei Xu #define ixSION_CL3_WrRspPoolCredit_Alloc_REG0                                                          0x1e138
468daad67b5SFeifei Xu #define ixSION_CL3_WrRspPoolCredit_Alloc_REG1                                                          0x1e13c
469daad67b5SFeifei Xu #define ixSION_CL4_RdRsp_BurstTarget_REG0                                                              0x1e140
470daad67b5SFeifei Xu #define ixSION_CL4_RdRsp_BurstTarget_REG1                                                              0x1e144
471daad67b5SFeifei Xu #define ixSION_CL4_RdRsp_TimeSlot_REG0                                                                 0x1e148
472daad67b5SFeifei Xu #define ixSION_CL4_RdRsp_TimeSlot_REG1                                                                 0x1e14c
473daad67b5SFeifei Xu #define ixSION_CL4_WrRsp_BurstTarget_REG0                                                              0x1e150
474daad67b5SFeifei Xu #define ixSION_CL4_WrRsp_BurstTarget_REG1                                                              0x1e154
475daad67b5SFeifei Xu #define ixSION_CL4_WrRsp_TimeSlot_REG0                                                                 0x1e158
476daad67b5SFeifei Xu #define ixSION_CL4_WrRsp_TimeSlot_REG1                                                                 0x1e15c
477daad67b5SFeifei Xu #define ixSION_CL4_Req_BurstTarget_REG0                                                                0x1e160
478daad67b5SFeifei Xu #define ixSION_CL4_Req_BurstTarget_REG1                                                                0x1e164
479daad67b5SFeifei Xu #define ixSION_CL4_Req_TimeSlot_REG0                                                                   0x1e168
480daad67b5SFeifei Xu #define ixSION_CL4_Req_TimeSlot_REG1                                                                   0x1e16c
481daad67b5SFeifei Xu #define ixSION_CL4_ReqPoolCredit_Alloc_REG0                                                            0x1e170
482daad67b5SFeifei Xu #define ixSION_CL4_ReqPoolCredit_Alloc_REG1                                                            0x1e174
483daad67b5SFeifei Xu #define ixSION_CL4_DataPoolCredit_Alloc_REG0                                                           0x1e178
484daad67b5SFeifei Xu #define ixSION_CL4_DataPoolCredit_Alloc_REG1                                                           0x1e17c
485daad67b5SFeifei Xu #define ixSION_CL4_RdRspPoolCredit_Alloc_REG0                                                          0x1e180
486daad67b5SFeifei Xu #define ixSION_CL4_RdRspPoolCredit_Alloc_REG1                                                          0x1e184
487daad67b5SFeifei Xu #define ixSION_CL4_WrRspPoolCredit_Alloc_REG0                                                          0x1e188
488daad67b5SFeifei Xu #define ixSION_CL4_WrRspPoolCredit_Alloc_REG1                                                          0x1e18c
489daad67b5SFeifei Xu #define ixSION_CL5_RdRsp_BurstTarget_REG0                                                              0x1e190
490daad67b5SFeifei Xu #define ixSION_CL5_RdRsp_BurstTarget_REG1                                                              0x1e194
491daad67b5SFeifei Xu #define ixSION_CL5_RdRsp_TimeSlot_REG0                                                                 0x1e198
492daad67b5SFeifei Xu #define ixSION_CL5_RdRsp_TimeSlot_REG1                                                                 0x1e19c
493daad67b5SFeifei Xu #define ixSION_CL5_WrRsp_BurstTarget_REG0                                                              0x1e1a0
494daad67b5SFeifei Xu #define ixSION_CL5_WrRsp_BurstTarget_REG1                                                              0x1e1a4
495daad67b5SFeifei Xu #define ixSION_CL5_WrRsp_TimeSlot_REG0                                                                 0x1e1a8
496daad67b5SFeifei Xu #define ixSION_CL5_WrRsp_TimeSlot_REG1                                                                 0x1e1ac
497daad67b5SFeifei Xu #define ixSION_CL5_Req_BurstTarget_REG0                                                                0x1e1b0
498daad67b5SFeifei Xu #define ixSION_CL5_Req_BurstTarget_REG1                                                                0x1e1b4
499daad67b5SFeifei Xu #define ixSION_CL5_Req_TimeSlot_REG0                                                                   0x1e1b8
500daad67b5SFeifei Xu #define ixSION_CL5_Req_TimeSlot_REG1                                                                   0x1e1bc
501daad67b5SFeifei Xu #define ixSION_CL5_ReqPoolCredit_Alloc_REG0                                                            0x1e1c0
502daad67b5SFeifei Xu #define ixSION_CL5_ReqPoolCredit_Alloc_REG1                                                            0x1e1c4
503daad67b5SFeifei Xu #define ixSION_CL5_DataPoolCredit_Alloc_REG0                                                           0x1e1c8
504daad67b5SFeifei Xu #define ixSION_CL5_DataPoolCredit_Alloc_REG1                                                           0x1e1cc
505daad67b5SFeifei Xu #define ixSION_CL5_RdRspPoolCredit_Alloc_REG0                                                          0x1e1d0
506daad67b5SFeifei Xu #define ixSION_CL5_RdRspPoolCredit_Alloc_REG1                                                          0x1e1d4
507daad67b5SFeifei Xu #define ixSION_CL5_WrRspPoolCredit_Alloc_REG0                                                          0x1e1d8
508daad67b5SFeifei Xu #define ixSION_CL5_WrRspPoolCredit_Alloc_REG1                                                          0x1e1dc
509daad67b5SFeifei Xu #define ixSION_CNTL_REG0                                                                               0x1e1e0
510daad67b5SFeifei Xu #define ixSION_CNTL_REG1                                                                               0x1e1e4
511daad67b5SFeifei Xu 
512daad67b5SFeifei Xu 
513daad67b5SFeifei Xu // addressBlock: syshub_mmreg_direct_syshubdirect
514daad67b5SFeifei Xu // base address: 0x1400000
515daad67b5SFeifei Xu #define ixSYSHUB_DS_CTRL_SOCCLK                                                                        0x10000 // duplicate
516daad67b5SFeifei Xu #define ixSYSHUB_DS_CTRL2_SOCCLK                                                                       0x10004 // duplicate
517daad67b5SFeifei Xu #define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK                                                     0x10008 // duplicate
518daad67b5SFeifei Xu #define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK                                                        0x1000c // duplicate
519daad67b5SFeifei Xu #define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL                                                                 0x10010 // duplicate
520daad67b5SFeifei Xu #define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL                                                                 0x10014 // duplicate
521daad67b5SFeifei Xu #define ixDMA_CLK0_SW0_CL0_CNTL                                                                        0x10018 // duplicate
522daad67b5SFeifei Xu #define ixDMA_CLK0_SW0_CL1_CNTL                                                                        0x1001c // duplicate
523daad67b5SFeifei Xu #define ixDMA_CLK0_SW0_CL2_CNTL                                                                        0x10020 // duplicate
524daad67b5SFeifei Xu #define ixDMA_CLK0_SW0_CL3_CNTL                                                                        0x10024 // duplicate
525daad67b5SFeifei Xu #define ixDMA_CLK0_SW0_CL4_CNTL                                                                        0x10028 // duplicate
526daad67b5SFeifei Xu #define ixDMA_CLK0_SW0_CL5_CNTL                                                                        0x1002c // duplicate
527daad67b5SFeifei Xu #define ixDMA_CLK0_SW1_CL0_CNTL                                                                        0x10030 // duplicate
528daad67b5SFeifei Xu #define ixDMA_CLK0_SW2_CL0_CNTL                                                                        0x10034 // duplicate
529daad67b5SFeifei Xu #define ixSYSHUB_CG_CNTL                                                                               0x10300 // duplicate
530daad67b5SFeifei Xu #define ixSYSHUB_TRANS_IDLE                                                                            0x10308 // duplicate
531daad67b5SFeifei Xu #define ixSYSHUB_HP_TIMER                                                                              0x1030c // duplicate
532daad67b5SFeifei Xu #define ixSYSHUB_SCRATCH                                                                               0x10f00 // duplicate
533daad67b5SFeifei Xu #define ixSYSHUB_DS_CTRL_SHUBCLK                                                                       0x11000 // duplicate
534daad67b5SFeifei Xu #define ixSYSHUB_DS_CTRL2_SHUBCLK                                                                      0x11004 // duplicate
535daad67b5SFeifei Xu #define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK                                                    0x11008 // duplicate
536daad67b5SFeifei Xu #define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK                                                       0x1100c // duplicate
537daad67b5SFeifei Xu #define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL                                                                 0x11010 // duplicate
538daad67b5SFeifei Xu #define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL                                                                 0x11014 // duplicate
539daad67b5SFeifei Xu #define ixDMA_CLK1_SW0_CL0_CNTL                                                                        0x11018 // duplicate
540daad67b5SFeifei Xu #define ixDMA_CLK1_SW0_CL1_CNTL                                                                        0x1101c // duplicate
541daad67b5SFeifei Xu #define ixDMA_CLK1_SW0_CL2_CNTL                                                                        0x11020 // duplicate
542daad67b5SFeifei Xu #define ixDMA_CLK1_SW0_CL3_CNTL                                                                        0x11024 // duplicate
543daad67b5SFeifei Xu #define ixDMA_CLK1_SW0_CL4_CNTL                                                                        0x11028 // duplicate
544daad67b5SFeifei Xu #define ixDMA_CLK1_SW1_CL0_CNTL                                                                        0x1102c // duplicate
545daad67b5SFeifei Xu #define ixDMA_CLK1_SW1_CL1_CNTL                                                                        0x11030 // duplicate
546daad67b5SFeifei Xu #define ixDMA_CLK1_SW1_CL2_CNTL                                                                        0x11034 // duplicate
547daad67b5SFeifei Xu #define ixDMA_CLK1_SW1_CL3_CNTL                                                                        0x11038 // duplicate
548daad67b5SFeifei Xu #define ixDMA_CLK1_SW1_CL4_CNTL                                                                        0x1103c // duplicate
549daad67b5SFeifei Xu 
550daad67b5SFeifei Xu 
551daad67b5SFeifei Xu // addressBlock: gdc_ras_gdc_ras_regblk
552daad67b5SFeifei Xu // base address: 0x1400000
553daad67b5SFeifei Xu #define ixGDC_RAS_LEAF0_CTRL                                                                           0x1f800
554daad67b5SFeifei Xu #define ixGDC_RAS_LEAF1_CTRL                                                                           0x1f804
555daad67b5SFeifei Xu #define ixGDC_RAS_LEAF2_CTRL                                                                           0x1f808
556daad67b5SFeifei Xu #define ixGDC_RAS_LEAF3_CTRL                                                                           0x1f80c
557daad67b5SFeifei Xu #define ixGDC_RAS_LEAF4_CTRL                                                                           0x1f810
558daad67b5SFeifei Xu #define ixGDC_RAS_LEAF5_CTRL                                                                           0x1f814
559daad67b5SFeifei Xu 
560daad67b5SFeifei Xu 
561daad67b5SFeifei Xu // addressBlock: gdc_rst_GDCRST_DEC
562daad67b5SFeifei Xu // base address: 0x1400000
563daad67b5SFeifei Xu #define ixSHUB_PF_FLR_RST                                                                              0x1f000
564daad67b5SFeifei Xu #define ixSHUB_GFX_DRV_MODE1_RST                                                                       0x1f004
565daad67b5SFeifei Xu #define ixSHUB_LINK_RESET                                                                              0x1f008
566daad67b5SFeifei Xu #define ixSHUB_PF0_VF_FLR_RST                                                                          0x1f020
567daad67b5SFeifei Xu #define ixSHUB_HARD_RST_CTRL                                                                           0x1f040
568daad67b5SFeifei Xu #define ixSHUB_SOFT_RST_CTRL                                                                           0x1f044
569daad67b5SFeifei Xu #define ixSHUB_SDP_PORT_RST                                                                            0x1f048
570daad67b5SFeifei Xu 
571daad67b5SFeifei Xu 
572daad67b5SFeifei Xu // memoryMap:EP0F0Reg
573daad67b5SFeifei Xu 
574daad67b5SFeifei Xu 
575daad67b5SFeifei Xu // addressBlock: bif_bx_pf_SYSDEC
576daad67b5SFeifei Xu // base address: 0x0
577daad67b5SFeifei Xu #define mmSBIOS_SCRATCH_0                                                                              0x0048 // duplicate
578daad67b5SFeifei Xu #define mmSBIOS_SCRATCH_0_BASE_IDX                                                                     0
579daad67b5SFeifei Xu #define mmSBIOS_SCRATCH_1                                                                              0x0049 // duplicate
580daad67b5SFeifei Xu #define mmSBIOS_SCRATCH_1_BASE_IDX                                                                     0
581daad67b5SFeifei Xu #define mmSBIOS_SCRATCH_2                                                                              0x004a // duplicate
582daad67b5SFeifei Xu #define mmSBIOS_SCRATCH_2_BASE_IDX                                                                     0
583daad67b5SFeifei Xu #define mmSBIOS_SCRATCH_3                                                                              0x004b // duplicate
584daad67b5SFeifei Xu #define mmSBIOS_SCRATCH_3_BASE_IDX                                                                     0
585daad67b5SFeifei Xu #define mmBIOS_SCRATCH_0                                                                               0x004c // duplicate
586daad67b5SFeifei Xu #define mmBIOS_SCRATCH_0_BASE_IDX                                                                      0
587daad67b5SFeifei Xu #define mmBIOS_SCRATCH_1                                                                               0x004d // duplicate
588daad67b5SFeifei Xu #define mmBIOS_SCRATCH_1_BASE_IDX                                                                      0
589daad67b5SFeifei Xu #define mmBIOS_SCRATCH_2                                                                               0x004e // duplicate
590daad67b5SFeifei Xu #define mmBIOS_SCRATCH_2_BASE_IDX                                                                      0
591daad67b5SFeifei Xu #define mmBIOS_SCRATCH_3                                                                               0x004f // duplicate
592daad67b5SFeifei Xu #define mmBIOS_SCRATCH_3_BASE_IDX                                                                      0
593daad67b5SFeifei Xu #define mmBIOS_SCRATCH_4                                                                               0x0050 // duplicate
594daad67b5SFeifei Xu #define mmBIOS_SCRATCH_4_BASE_IDX                                                                      0
595daad67b5SFeifei Xu #define mmBIOS_SCRATCH_5                                                                               0x0051 // duplicate
596daad67b5SFeifei Xu #define mmBIOS_SCRATCH_5_BASE_IDX                                                                      0
597daad67b5SFeifei Xu #define mmBIOS_SCRATCH_6                                                                               0x0052 // duplicate
598daad67b5SFeifei Xu #define mmBIOS_SCRATCH_6_BASE_IDX                                                                      0
599daad67b5SFeifei Xu #define mmBIOS_SCRATCH_7                                                                               0x0053 // duplicate
600daad67b5SFeifei Xu #define mmBIOS_SCRATCH_7_BASE_IDX                                                                      0
601daad67b5SFeifei Xu #define mmBIOS_SCRATCH_8                                                                               0x0054 // duplicate
602daad67b5SFeifei Xu #define mmBIOS_SCRATCH_8_BASE_IDX                                                                      0
603daad67b5SFeifei Xu #define mmBIOS_SCRATCH_9                                                                               0x0055 // duplicate
604daad67b5SFeifei Xu #define mmBIOS_SCRATCH_9_BASE_IDX                                                                      0
605daad67b5SFeifei Xu #define mmBIOS_SCRATCH_10                                                                              0x0056 // duplicate
606daad67b5SFeifei Xu #define mmBIOS_SCRATCH_10_BASE_IDX                                                                     0
607daad67b5SFeifei Xu #define mmBIOS_SCRATCH_11                                                                              0x0057 // duplicate
608daad67b5SFeifei Xu #define mmBIOS_SCRATCH_11_BASE_IDX                                                                     0
609daad67b5SFeifei Xu #define mmBIOS_SCRATCH_12                                                                              0x0058 // duplicate
610daad67b5SFeifei Xu #define mmBIOS_SCRATCH_12_BASE_IDX                                                                     0
611daad67b5SFeifei Xu #define mmBIOS_SCRATCH_13                                                                              0x0059 // duplicate
612daad67b5SFeifei Xu #define mmBIOS_SCRATCH_13_BASE_IDX                                                                     0
613daad67b5SFeifei Xu #define mmBIOS_SCRATCH_14                                                                              0x005a // duplicate
614daad67b5SFeifei Xu #define mmBIOS_SCRATCH_14_BASE_IDX                                                                     0
615daad67b5SFeifei Xu #define mmBIOS_SCRATCH_15                                                                              0x005b // duplicate
616daad67b5SFeifei Xu #define mmBIOS_SCRATCH_15_BASE_IDX                                                                     0
617daad67b5SFeifei Xu #define mmBIF_RLC_INTR_CNTL                                                                            0x0060 // duplicate
618daad67b5SFeifei Xu #define mmBIF_RLC_INTR_CNTL_BASE_IDX                                                                   0
619daad67b5SFeifei Xu #define mmBIF_VCE_INTR_CNTL                                                                            0x0061 // duplicate
620daad67b5SFeifei Xu #define mmBIF_VCE_INTR_CNTL_BASE_IDX                                                                   0
621daad67b5SFeifei Xu #define mmBIF_UVD_INTR_CNTL                                                                            0x0062 // duplicate
622daad67b5SFeifei Xu #define mmBIF_UVD_INTR_CNTL_BASE_IDX                                                                   0
623daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR0                                                                        0x0080 // duplicate
624daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX                                                               0
625daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR0                                                                  0x0081 // duplicate
626daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX                                                         0
627daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR1                                                                        0x0082 // duplicate
628daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX                                                               0
629daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR1                                                                  0x0083 // duplicate
630daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX                                                         0
631daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR2                                                                        0x0084 // duplicate
632daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX                                                               0
633daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR2                                                                  0x0085 // duplicate
634daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX                                                         0
635daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR3                                                                        0x0086 // duplicate
636daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX                                                               0
637daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR3                                                                  0x0087 // duplicate
638daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX                                                         0
639daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR4                                                                        0x0088 // duplicate
640daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX                                                               0
641daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR4                                                                  0x0089 // duplicate
642daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX                                                         0
643daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR5                                                                        0x008a // duplicate
644daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX                                                               0
645daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR5                                                                  0x008b // duplicate
646daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX                                                         0
647daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR6                                                                        0x008c // duplicate
648daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX                                                               0
649daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR6                                                                  0x008d // duplicate
650daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX                                                         0
651daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR7                                                                        0x008e // duplicate
652daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX                                                               0
653daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR7                                                                  0x008f // duplicate
654daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX                                                         0
655daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_CNTL                                                                         0x0090 // duplicate
656daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX                                                                0
657daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ZERO_CPL                                                                     0x0091 // duplicate
658daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX                                                            0
659daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ONE_CPL                                                                      0x0092 // duplicate
660daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX                                                             0
661daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL                                                             0x0093 // duplicate
662daad67b5SFeifei Xu #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX                                                    0
663daad67b5SFeifei Xu 
664daad67b5SFeifei Xu 
665daad67b5SFeifei Xu // addressBlock: bif_bx_pf_SYSPFVFDEC
666daad67b5SFeifei Xu // base address: 0x0
667daad67b5SFeifei Xu #define mmMM_INDEX                                                                                     0x0000 // duplicate
668daad67b5SFeifei Xu #define mmMM_INDEX_BASE_IDX                                                                            0
669daad67b5SFeifei Xu #define mmMM_DATA                                                                                      0x0001 // duplicate
670daad67b5SFeifei Xu #define mmMM_DATA_BASE_IDX                                                                             0
671daad67b5SFeifei Xu #define mmMM_INDEX_HI                                                                                  0x0006 // duplicate
672daad67b5SFeifei Xu #define mmMM_INDEX_HI_BASE_IDX                                                                         0
673daad67b5SFeifei Xu #define mmSYSHUB_INDEX_OVLP                                                                            0x0008 // duplicate
674daad67b5SFeifei Xu #define mmSYSHUB_INDEX_OVLP_BASE_IDX                                                                   0
675daad67b5SFeifei Xu #define mmSYSHUB_DATA_OVLP                                                                             0x0009 // duplicate
676daad67b5SFeifei Xu #define mmSYSHUB_DATA_OVLP_BASE_IDX                                                                    0
677daad67b5SFeifei Xu #define mmPCIE_INDEX                                                                                   0x000c // duplicate
678daad67b5SFeifei Xu #define mmPCIE_INDEX_BASE_IDX                                                                          0
679daad67b5SFeifei Xu #define mmPCIE_DATA                                                                                    0x000d // duplicate
680daad67b5SFeifei Xu #define mmPCIE_DATA_BASE_IDX                                                                           0
681daad67b5SFeifei Xu #define mmPCIE_INDEX2                                                                                  0x000e // duplicate
682daad67b5SFeifei Xu #define mmPCIE_INDEX2_BASE_IDX                                                                         0
683daad67b5SFeifei Xu #define mmPCIE_DATA2                                                                                   0x000f // duplicate
684daad67b5SFeifei Xu #define mmPCIE_DATA2_BASE_IDX                                                                          0
685daad67b5SFeifei Xu 
686daad67b5SFeifei Xu 
687daad67b5SFeifei Xu // addressBlock: rcc_dwn_BIFDEC1
688daad67b5SFeifei Xu // base address: 0x0
689daad67b5SFeifei Xu #define mmDN_PCIE_RESERVED                                                                             0x0d60 // duplicate
690daad67b5SFeifei Xu #define mmDN_PCIE_RESERVED_BASE_IDX                                                                    0
691daad67b5SFeifei Xu #define mmDN_PCIE_SCRATCH                                                                              0x0d61 // duplicate
692daad67b5SFeifei Xu #define mmDN_PCIE_SCRATCH_BASE_IDX                                                                     0
693daad67b5SFeifei Xu #define mmDN_PCIE_CNTL                                                                                 0x0d63 // duplicate
694daad67b5SFeifei Xu #define mmDN_PCIE_CNTL_BASE_IDX                                                                        0
695daad67b5SFeifei Xu #define mmDN_PCIE_CONFIG_CNTL                                                                          0x0d64 // duplicate
696daad67b5SFeifei Xu #define mmDN_PCIE_CONFIG_CNTL_BASE_IDX                                                                 0
697daad67b5SFeifei Xu #define mmDN_PCIE_RX_CNTL2                                                                             0x0d65 // duplicate
698daad67b5SFeifei Xu #define mmDN_PCIE_RX_CNTL2_BASE_IDX                                                                    0
699daad67b5SFeifei Xu #define mmDN_PCIE_BUS_CNTL                                                                             0x0d66 // duplicate
700daad67b5SFeifei Xu #define mmDN_PCIE_BUS_CNTL_BASE_IDX                                                                    0
701daad67b5SFeifei Xu #define mmDN_PCIE_CFG_CNTL                                                                             0x0d67 // duplicate
702daad67b5SFeifei Xu #define mmDN_PCIE_CFG_CNTL_BASE_IDX                                                                    0
703daad67b5SFeifei Xu #define mmDN_PCIE_STRAP_F0                                                                             0x0d68 // duplicate
704daad67b5SFeifei Xu #define mmDN_PCIE_STRAP_F0_BASE_IDX                                                                    0
705daad67b5SFeifei Xu #define mmDN_PCIE_STRAP_MISC                                                                           0x0d69 // duplicate
706daad67b5SFeifei Xu #define mmDN_PCIE_STRAP_MISC_BASE_IDX                                                                  0
707daad67b5SFeifei Xu #define mmDN_PCIE_STRAP_MISC2                                                                          0x0d6a // duplicate
708daad67b5SFeifei Xu #define mmDN_PCIE_STRAP_MISC2_BASE_IDX                                                                 0
709daad67b5SFeifei Xu 
710daad67b5SFeifei Xu 
711daad67b5SFeifei Xu // addressBlock: rcc_dwnp_BIFDEC1
712daad67b5SFeifei Xu // base address: 0x0
713daad67b5SFeifei Xu #define mmPCIEP_RESERVED                                                                               0x0d6c // duplicate
714daad67b5SFeifei Xu #define mmPCIEP_RESERVED_BASE_IDX                                                                      0
715daad67b5SFeifei Xu #define mmPCIEP_SCRATCH                                                                                0x0d6d // duplicate
716daad67b5SFeifei Xu #define mmPCIEP_SCRATCH_BASE_IDX                                                                       0
717daad67b5SFeifei Xu #define mmPCIE_ERR_CNTL                                                                                0x0d6f // duplicate
718daad67b5SFeifei Xu #define mmPCIE_ERR_CNTL_BASE_IDX                                                                       0
719daad67b5SFeifei Xu #define mmPCIE_RX_CNTL                                                                                 0x0d70 // duplicate
720daad67b5SFeifei Xu #define mmPCIE_RX_CNTL_BASE_IDX                                                                        0
721daad67b5SFeifei Xu #define mmPCIE_LC_SPEED_CNTL                                                                           0x0d71 // duplicate
722daad67b5SFeifei Xu #define mmPCIE_LC_SPEED_CNTL_BASE_IDX                                                                  0
723daad67b5SFeifei Xu #define mmPCIE_LC_CNTL2                                                                                0x0d72 // duplicate
724daad67b5SFeifei Xu #define mmPCIE_LC_CNTL2_BASE_IDX                                                                       0
725daad67b5SFeifei Xu #define mmPCIEP_STRAP_MISC                                                                             0x0d73 // duplicate
726daad67b5SFeifei Xu #define mmPCIEP_STRAP_MISC_BASE_IDX                                                                    0
727daad67b5SFeifei Xu #define mmLTR_MSG_INFO_FROM_EP                                                                         0x0d74 // duplicate
728daad67b5SFeifei Xu #define mmLTR_MSG_INFO_FROM_EP_BASE_IDX                                                                0
729daad67b5SFeifei Xu 
730daad67b5SFeifei Xu 
731daad67b5SFeifei Xu // addressBlock: rcc_ep_BIFDEC1
732daad67b5SFeifei Xu // base address: 0x0
733daad67b5SFeifei Xu #define mmEP_PCIE_SCRATCH                                                                              0x0d43 // duplicate
734daad67b5SFeifei Xu #define mmEP_PCIE_SCRATCH_BASE_IDX                                                                     0
735daad67b5SFeifei Xu #define mmEP_PCIE_CNTL                                                                                 0x0d45 // duplicate
736daad67b5SFeifei Xu #define mmEP_PCIE_CNTL_BASE_IDX                                                                        0
737daad67b5SFeifei Xu #define mmEP_PCIE_INT_CNTL                                                                             0x0d46 // duplicate
738daad67b5SFeifei Xu #define mmEP_PCIE_INT_CNTL_BASE_IDX                                                                    0
739daad67b5SFeifei Xu #define mmEP_PCIE_INT_STATUS                                                                           0x0d47 // duplicate
740daad67b5SFeifei Xu #define mmEP_PCIE_INT_STATUS_BASE_IDX                                                                  0
741daad67b5SFeifei Xu #define mmEP_PCIE_RX_CNTL2                                                                             0x0d48 // duplicate
742daad67b5SFeifei Xu #define mmEP_PCIE_RX_CNTL2_BASE_IDX                                                                    0
743daad67b5SFeifei Xu #define mmEP_PCIE_BUS_CNTL                                                                             0x0d49 // duplicate
744daad67b5SFeifei Xu #define mmEP_PCIE_BUS_CNTL_BASE_IDX                                                                    0
745daad67b5SFeifei Xu #define mmEP_PCIE_CFG_CNTL                                                                             0x0d4a // duplicate
746daad67b5SFeifei Xu #define mmEP_PCIE_CFG_CNTL_BASE_IDX                                                                    0
747daad67b5SFeifei Xu #define mmEP_PCIE_OBFF_CNTL                                                                            0x0d4b // duplicate
748daad67b5SFeifei Xu #define mmEP_PCIE_OBFF_CNTL_BASE_IDX                                                                   0
749daad67b5SFeifei Xu #define mmEP_PCIE_TX_LTR_CNTL                                                                          0x0d4c // duplicate
750daad67b5SFeifei Xu #define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX                                                                 0
751daad67b5SFeifei Xu #define mmEP_PCIE_STRAP_MISC                                                                           0x0d4f // duplicate
752daad67b5SFeifei Xu #define mmEP_PCIE_STRAP_MISC_BASE_IDX                                                                  0
753daad67b5SFeifei Xu #define mmEP_PCIE_STRAP_MISC2                                                                          0x0d50 // duplicate
754daad67b5SFeifei Xu #define mmEP_PCIE_STRAP_MISC2_BASE_IDX                                                                 0
755daad67b5SFeifei Xu #define mmEP_PCIE_STRAP_PI                                                                             0x0d51 // duplicate
756daad67b5SFeifei Xu #define mmEP_PCIE_STRAP_PI_BASE_IDX                                                                    0
757daad67b5SFeifei Xu #define mmEP_PCIE_F0_DPA_CAP                                                                           0x0d52 // duplicate
758daad67b5SFeifei Xu #define mmEP_PCIE_F0_DPA_CAP_BASE_IDX                                                                  0
759daad67b5SFeifei Xu #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR                                                             0x0d53 // duplicate
760daad67b5SFeifei Xu #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX                                                    0
761daad67b5SFeifei Xu #define mmEP_PCIE_F0_DPA_CNTL                                                                          0x0d53 // duplicate
762daad67b5SFeifei Xu #define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX                                                                 0
763daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                                             0x0d53 // duplicate
764daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                                    0
765daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                                             0x0d54 // duplicate
766daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                                    0
767daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                                             0x0d54 // duplicate
768daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                                    0
769daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                                             0x0d54 // duplicate
770daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                                    0
771daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                                             0x0d54 // duplicate
772daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                                    0
773daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                                             0x0d55 // duplicate
774daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                                    0
775daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                                             0x0d55 // duplicate
776daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                                    0
777daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                                             0x0d55 // duplicate
778daad67b5SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                                    0
779daad67b5SFeifei Xu #define mmEP_PCIE_PME_CONTROL                                                                          0x0d55 // duplicate
780daad67b5SFeifei Xu #define mmEP_PCIE_PME_CONTROL_BASE_IDX                                                                 0
781daad67b5SFeifei Xu #define mmEP_PCIEP_RESERVED                                                                            0x0d56 // duplicate
782daad67b5SFeifei Xu #define mmEP_PCIEP_RESERVED_BASE_IDX                                                                   0
783daad67b5SFeifei Xu #define mmEP_PCIE_TX_CNTL                                                                              0x0d58 // duplicate
784daad67b5SFeifei Xu #define mmEP_PCIE_TX_CNTL_BASE_IDX                                                                     0
785daad67b5SFeifei Xu #define mmEP_PCIE_TX_REQUESTER_ID                                                                      0x0d59 // duplicate
786daad67b5SFeifei Xu #define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX                                                             0
787daad67b5SFeifei Xu #define mmEP_PCIE_ERR_CNTL                                                                             0x0d5a // duplicate
788daad67b5SFeifei Xu #define mmEP_PCIE_ERR_CNTL_BASE_IDX                                                                    0
789daad67b5SFeifei Xu #define mmEP_PCIE_RX_CNTL                                                                              0x0d5b // duplicate
790daad67b5SFeifei Xu #define mmEP_PCIE_RX_CNTL_BASE_IDX                                                                     0
791daad67b5SFeifei Xu #define mmEP_PCIE_LC_SPEED_CNTL                                                                        0x0d5c // duplicate
792daad67b5SFeifei Xu #define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX                                                               0
793daad67b5SFeifei Xu 
794daad67b5SFeifei Xu 
795daad67b5SFeifei Xu // addressBlock: bif_bx_pf_BIFDEC1
796daad67b5SFeifei Xu // base address: 0x0
797daad67b5SFeifei Xu #define mmBIF_MM_INDACCESS_CNTL                                                                        0x0e06 // duplicate
798daad67b5SFeifei Xu #define mmBIF_MM_INDACCESS_CNTL_BASE_IDX                                                               0
799daad67b5SFeifei Xu #define mmBUS_CNTL                                                                                     0x0e07 // duplicate
800daad67b5SFeifei Xu #define mmBUS_CNTL_BASE_IDX                                                                            0
801daad67b5SFeifei Xu #define mmBIF_SCRATCH0                                                                                 0x0e08 // duplicate
802daad67b5SFeifei Xu #define mmBIF_SCRATCH0_BASE_IDX                                                                        0
803daad67b5SFeifei Xu #define mmBIF_SCRATCH1                                                                                 0x0e09 // duplicate
804daad67b5SFeifei Xu #define mmBIF_SCRATCH1_BASE_IDX                                                                        0
805daad67b5SFeifei Xu #define mmBX_RESET_EN                                                                                  0x0e0d // duplicate
806daad67b5SFeifei Xu #define mmBX_RESET_EN_BASE_IDX                                                                         0
807daad67b5SFeifei Xu #define mmMM_CFGREGS_CNTL                                                                              0x0e0e // duplicate
808daad67b5SFeifei Xu #define mmMM_CFGREGS_CNTL_BASE_IDX                                                                     0
809daad67b5SFeifei Xu #define mmBX_RESET_CNTL                                                                                0x0e10 // duplicate
810daad67b5SFeifei Xu #define mmBX_RESET_CNTL_BASE_IDX                                                                       0
811daad67b5SFeifei Xu #define mmINTERRUPT_CNTL                                                                               0x0e11 // duplicate
812daad67b5SFeifei Xu #define mmINTERRUPT_CNTL_BASE_IDX                                                                      0
813daad67b5SFeifei Xu #define mmINTERRUPT_CNTL2                                                                              0x0e12 // duplicate
814daad67b5SFeifei Xu #define mmINTERRUPT_CNTL2_BASE_IDX                                                                     0
815daad67b5SFeifei Xu #define mmCLKREQB_PAD_CNTL                                                                             0x0e18 // duplicate
816daad67b5SFeifei Xu #define mmCLKREQB_PAD_CNTL_BASE_IDX                                                                    0
817daad67b5SFeifei Xu #define mmCLKREQB_PERF_COUNTER                                                                         0x0e19 // duplicate
818daad67b5SFeifei Xu #define mmCLKREQB_PERF_COUNTER_BASE_IDX                                                                0
819daad67b5SFeifei Xu #define mmBIF_CLK_CTRL                                                                                 0x0e1a // duplicate
820daad67b5SFeifei Xu #define mmBIF_CLK_CTRL_BASE_IDX                                                                        0
821daad67b5SFeifei Xu #define mmBIF_FEATURES_CONTROL_MISC                                                                    0x0e1b // duplicate
822daad67b5SFeifei Xu #define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX                                                           0
823daad67b5SFeifei Xu #define mmBIF_DOORBELL_CNTL                                                                            0x0e1c // duplicate
824daad67b5SFeifei Xu #define mmBIF_DOORBELL_CNTL_BASE_IDX                                                                   0
825daad67b5SFeifei Xu #define mmBIF_DOORBELL_INT_CNTL                                                                        0x0e1d // duplicate
826daad67b5SFeifei Xu #define mmBIF_DOORBELL_INT_CNTL_BASE_IDX                                                               0
827daad67b5SFeifei Xu #define mmBIF_SLVARB_MODE                                                                              0x0e1e // duplicate
828daad67b5SFeifei Xu #define mmBIF_SLVARB_MODE_BASE_IDX                                                                     0
829daad67b5SFeifei Xu #define mmBIF_FB_EN                                                                                    0x0e1f // duplicate
830daad67b5SFeifei Xu #define mmBIF_FB_EN_BASE_IDX                                                                           0
831daad67b5SFeifei Xu #define mmBIF_BUSY_DELAY_CNTR                                                                          0x0e20 // duplicate
832daad67b5SFeifei Xu #define mmBIF_BUSY_DELAY_CNTR_BASE_IDX                                                                 0
833daad67b5SFeifei Xu #define mmBIF_PERFMON_CNTL                                                                             0x0e21 // duplicate
834daad67b5SFeifei Xu #define mmBIF_PERFMON_CNTL_BASE_IDX                                                                    0
835daad67b5SFeifei Xu #define mmBIF_PERFCOUNTER0_RESULT                                                                      0x0e22 // duplicate
836daad67b5SFeifei Xu #define mmBIF_PERFCOUNTER0_RESULT_BASE_IDX                                                             0
837daad67b5SFeifei Xu #define mmBIF_PERFCOUNTER1_RESULT                                                                      0x0e23 // duplicate
838daad67b5SFeifei Xu #define mmBIF_PERFCOUNTER1_RESULT_BASE_IDX                                                             0
839daad67b5SFeifei Xu #define mmBIF_MST_TRANS_PENDING_VF                                                                     0x0e29 // duplicate
840daad67b5SFeifei Xu #define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX                                                            0
841daad67b5SFeifei Xu #define mmBIF_SLV_TRANS_PENDING_VF                                                                     0x0e2a // duplicate
842daad67b5SFeifei Xu #define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX                                                            0
843daad67b5SFeifei Xu #define mmBACO_CNTL                                                                                    0x0e2b // duplicate
844daad67b5SFeifei Xu #define mmBACO_CNTL_BASE_IDX                                                                           0
845daad67b5SFeifei Xu #define mmBIF_BACO_EXIT_TIME0                                                                          0x0e2c // duplicate
846daad67b5SFeifei Xu #define mmBIF_BACO_EXIT_TIME0_BASE_IDX                                                                 0
847daad67b5SFeifei Xu #define mmBIF_BACO_EXIT_TIMER1                                                                         0x0e2d // duplicate
848daad67b5SFeifei Xu #define mmBIF_BACO_EXIT_TIMER1_BASE_IDX                                                                0
849daad67b5SFeifei Xu #define mmBIF_BACO_EXIT_TIMER2                                                                         0x0e2e // duplicate
850daad67b5SFeifei Xu #define mmBIF_BACO_EXIT_TIMER2_BASE_IDX                                                                0
851daad67b5SFeifei Xu #define mmBIF_BACO_EXIT_TIMER3                                                                         0x0e2f // duplicate
852daad67b5SFeifei Xu #define mmBIF_BACO_EXIT_TIMER3_BASE_IDX                                                                0
853daad67b5SFeifei Xu #define mmBIF_BACO_EXIT_TIMER4                                                                         0x0e30 // duplicate
854daad67b5SFeifei Xu #define mmBIF_BACO_EXIT_TIMER4_BASE_IDX                                                                0
855daad67b5SFeifei Xu #define mmMEM_TYPE_CNTL                                                                                0x0e31 // duplicate
856daad67b5SFeifei Xu #define mmMEM_TYPE_CNTL_BASE_IDX                                                                       0
857daad67b5SFeifei Xu #define mmSMU_BIF_VDDGFX_PWR_STATUS                                                                    0x0e33 // duplicate
858daad67b5SFeifei Xu #define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX                                                           0
859daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX0_LOWER                                                                        0x0e34 // duplicate
860daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX0_LOWER_BASE_IDX                                                               0
861daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX0_UPPER                                                                        0x0e35 // duplicate
862daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX0_UPPER_BASE_IDX                                                               0
863daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX1_LOWER                                                                        0x0e36 // duplicate
864daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX1_LOWER_BASE_IDX                                                               0
865daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX1_UPPER                                                                        0x0e37 // duplicate
866daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX1_UPPER_BASE_IDX                                                               0
867daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX2_LOWER                                                                        0x0e38 // duplicate
868daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX2_LOWER_BASE_IDX                                                               0
869daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX2_UPPER                                                                        0x0e39 // duplicate
870daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX2_UPPER_BASE_IDX                                                               0
871daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX3_LOWER                                                                        0x0e3a // duplicate
872daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX3_LOWER_BASE_IDX                                                               0
873daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX3_UPPER                                                                        0x0e3b // duplicate
874daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX3_UPPER_BASE_IDX                                                               0
875daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX4_LOWER                                                                        0x0e3c // duplicate
876daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX4_LOWER_BASE_IDX                                                               0
877daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX4_UPPER                                                                        0x0e3d // duplicate
878daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX4_UPPER_BASE_IDX                                                               0
879daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX5_LOWER                                                                        0x0e3e // duplicate
880daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX5_LOWER_BASE_IDX                                                               0
881daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX5_UPPER                                                                        0x0e3f // duplicate
882daad67b5SFeifei Xu #define mmBIF_VDDGFX_GFX5_UPPER_BASE_IDX                                                               0
883daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV1_LOWER                                                                        0x0e40 // duplicate
884daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV1_LOWER_BASE_IDX                                                               0
885daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV1_UPPER                                                                        0x0e41 // duplicate
886daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV1_UPPER_BASE_IDX                                                               0
887daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV2_LOWER                                                                        0x0e42 // duplicate
888daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV2_LOWER_BASE_IDX                                                               0
889daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV2_UPPER                                                                        0x0e43 // duplicate
890daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV2_UPPER_BASE_IDX                                                               0
891daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV3_LOWER                                                                        0x0e44 // duplicate
892daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV3_LOWER_BASE_IDX                                                               0
893daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV3_UPPER                                                                        0x0e45 // duplicate
894daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV3_UPPER_BASE_IDX                                                               0
895daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV4_LOWER                                                                        0x0e46 // duplicate
896daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV4_LOWER_BASE_IDX                                                               0
897daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV4_UPPER                                                                        0x0e47 // duplicate
898daad67b5SFeifei Xu #define mmBIF_VDDGFX_RSV4_UPPER_BASE_IDX                                                               0
899daad67b5SFeifei Xu #define mmBIF_VDDGFX_FB_CMP                                                                            0x0e48 // duplicate
900daad67b5SFeifei Xu #define mmBIF_VDDGFX_FB_CMP_BASE_IDX                                                                   0
901daad67b5SFeifei Xu #define mmBIF_DOORBELL_GBLAPER1_LOWER                                                                  0x0e49 // duplicate
902daad67b5SFeifei Xu #define mmBIF_DOORBELL_GBLAPER1_LOWER_BASE_IDX                                                         0
903daad67b5SFeifei Xu #define mmBIF_DOORBELL_GBLAPER1_UPPER                                                                  0x0e4a // duplicate
904daad67b5SFeifei Xu #define mmBIF_DOORBELL_GBLAPER1_UPPER_BASE_IDX                                                         0
905daad67b5SFeifei Xu #define mmBIF_DOORBELL_GBLAPER2_LOWER                                                                  0x0e4b // duplicate
906daad67b5SFeifei Xu #define mmBIF_DOORBELL_GBLAPER2_LOWER_BASE_IDX                                                         0
907daad67b5SFeifei Xu #define mmBIF_DOORBELL_GBLAPER2_UPPER                                                                  0x0e4c // duplicate
908daad67b5SFeifei Xu #define mmBIF_DOORBELL_GBLAPER2_UPPER_BASE_IDX                                                         0
909daad67b5SFeifei Xu #define mmREMAP_HDP_MEM_FLUSH_CNTL                                                                     0x0e4d // duplicate
910daad67b5SFeifei Xu #define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX                                                            0
911daad67b5SFeifei Xu #define mmREMAP_HDP_REG_FLUSH_CNTL                                                                     0x0e4e // duplicate
912daad67b5SFeifei Xu #define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX                                                            0
913daad67b5SFeifei Xu #define mmBIF_RB_CNTL                                                                                  0x0e4f // duplicate
914daad67b5SFeifei Xu #define mmBIF_RB_CNTL_BASE_IDX                                                                         0
915daad67b5SFeifei Xu #define mmBIF_RB_BASE                                                                                  0x0e50 // duplicate
916daad67b5SFeifei Xu #define mmBIF_RB_BASE_BASE_IDX                                                                         0
917daad67b5SFeifei Xu #define mmBIF_RB_RPTR                                                                                  0x0e51 // duplicate
918daad67b5SFeifei Xu #define mmBIF_RB_RPTR_BASE_IDX                                                                         0
919daad67b5SFeifei Xu #define mmBIF_RB_WPTR                                                                                  0x0e52 // duplicate
920daad67b5SFeifei Xu #define mmBIF_RB_WPTR_BASE_IDX                                                                         0
921daad67b5SFeifei Xu #define mmBIF_RB_WPTR_ADDR_HI                                                                          0x0e53 // duplicate
922daad67b5SFeifei Xu #define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX                                                                 0
923daad67b5SFeifei Xu #define mmBIF_RB_WPTR_ADDR_LO                                                                          0x0e54 // duplicate
924daad67b5SFeifei Xu #define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX                                                                 0
925daad67b5SFeifei Xu #define mmMAILBOX_INDEX                                                                                0x0e55 // duplicate
926daad67b5SFeifei Xu #define mmMAILBOX_INDEX_BASE_IDX                                                                       0
927daad67b5SFeifei Xu #define mmBIF_GPUIOV_RESET_NOTIFICATION                                                                0x0e62 // duplicate
928daad67b5SFeifei Xu #define mmBIF_GPUIOV_RESET_NOTIFICATION_BASE_IDX                                                       0
929daad67b5SFeifei Xu #define mmBIF_UVD_GPUIOV_CFG_SIZE                                                                      0x0e63 // duplicate
930daad67b5SFeifei Xu #define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX                                                             0
931daad67b5SFeifei Xu #define mmBIF_VCE_GPUIOV_CFG_SIZE                                                                      0x0e64 // duplicate
932daad67b5SFeifei Xu #define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX                                                             0
933daad67b5SFeifei Xu #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE                                                                 0x0e65 // duplicate
934daad67b5SFeifei Xu #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX                                                        0
935daad67b5SFeifei Xu #define mmBIF_GMI_WRR_WEIGHT                                                                           0x0e66 // duplicate
936daad67b5SFeifei Xu #define mmBIF_GMI_WRR_WEIGHT_BASE_IDX                                                                  0
937daad67b5SFeifei Xu #define mmNBIF_STRAP_WRITE_CTRL                                                                        0x0e67 // duplicate
938daad67b5SFeifei Xu #define mmNBIF_STRAP_WRITE_CTRL_BASE_IDX                                                               0
939daad67b5SFeifei Xu #define mmBIF_PERSTB_PAD_CNTL                                                                          0x0e68 // duplicate
940daad67b5SFeifei Xu #define mmBIF_PERSTB_PAD_CNTL_BASE_IDX                                                                 0
941daad67b5SFeifei Xu #define mmBIF_PX_EN_PAD_CNTL                                                                           0x0e69 // duplicate
942daad67b5SFeifei Xu #define mmBIF_PX_EN_PAD_CNTL_BASE_IDX                                                                  0
943daad67b5SFeifei Xu #define mmBIF_REFPADKIN_PAD_CNTL                                                                       0x0e6a // duplicate
944daad67b5SFeifei Xu #define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX                                                              0
945daad67b5SFeifei Xu #define mmBIF_CLKREQB_PAD_CNTL                                                                         0x0e6b // duplicate
946daad67b5SFeifei Xu #define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX                                                                0
947daad67b5SFeifei Xu 
948daad67b5SFeifei Xu 
949daad67b5SFeifei Xu // addressBlock: rcc_pf_0_BIFDEC1
950daad67b5SFeifei Xu // base address: 0x0
951daad67b5SFeifei Xu #define mmRCC_BACO_CNTL_MISC                                                                           0x0da7 // duplicate
952daad67b5SFeifei Xu #define mmRCC_BACO_CNTL_MISC_BASE_IDX                                                                  0
953daad67b5SFeifei Xu #define mmRCC_RESET_EN                                                                                 0x0da8 // duplicate
954daad67b5SFeifei Xu #define mmRCC_RESET_EN_BASE_IDX                                                                        0
955daad67b5SFeifei Xu #define mmRCC_VDM_SUPPORT                                                                              0x0da9 // duplicate
956daad67b5SFeifei Xu #define mmRCC_VDM_SUPPORT_BASE_IDX                                                                     0
957daad67b5SFeifei Xu #define mmRCC_PEER_REG_RANGE0                                                                          0x0dde // duplicate
958daad67b5SFeifei Xu #define mmRCC_PEER_REG_RANGE0_BASE_IDX                                                                 0
959daad67b5SFeifei Xu #define mmRCC_PEER_REG_RANGE1                                                                          0x0ddf // duplicate
960daad67b5SFeifei Xu #define mmRCC_PEER_REG_RANGE1_BASE_IDX                                                                 0
961daad67b5SFeifei Xu #define mmRCC_BUS_CNTL                                                                                 0x0de1 // duplicate
962daad67b5SFeifei Xu #define mmRCC_BUS_CNTL_BASE_IDX                                                                        0
963daad67b5SFeifei Xu #define mmRCC_CONFIG_CNTL                                                                              0x0de2 // duplicate
964daad67b5SFeifei Xu #define mmRCC_CONFIG_CNTL_BASE_IDX                                                                     0
965daad67b5SFeifei Xu #define mmRCC_CONFIG_F0_BASE                                                                           0x0de6 // duplicate
966daad67b5SFeifei Xu #define mmRCC_CONFIG_F0_BASE_BASE_IDX                                                                  0
967daad67b5SFeifei Xu #define mmRCC_CONFIG_APER_SIZE                                                                         0x0de7 // duplicate
968daad67b5SFeifei Xu #define mmRCC_CONFIG_APER_SIZE_BASE_IDX                                                                0
969daad67b5SFeifei Xu #define mmRCC_CONFIG_REG_APER_SIZE                                                                     0x0de8 // duplicate
970daad67b5SFeifei Xu #define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX                                                            0
971daad67b5SFeifei Xu #define mmRCC_XDMA_LO                                                                                  0x0de9 // duplicate
972daad67b5SFeifei Xu #define mmRCC_XDMA_LO_BASE_IDX                                                                         0
973daad67b5SFeifei Xu #define mmRCC_XDMA_HI                                                                                  0x0dea // duplicate
974daad67b5SFeifei Xu #define mmRCC_XDMA_HI_BASE_IDX                                                                         0
975daad67b5SFeifei Xu #define mmRCC_FEATURES_CONTROL_MISC                                                                    0x0deb // duplicate
976daad67b5SFeifei Xu #define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX                                                           0
977daad67b5SFeifei Xu #define mmRCC_BUSNUM_CNTL1                                                                             0x0dec // duplicate
978daad67b5SFeifei Xu #define mmRCC_BUSNUM_CNTL1_BASE_IDX                                                                    0
979daad67b5SFeifei Xu #define mmRCC_BUSNUM_LIST0                                                                             0x0ded // duplicate
980daad67b5SFeifei Xu #define mmRCC_BUSNUM_LIST0_BASE_IDX                                                                    0
981daad67b5SFeifei Xu #define mmRCC_BUSNUM_LIST1                                                                             0x0dee // duplicate
982daad67b5SFeifei Xu #define mmRCC_BUSNUM_LIST1_BASE_IDX                                                                    0
983daad67b5SFeifei Xu #define mmRCC_BUSNUM_CNTL2                                                                             0x0def // duplicate
984daad67b5SFeifei Xu #define mmRCC_BUSNUM_CNTL2_BASE_IDX                                                                    0
985daad67b5SFeifei Xu #define mmRCC_CAPTURE_HOST_BUSNUM                                                                      0x0df0 // duplicate
986daad67b5SFeifei Xu #define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX                                                             0
987daad67b5SFeifei Xu #define mmRCC_HOST_BUSNUM                                                                              0x0df1 // duplicate
988daad67b5SFeifei Xu #define mmRCC_HOST_BUSNUM_BASE_IDX                                                                     0
989daad67b5SFeifei Xu #define mmRCC_PEER0_FB_OFFSET_HI                                                                       0x0df2 // duplicate
990daad67b5SFeifei Xu #define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX                                                              0
991daad67b5SFeifei Xu #define mmRCC_PEER0_FB_OFFSET_LO                                                                       0x0df3 // duplicate
992daad67b5SFeifei Xu #define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX                                                              0
993daad67b5SFeifei Xu #define mmRCC_PEER1_FB_OFFSET_HI                                                                       0x0df4 // duplicate
994daad67b5SFeifei Xu #define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX                                                              0
995daad67b5SFeifei Xu #define mmRCC_PEER1_FB_OFFSET_LO                                                                       0x0df5 // duplicate
996daad67b5SFeifei Xu #define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX                                                              0
997daad67b5SFeifei Xu #define mmRCC_PEER2_FB_OFFSET_HI                                                                       0x0df6 // duplicate
998daad67b5SFeifei Xu #define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX                                                              0
999daad67b5SFeifei Xu #define mmRCC_PEER2_FB_OFFSET_LO                                                                       0x0df7 // duplicate
1000daad67b5SFeifei Xu #define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX                                                              0
1001daad67b5SFeifei Xu #define mmRCC_PEER3_FB_OFFSET_HI                                                                       0x0df8 // duplicate
1002daad67b5SFeifei Xu #define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX                                                              0
1003daad67b5SFeifei Xu #define mmRCC_PEER3_FB_OFFSET_LO                                                                       0x0df9 // duplicate
1004daad67b5SFeifei Xu #define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX                                                              0
1005daad67b5SFeifei Xu #define mmRCC_DEVFUNCNUM_LIST0                                                                         0x0dfa // duplicate
1006daad67b5SFeifei Xu #define mmRCC_DEVFUNCNUM_LIST0_BASE_IDX                                                                0
1007daad67b5SFeifei Xu #define mmRCC_DEVFUNCNUM_LIST1                                                                         0x0dfb // duplicate
1008daad67b5SFeifei Xu #define mmRCC_DEVFUNCNUM_LIST1_BASE_IDX                                                                0
1009daad67b5SFeifei Xu #define mmRCC_DEV0_LINK_CNTL                                                                           0x0dfd // duplicate
1010daad67b5SFeifei Xu #define mmRCC_DEV0_LINK_CNTL_BASE_IDX                                                                  0
1011daad67b5SFeifei Xu #define mmRCC_CMN_LINK_CNTL                                                                            0x0dfe // duplicate
1012daad67b5SFeifei Xu #define mmRCC_CMN_LINK_CNTL_BASE_IDX                                                                   0
1013daad67b5SFeifei Xu #define mmRCC_EP_REQUESTERID_RESTORE                                                                   0x0dff // duplicate
1014daad67b5SFeifei Xu #define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX                                                          0
1015daad67b5SFeifei Xu #define mmRCC_LTR_LSWITCH_CNTL                                                                         0x0e00 // duplicate
1016daad67b5SFeifei Xu #define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX                                                                0
1017daad67b5SFeifei Xu #define mmRCC_MH_ARB_CNTL                                                                              0x0e01 // duplicate
1018daad67b5SFeifei Xu #define mmRCC_MH_ARB_CNTL_BASE_IDX                                                                     0
1019daad67b5SFeifei Xu 
1020daad67b5SFeifei Xu 
1021daad67b5SFeifei Xu // addressBlock: rcc_pf_0_BIFDEC2
1022daad67b5SFeifei Xu // base address: 0x0
1023daad67b5SFeifei Xu #define mmGFXMSIX_VECT0_ADDR_LO                                                                        0x10800 // duplicate
1024daad67b5SFeifei Xu #define mmGFXMSIX_VECT0_ADDR_LO_BASE_IDX                                                               0
1025daad67b5SFeifei Xu #define mmGFXMSIX_VECT0_ADDR_HI                                                                        0x10801 // duplicate
1026daad67b5SFeifei Xu #define mmGFXMSIX_VECT0_ADDR_HI_BASE_IDX                                                               0
1027daad67b5SFeifei Xu #define mmGFXMSIX_VECT0_MSG_DATA                                                                       0x10802 // duplicate
1028daad67b5SFeifei Xu #define mmGFXMSIX_VECT0_MSG_DATA_BASE_IDX                                                              0
1029daad67b5SFeifei Xu #define mmGFXMSIX_VECT0_CONTROL                                                                        0x10803 // duplicate
1030daad67b5SFeifei Xu #define mmGFXMSIX_VECT0_CONTROL_BASE_IDX                                                               0
1031daad67b5SFeifei Xu #define mmGFXMSIX_VECT1_ADDR_LO                                                                        0x10804 // duplicate
1032daad67b5SFeifei Xu #define mmGFXMSIX_VECT1_ADDR_LO_BASE_IDX                                                               0
1033daad67b5SFeifei Xu #define mmGFXMSIX_VECT1_ADDR_HI                                                                        0x10805 // duplicate
1034daad67b5SFeifei Xu #define mmGFXMSIX_VECT1_ADDR_HI_BASE_IDX                                                               0
1035daad67b5SFeifei Xu #define mmGFXMSIX_VECT1_MSG_DATA                                                                       0x10806 // duplicate
1036daad67b5SFeifei Xu #define mmGFXMSIX_VECT1_MSG_DATA_BASE_IDX                                                              0
1037daad67b5SFeifei Xu #define mmGFXMSIX_VECT1_CONTROL                                                                        0x10807 // duplicate
1038daad67b5SFeifei Xu #define mmGFXMSIX_VECT1_CONTROL_BASE_IDX                                                               0
1039daad67b5SFeifei Xu #define mmGFXMSIX_VECT2_ADDR_LO                                                                        0x10808 // duplicate
1040daad67b5SFeifei Xu #define mmGFXMSIX_VECT2_ADDR_LO_BASE_IDX                                                               0
1041daad67b5SFeifei Xu #define mmGFXMSIX_VECT2_ADDR_HI                                                                        0x10809 // duplicate
1042daad67b5SFeifei Xu #define mmGFXMSIX_VECT2_ADDR_HI_BASE_IDX                                                               0
1043daad67b5SFeifei Xu #define mmGFXMSIX_VECT2_MSG_DATA                                                                       0x1080a // duplicate
1044daad67b5SFeifei Xu #define mmGFXMSIX_VECT2_MSG_DATA_BASE_IDX                                                              0
1045daad67b5SFeifei Xu #define mmGFXMSIX_VECT2_CONTROL                                                                        0x1080b // duplicate
1046daad67b5SFeifei Xu #define mmGFXMSIX_VECT2_CONTROL_BASE_IDX                                                               0
1047daad67b5SFeifei Xu #define mmGFXMSIX_PBA                                                                                  0x10c00 // duplicate
1048daad67b5SFeifei Xu #define mmGFXMSIX_PBA_BASE_IDX                                                                         0
1049daad67b5SFeifei Xu 
1050daad67b5SFeifei Xu 
1051daad67b5SFeifei Xu // addressBlock: rcc_strap_BIFDEC1
1052daad67b5SFeifei Xu // base address: 0x0
1053daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP0                                                                         0x0d27 // duplicate
1054daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP0_BASE_IDX                                                                0
1055daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP1                                                                         0x0d28 // duplicate
1056daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP1_BASE_IDX                                                                0
1057daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP2                                                                         0x0d29 // duplicate
1058daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP2_BASE_IDX                                                                0
1059daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP3                                                                         0x0d2a // duplicate
1060daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP3_BASE_IDX                                                                0
1061daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP4                                                                         0x0d2b // duplicate
1062daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP4_BASE_IDX                                                                0
1063daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP5                                                                         0x0d2c // duplicate
1064daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP5_BASE_IDX                                                                0
1065daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP6                                                                         0x0d2d // duplicate
1066daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP6_BASE_IDX                                                                0
1067daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP7                                                                         0x0d2e // duplicate
1068daad67b5SFeifei Xu #define mmRCC_DEV0_PORT_STRAP7_BASE_IDX                                                                0
1069daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP0                                                                         0x0d2f // duplicate
1070daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX                                                                0
1071daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP1                                                                         0x0d30 // duplicate
1072daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP1_BASE_IDX                                                                0
1073daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP13                                                                        0x0d31 // duplicate
1074daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP13_BASE_IDX                                                               0
1075daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP2                                                                         0x0d32 // duplicate
1076daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP2_BASE_IDX                                                                0
1077daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP3                                                                         0x0d33 // duplicate
1078daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP3_BASE_IDX                                                                0
1079daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP4                                                                         0x0d34 // duplicate
1080daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP4_BASE_IDX                                                                0
1081daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP5                                                                         0x0d35 // duplicate
1082daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP5_BASE_IDX                                                                0
1083daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP8                                                                         0x0d36 // duplicate
1084daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP8_BASE_IDX                                                                0
1085daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP9                                                                         0x0d37 // duplicate
1086daad67b5SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP9_BASE_IDX                                                                0
1087daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP0                                                                         0x0d38 // duplicate
1088daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP0_BASE_IDX                                                                0
1089daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP10                                                                        0x0d39 // duplicate
1090daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP10_BASE_IDX                                                               0
1091daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP11                                                                        0x0d3a // duplicate
1092daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP11_BASE_IDX                                                               0
1093daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP12                                                                        0x0d3b // duplicate
1094daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP12_BASE_IDX                                                               0
1095daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP13                                                                        0x0d3c // duplicate
1096daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP13_BASE_IDX                                                               0
1097daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP2                                                                         0x0d3d // duplicate
1098daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP2_BASE_IDX                                                                0
1099daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP3                                                                         0x0d3e // duplicate
1100daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP3_BASE_IDX                                                                0
1101daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP4                                                                         0x0d3f // duplicate
1102daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP4_BASE_IDX                                                                0
1103daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP5                                                                         0x0d40 // duplicate
1104daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP5_BASE_IDX                                                                0
1105daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP6                                                                         0x0d41 // duplicate
1106daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP6_BASE_IDX                                                                0
1107daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP7                                                                         0x0d42 // duplicate
1108daad67b5SFeifei Xu #define mmRCC_DEV0_EPF1_STRAP7_BASE_IDX                                                                0
1109daad67b5SFeifei Xu 
1110daad67b5SFeifei Xu 
1111daad67b5SFeifei Xu // addressBlock: bif_bx_pf_BIFPFVFDEC1
1112daad67b5SFeifei Xu // base address: 0x0
1113daad67b5SFeifei Xu #define mmBIF_BME_STATUS                                                                               0x0e0b // duplicate
1114daad67b5SFeifei Xu #define mmBIF_BME_STATUS_BASE_IDX                                                                      0
1115daad67b5SFeifei Xu #define mmBIF_ATOMIC_ERR_LOG                                                                           0x0e0c // duplicate
1116daad67b5SFeifei Xu #define mmBIF_ATOMIC_ERR_LOG_BASE_IDX                                                                  0
1117daad67b5SFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH                                                         0x0e13 // duplicate
1118daad67b5SFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                                                0
1119daad67b5SFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW                                                          0x0e14 // duplicate
1120daad67b5SFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                                                 0
1121daad67b5SFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_CNTL                                                              0x0e15 // duplicate
1122daad67b5SFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                                     0
1123daad67b5SFeifei Xu #define mmHDP_REG_COHERENCY_FLUSH_CNTL                                                                 0x0e16 // duplicate
1124daad67b5SFeifei Xu #define mmHDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                                        0
1125daad67b5SFeifei Xu #define mmHDP_MEM_COHERENCY_FLUSH_CNTL                                                                 0x0e17 // duplicate
1126daad67b5SFeifei Xu #define mmHDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                                        0
1127daad67b5SFeifei Xu #define mmGPU_HDP_FLUSH_REQ                                                                            0x0e26 // duplicate
1128daad67b5SFeifei Xu #define mmGPU_HDP_FLUSH_REQ_BASE_IDX                                                                   0
1129daad67b5SFeifei Xu #define mmGPU_HDP_FLUSH_DONE                                                                           0x0e27 // duplicate
1130daad67b5SFeifei Xu #define mmGPU_HDP_FLUSH_DONE_BASE_IDX                                                                  0
1131daad67b5SFeifei Xu #define mmBIF_TRANS_PENDING                                                                            0x0e28 // duplicate
1132daad67b5SFeifei Xu #define mmBIF_TRANS_PENDING_BASE_IDX                                                                   0
1133daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW0                                                                       0x0e56 // duplicate
1134daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                                              0
1135daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW1                                                                       0x0e57 // duplicate
1136daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                                              0
1137daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW2                                                                       0x0e58 // duplicate
1138daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                                              0
1139daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW3                                                                       0x0e59 // duplicate
1140daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                                              0
1141daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW0                                                                       0x0e5a // duplicate
1142daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                                              0
1143daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW1                                                                       0x0e5b // duplicate
1144daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                                              0
1145daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW2                                                                       0x0e5c // duplicate
1146daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                                              0
1147daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW3                                                                       0x0e5d // duplicate
1148daad67b5SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                                              0
1149daad67b5SFeifei Xu #define mmMAILBOX_CONTROL                                                                              0x0e5e // duplicate
1150daad67b5SFeifei Xu #define mmMAILBOX_CONTROL_BASE_IDX                                                                     0
1151daad67b5SFeifei Xu #define mmMAILBOX_INT_CNTL                                                                             0x0e5f // duplicate
1152daad67b5SFeifei Xu #define mmMAILBOX_INT_CNTL_BASE_IDX                                                                    0
1153daad67b5SFeifei Xu #define mmBIF_VMHV_MAILBOX                                                                             0x0e60 // duplicate
1154daad67b5SFeifei Xu #define mmBIF_VMHV_MAILBOX_BASE_IDX                                                                    0
1155daad67b5SFeifei Xu 
1156daad67b5SFeifei Xu 
1157daad67b5SFeifei Xu // addressBlock: rcc_pf_0_BIFPFVFDEC1
1158daad67b5SFeifei Xu // base address: 0x0
1159daad67b5SFeifei Xu #define mmRCC_DOORBELL_APER_EN                                                                         0x0de0 // duplicate
1160daad67b5SFeifei Xu #define mmRCC_DOORBELL_APER_EN_BASE_IDX                                                                0
1161daad67b5SFeifei Xu #define mmRCC_CONFIG_MEMSIZE                                                                           0x0de3 // duplicate
1162daad67b5SFeifei Xu #define mmRCC_CONFIG_MEMSIZE_BASE_IDX                                                                  0
1163daad67b5SFeifei Xu #define mmRCC_CONFIG_RESERVED                                                                          0x0de4 // duplicate
1164daad67b5SFeifei Xu #define mmRCC_CONFIG_RESERVED_BASE_IDX                                                                 0
11653aa0115dSMonk Liu #ifndef mmRCC_IOV_FUNC_IDENTIFIER
1166daad67b5SFeifei Xu #define mmRCC_IOV_FUNC_IDENTIFIER                                                                      0x0de5 // duplicate
1167daad67b5SFeifei Xu #define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                                             0
11683aa0115dSMonk Liu #endif
1169daad67b5SFeifei Xu 
1170daad67b5SFeifei Xu 
1171daad67b5SFeifei Xu // addressBlock: syshub_mmreg_ind_syshubdec
1172daad67b5SFeifei Xu // base address: 0x0
1173daad67b5SFeifei Xu #define mmSYSHUB_INDEX                                                                                 0x0008
1174daad67b5SFeifei Xu #define mmSYSHUB_INDEX_BASE_IDX                                                                        0
1175daad67b5SFeifei Xu #define mmSYSHUB_DATA                                                                                  0x0009
1176daad67b5SFeifei Xu #define mmSYSHUB_DATA_BASE_IDX                                                                         0
1177daad67b5SFeifei Xu 
1178daad67b5SFeifei Xu 
1179daad67b5SFeifei Xu // addressBlock: rcc_strap_rcc_strap_internal
1180daad67b5SFeifei Xu // base address: 0x10100000
1181daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0                                                        0x403c000 // duplicate
1182daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0_BASE_IDX                                               3
1183daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1                                                        0x403c001 // duplicate
1184daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1_BASE_IDX                                               3
1185daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2                                                        0x403c002 // duplicate
1186daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2_BASE_IDX                                               3
1187daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3                                                        0x403c003 // duplicate
1188daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3_BASE_IDX                                               3
1189daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4                                                        0x403c004 // duplicate
1190daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4_BASE_IDX                                               3
1191daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5                                                        0x403c005 // duplicate
1192daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5_BASE_IDX                                               3
1193daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6                                                        0x403c006 // duplicate
1194daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6_BASE_IDX                                               3
1195daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7                                                        0x403c007 // duplicate
1196daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7_BASE_IDX                                               3
1197daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP0                                                                         0x403c080
1198daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP0_BASE_IDX                                                                3
1199daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP1                                                                         0x403c081
1200daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP1_BASE_IDX                                                                3
1201daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP2                                                                         0x403c082
1202daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP2_BASE_IDX                                                                3
1203daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP3                                                                         0x403c083
1204daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP3_BASE_IDX                                                                3
1205daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP4                                                                         0x403c084
1206daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP4_BASE_IDX                                                                3
1207daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP5                                                                         0x403c085
1208daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP5_BASE_IDX                                                                3
1209daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP6                                                                         0x403c086
1210daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP6_BASE_IDX                                                                3
1211daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP7                                                                         0x403c087
1212daad67b5SFeifei Xu #define mmRCC_DEV1_PORT_STRAP7_BASE_IDX                                                                3
1213daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0                                                        0x403cc00 // duplicate
1214daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0_BASE_IDX                                               3
1215daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1                                                        0x403cc01 // duplicate
1216daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1_BASE_IDX                                               3
1217daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2                                                        0x403cc02 // duplicate
1218daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2_BASE_IDX                                               3
1219daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3                                                        0x403cc03 // duplicate
1220daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3_BASE_IDX                                               3
1221daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4                                                        0x403cc04 // duplicate
1222daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4_BASE_IDX                                               3
1223daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5                                                        0x403cc05 // duplicate
1224daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5_BASE_IDX                                               3
1225daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8                                                        0x403cc08 // duplicate
1226daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8_BASE_IDX                                               3
1227daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9                                                        0x403cc09 // duplicate
1228daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9_BASE_IDX                                               3
1229daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13                                                       0x403cc0d // duplicate
1230daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13_BASE_IDX                                              3
1231daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0                                                        0x403cc80 // duplicate
1232daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0_BASE_IDX                                               3
1233daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2                                                        0x403cc82 // duplicate
1234daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2_BASE_IDX                                               3
1235daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3                                                        0x403cc83 // duplicate
1236daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3_BASE_IDX                                               3
1237daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4                                                        0x403cc84 // duplicate
1238daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4_BASE_IDX                                               3
1239daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5                                                        0x403cc85 // duplicate
1240daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5_BASE_IDX                                               3
1241daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6                                                        0x403cc86 // duplicate
1242daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6_BASE_IDX                                               3
1243daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7                                                        0x403cc87 // duplicate
1244daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7_BASE_IDX                                               3
1245daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10                                                       0x403cc8a // duplicate
1246daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10_BASE_IDX                                              3
1247daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11                                                       0x403cc8b // duplicate
1248daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11_BASE_IDX                                              3
1249daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12                                                       0x403cc8c // duplicate
1250daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12_BASE_IDX                                              3
1251daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13                                                       0x403cc8d // duplicate
1252daad67b5SFeifei Xu #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13_BASE_IDX                                              3
1253daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP0                                                                         0x403cd00
1254daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP0_BASE_IDX                                                                3
1255daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP2                                                                         0x403cd02
1256daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP2_BASE_IDX                                                                3
1257daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP3                                                                         0x403cd03
1258daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP3_BASE_IDX                                                                3
1259daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP4                                                                         0x403cd04
1260daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP4_BASE_IDX                                                                3
1261daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP5                                                                         0x403cd05
1262daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP5_BASE_IDX                                                                3
1263daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP6                                                                         0x403cd06
1264daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP6_BASE_IDX                                                                3
1265daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP13                                                                        0x403cd0d
1266daad67b5SFeifei Xu #define mmRCC_DEV0_EPF2_STRAP13_BASE_IDX                                                               3
1267daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP0                                                                         0x403cd80
1268daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP0_BASE_IDX                                                                3
1269daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP2                                                                         0x403cd82
1270daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP2_BASE_IDX                                                                3
1271daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP3                                                                         0x403cd83
1272daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP3_BASE_IDX                                                                3
1273daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP4                                                                         0x403cd84
1274daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP4_BASE_IDX                                                                3
1275daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP5                                                                         0x403cd85
1276daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP5_BASE_IDX                                                                3
1277daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP6                                                                         0x403cd86
1278daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP6_BASE_IDX                                                                3
1279daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP13                                                                        0x403cd8d
1280daad67b5SFeifei Xu #define mmRCC_DEV0_EPF3_STRAP13_BASE_IDX                                                               3
1281daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP0                                                                         0x403ce00
1282daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP0_BASE_IDX                                                                3
1283daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP2                                                                         0x403ce02
1284daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP2_BASE_IDX                                                                3
1285daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP3                                                                         0x403ce03
1286daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP3_BASE_IDX                                                                3
1287daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP4                                                                         0x403ce04
1288daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP4_BASE_IDX                                                                3
1289daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP5                                                                         0x403ce05
1290daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP5_BASE_IDX                                                                3
1291daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP6                                                                         0x403ce06
1292daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP6_BASE_IDX                                                                3
1293daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP13                                                                        0x403ce0d
1294daad67b5SFeifei Xu #define mmRCC_DEV0_EPF4_STRAP13_BASE_IDX                                                               3
1295daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP0                                                                         0x403ce80
1296daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP0_BASE_IDX                                                                3
1297daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP2                                                                         0x403ce82
1298daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP2_BASE_IDX                                                                3
1299daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP3                                                                         0x403ce83
1300daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP3_BASE_IDX                                                                3
1301daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP4                                                                         0x403ce84
1302daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP4_BASE_IDX                                                                3
1303daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP5                                                                         0x403ce85
1304daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP5_BASE_IDX                                                                3
1305daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP6                                                                         0x403ce86
1306daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP6_BASE_IDX                                                                3
1307daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP13                                                                        0x403ce8d
1308daad67b5SFeifei Xu #define mmRCC_DEV0_EPF5_STRAP13_BASE_IDX                                                               3
1309daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP0                                                                         0x403cf00
1310daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP0_BASE_IDX                                                                3
1311daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP2                                                                         0x403cf02
1312daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP2_BASE_IDX                                                                3
1313daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP3                                                                         0x403cf03
1314daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP3_BASE_IDX                                                                3
1315daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP4                                                                         0x403cf04
1316daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP4_BASE_IDX                                                                3
1317daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP5                                                                         0x403cf05
1318daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP5_BASE_IDX                                                                3
1319daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP6                                                                         0x403cf06
1320daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP6_BASE_IDX                                                                3
1321daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP13                                                                        0x403cf0d
1322daad67b5SFeifei Xu #define mmRCC_DEV0_EPF6_STRAP13_BASE_IDX                                                               3
1323daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP0                                                                         0x403cf80
1324daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP0_BASE_IDX                                                                3
1325daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP2                                                                         0x403cf82
1326daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP2_BASE_IDX                                                                3
1327daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP3                                                                         0x403cf83
1328daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP3_BASE_IDX                                                                3
1329daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP4                                                                         0x403cf84
1330daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP4_BASE_IDX                                                                3
1331daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP5                                                                         0x403cf85
1332daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP5_BASE_IDX                                                                3
1333daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP6                                                                         0x403cf86
1334daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP6_BASE_IDX                                                                3
1335daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP13                                                                        0x403cf8d
1336daad67b5SFeifei Xu #define mmRCC_DEV0_EPF7_STRAP13_BASE_IDX                                                               3
1337daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP0                                                                         0x403d000
1338daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP0_BASE_IDX                                                                3
1339daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP2                                                                         0x403d002
1340daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP2_BASE_IDX                                                                3
1341daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP3                                                                         0x403d003
1342daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP3_BASE_IDX                                                                3
1343daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP4                                                                         0x403d004
1344daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP4_BASE_IDX                                                                3
1345daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP5                                                                         0x403d005
1346daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP5_BASE_IDX                                                                3
1347daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP6                                                                         0x403d006
1348daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP6_BASE_IDX                                                                3
1349daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP13                                                                        0x403d00d
1350daad67b5SFeifei Xu #define mmRCC_DEV1_EPF0_STRAP13_BASE_IDX                                                               3
1351daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP0                                                                         0x403d080
1352daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP0_BASE_IDX                                                                3
1353daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP2                                                                         0x403d082
1354daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP2_BASE_IDX                                                                3
1355daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP3                                                                         0x403d083
1356daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP3_BASE_IDX                                                                3
1357daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP4                                                                         0x403d084
1358daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP4_BASE_IDX                                                                3
1359daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP5                                                                         0x403d085
1360daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP5_BASE_IDX                                                                3
1361daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP6                                                                         0x403d086
1362daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP6_BASE_IDX                                                                3
1363daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP13                                                                        0x403d08d
1364daad67b5SFeifei Xu #define mmRCC_DEV1_EPF1_STRAP13_BASE_IDX                                                               3
1365daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP0                                                                         0x403d100
1366daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP0_BASE_IDX                                                                3
1367daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP2                                                                         0x403d102
1368daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP2_BASE_IDX                                                                3
1369daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP3                                                                         0x403d103
1370daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP3_BASE_IDX                                                                3
1371daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP4                                                                         0x403d104
1372daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP4_BASE_IDX                                                                3
1373daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP5                                                                         0x403d105
1374daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP5_BASE_IDX                                                                3
1375daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP6                                                                         0x403d106
1376daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP6_BASE_IDX                                                                3
1377daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP13                                                                        0x403d10d
1378daad67b5SFeifei Xu #define mmRCC_DEV1_EPF2_STRAP13_BASE_IDX                                                               3
1379daad67b5SFeifei Xu 
1380daad67b5SFeifei Xu 
1381daad67b5SFeifei Xu // addressBlock: bif_rst_bif_rst_regblk
1382daad67b5SFeifei Xu // base address: 0x10100000
1383daad67b5SFeifei Xu #define ixHARD_RST_CTRL                                                                                0x38000
1384daad67b5SFeifei Xu #define ixRSMU_SOFT_RST_CTRL                                                                           0x38004
1385daad67b5SFeifei Xu #define ixSELF_SOFT_RST                                                                                0x38008
1386daad67b5SFeifei Xu #define ixGFX_DRV_MODE1_RST_CTRL                                                                       0x3800c
1387daad67b5SFeifei Xu #define ixBIF_RST_MISC_CTRL                                                                            0x38010
1388daad67b5SFeifei Xu #define ixBIF_RST_MISC_CTRL2                                                                           0x38014
1389daad67b5SFeifei Xu #define ixBIF_RST_MISC_CTRL3                                                                           0x38018
1390daad67b5SFeifei Xu #define ixBIF_RST_GFXVF_FLR_IDLE                                                                       0x3801c
1391daad67b5SFeifei Xu #define ixDEV0_PF0_FLR_RST_CTRL                                                                        0x38020
1392daad67b5SFeifei Xu #define ixDEV0_PF1_FLR_RST_CTRL                                                                        0x38024
1393daad67b5SFeifei Xu #define ixDEV0_PF2_FLR_RST_CTRL                                                                        0x38028
1394daad67b5SFeifei Xu #define ixDEV0_PF3_FLR_RST_CTRL                                                                        0x3802c
1395daad67b5SFeifei Xu #define ixDEV0_PF4_FLR_RST_CTRL                                                                        0x38030
1396daad67b5SFeifei Xu #define ixDEV0_PF5_FLR_RST_CTRL                                                                        0x38034
1397daad67b5SFeifei Xu #define ixDEV0_PF6_FLR_RST_CTRL                                                                        0x38038
1398daad67b5SFeifei Xu #define ixDEV0_PF7_FLR_RST_CTRL                                                                        0x3803c
1399daad67b5SFeifei Xu #define ixBIF_INST_RESET_INTR_STS                                                                      0x38040
1400daad67b5SFeifei Xu #define ixBIF_PF_FLR_INTR_STS                                                                          0x38044
1401daad67b5SFeifei Xu #define ixBIF_D3HOTD0_INTR_STS                                                                         0x38048
1402daad67b5SFeifei Xu #define ixBIF_POWER_INTR_STS                                                                           0x38050
1403daad67b5SFeifei Xu #define ixBIF_PF_DSTATE_INTR_STS                                                                       0x38054
1404daad67b5SFeifei Xu #define ixBIF_PF0_VF_FLR_INTR_STS                                                                      0x38060
1405daad67b5SFeifei Xu #define ixBIF_INST_RESET_INTR_MASK                                                                     0x38080
1406daad67b5SFeifei Xu #define ixBIF_PF_FLR_INTR_MASK                                                                         0x38084
1407daad67b5SFeifei Xu #define ixBIF_D3HOTD0_INTR_MASK                                                                        0x38088
1408daad67b5SFeifei Xu #define ixBIF_POWER_INTR_MASK                                                                          0x38090
1409daad67b5SFeifei Xu #define ixBIF_PF_DSTATE_INTR_MASK                                                                      0x38094
1410daad67b5SFeifei Xu #define ixBIF_PF0_VF_FLR_INTR_MASK                                                                     0x380a0
1411daad67b5SFeifei Xu #define ixBIF_PF_FLR_RST                                                                               0x38100
1412daad67b5SFeifei Xu #define ixBIF_PF0_VF_FLR_RST                                                                           0x38120
1413daad67b5SFeifei Xu #define ixBIF_DEV0_PF0_DSTATE_VALUE                                                                    0x38140
1414daad67b5SFeifei Xu #define ixBIF_DEV0_PF1_DSTATE_VALUE                                                                    0x38144
1415daad67b5SFeifei Xu #define ixBIF_DEV0_PF2_DSTATE_VALUE                                                                    0x38148
1416daad67b5SFeifei Xu #define ixBIF_DEV0_PF3_DSTATE_VALUE                                                                    0x3814c
1417daad67b5SFeifei Xu #define ixBIF_DEV0_PF4_DSTATE_VALUE                                                                    0x38150
1418daad67b5SFeifei Xu #define ixBIF_DEV0_PF5_DSTATE_VALUE                                                                    0x38154
1419daad67b5SFeifei Xu #define ixBIF_DEV0_PF6_DSTATE_VALUE                                                                    0x38158
1420daad67b5SFeifei Xu #define ixBIF_DEV0_PF7_DSTATE_VALUE                                                                    0x3815c
1421daad67b5SFeifei Xu #define ixDEV0_PF0_D3HOTD0_RST_CTRL                                                                    0x381e0
1422daad67b5SFeifei Xu #define ixDEV0_PF1_D3HOTD0_RST_CTRL                                                                    0x381e4
1423daad67b5SFeifei Xu #define ixDEV0_PF2_D3HOTD0_RST_CTRL                                                                    0x381e8
1424daad67b5SFeifei Xu #define ixDEV0_PF3_D3HOTD0_RST_CTRL                                                                    0x381ec
1425daad67b5SFeifei Xu #define ixDEV0_PF4_D3HOTD0_RST_CTRL                                                                    0x381f0
1426daad67b5SFeifei Xu #define ixDEV0_PF5_D3HOTD0_RST_CTRL                                                                    0x381f4
1427daad67b5SFeifei Xu #define ixDEV0_PF6_D3HOTD0_RST_CTRL                                                                    0x381f8
1428daad67b5SFeifei Xu #define ixDEV0_PF7_D3HOTD0_RST_CTRL                                                                    0x381fc
1429daad67b5SFeifei Xu #define ixBIF_PORT0_DSTATE_VALUE                                                                       0x388c0
1430daad67b5SFeifei Xu 
1431daad67b5SFeifei Xu 
1432daad67b5SFeifei Xu // addressBlock: bif_misc_bif_misc_regblk
1433daad67b5SFeifei Xu // base address: 0x10100000
1434daad67b5SFeifei Xu #define ixMISC_SCRATCH                                                                                 0x3a000
1435daad67b5SFeifei Xu #define ixINTR_LINE_POLARITY                                                                           0x3a004
1436daad67b5SFeifei Xu #define ixINTR_LINE_ENABLE                                                                             0x3a008
1437daad67b5SFeifei Xu #define ixOUTSTANDING_VC_ALLOC                                                                         0x3a00c
1438daad67b5SFeifei Xu #define ixBIFC_MISC_CTRL0                                                                              0x3a010
1439daad67b5SFeifei Xu #define ixBIFC_MISC_CTRL1                                                                              0x3a014
1440daad67b5SFeifei Xu #define ixBIFC_BME_ERR_LOG                                                                             0x3a018
1441daad67b5SFeifei Xu #define ixBIFC_RCCBIH_BME_ERR_LOG                                                                      0x3a01c
1442daad67b5SFeifei Xu #define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1                                                            0x3a020
1443daad67b5SFeifei Xu #define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3                                                            0x3a024
1444daad67b5SFeifei Xu #define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5                                                            0x3a028
1445daad67b5SFeifei Xu #define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7                                                            0x3a02c
1446daad67b5SFeifei Xu #define ixNBIF_VWIRE_CTRL                                                                              0x3a040
1447daad67b5SFeifei Xu #define ixNBIF_SMN_VWR_VCHG_DIS_CTRL                                                                   0x3a044
1448daad67b5SFeifei Xu #define ixNBIF_SMN_VWR_VCHG_RST_CTRL0                                                                  0x3a048
1449daad67b5SFeifei Xu #define ixNBIF_SMN_VWR_VCHG_TRIG                                                                       0x3a050
1450daad67b5SFeifei Xu #define ixNBIF_SMN_VWR_WTRIG_CNTL                                                                      0x3a054
1451daad67b5SFeifei Xu #define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1                                                                 0x3a058
1452daad67b5SFeifei Xu #define ixNBIF_MGCG_CTRL                                                                               0x3a05c
1453daad67b5SFeifei Xu #define ixNBIF_DS_CTRL_LCLK                                                                            0x3a060
1454daad67b5SFeifei Xu #define ixSMN_MST_CNTL0                                                                                0x3a064
1455daad67b5SFeifei Xu #define ixSMN_MST_EP_CNTL1                                                                             0x3a068
1456daad67b5SFeifei Xu #define ixSMN_MST_EP_CNTL2                                                                             0x3a06c
1457daad67b5SFeifei Xu #define ixNBIF_SDP_VWR_VCHG_DIS_CTRL                                                                   0x3a070
1458daad67b5SFeifei Xu #define ixNBIF_SDP_VWR_VCHG_RST_CTRL0                                                                  0x3a074
1459daad67b5SFeifei Xu #define ixNBIF_SDP_VWR_VCHG_RST_CTRL1                                                                  0x3a078
1460daad67b5SFeifei Xu #define ixNBIF_SDP_VWR_VCHG_TRIG                                                                       0x3a07c
1461daad67b5SFeifei Xu #define ixBME_DUMMY_CNTL_0                                                                             0x3a098
1462daad67b5SFeifei Xu #define ixBIFC_THT_CNTL                                                                                0x3a09c
1463daad67b5SFeifei Xu #define ixBIFC_HSTARB_CNTL                                                                             0x3a0a0
1464daad67b5SFeifei Xu #define ixBIFC_GSI_CNTL                                                                                0x3a0a4
1465daad67b5SFeifei Xu #define ixBIFC_PCIEFUNC_CNTL                                                                           0x3a0a8
1466daad67b5SFeifei Xu #define ixBIFC_SDP_CNTL_0                                                                              0x3a0b0
1467daad67b5SFeifei Xu #define ixBIFC_PERF_CNTL_0                                                                             0x3a0c0
1468daad67b5SFeifei Xu #define ixBIFC_PERF_CNTL_1                                                                             0x3a0c4
1469daad67b5SFeifei Xu #define ixBIFC_PERF_CNT_MMIO_RD                                                                        0x3a0c8
1470daad67b5SFeifei Xu #define ixBIFC_PERF_CNT_MMIO_WR                                                                        0x3a0cc
1471daad67b5SFeifei Xu #define ixBIFC_PERF_CNT_DMA_RD                                                                         0x3a0d0
1472daad67b5SFeifei Xu #define ixBIFC_PERF_CNT_DMA_WR                                                                         0x3a0d4
1473daad67b5SFeifei Xu #define ixNBIF_REGIF_ERRSET_CTRL                                                                       0x3a0d8
1474daad67b5SFeifei Xu #define ixSMN_MST_EP_CNTL3                                                                             0x3a0f0
1475daad67b5SFeifei Xu #define ixSMN_MST_EP_CNTL4                                                                             0x3a0f4
1476daad67b5SFeifei Xu #define ixBIF_SELFRING_BUFFER_VID                                                                      0x3a100
1477daad67b5SFeifei Xu #define ixBIF_SELFRING_VECTOR_CNTL                                                                     0x3a104
1478daad67b5SFeifei Xu 
1479daad67b5SFeifei Xu 
1480daad67b5SFeifei Xu // addressBlock: bif_ras_bif_ras_regblk
1481daad67b5SFeifei Xu // base address: 0x10100000
1482daad67b5SFeifei Xu #define ixBIF_RAS_LEAF0_CTRL                                                                           0x39000
1483daad67b5SFeifei Xu #define ixBIF_RAS_LEAF1_CTRL                                                                           0x39004
1484daad67b5SFeifei Xu #define ixBIF_RAS_LEAF2_CTRL                                                                           0x39008
1485daad67b5SFeifei Xu #define ixBIF_RAS_MISC_CTRL                                                                            0x39100
1486daad67b5SFeifei Xu #define ixBIF_IOHUB_RAS_IH_CNTL                                                                        0x39ff8
1487daad67b5SFeifei Xu #define ixBIF_RAS_VWR_FROM_IOHUB                                                                       0x39ffc
1488daad67b5SFeifei Xu 
1489daad67b5SFeifei Xu 
1490daad67b5SFeifei Xu // addressBlock: rcc_pfc_amdgfx_RCCPFCDEC
1491daad67b5SFeifei Xu // base address: 0x10134000
1492daad67b5SFeifei Xu #define ixRCC_PFC_LTR_CNTL                                                                             0x0100 // duplicate
1493daad67b5SFeifei Xu #define ixRCC_PFC_PME_RESTORE                                                                          0x0104 // duplicate
1494daad67b5SFeifei Xu #define ixRCC_PFC_STICKY_RESTORE_0                                                                     0x0108 // duplicate
1495daad67b5SFeifei Xu #define ixRCC_PFC_STICKY_RESTORE_1                                                                     0x010c // duplicate
1496daad67b5SFeifei Xu #define ixRCC_PFC_STICKY_RESTORE_2                                                                     0x0110 // duplicate
1497daad67b5SFeifei Xu #define ixRCC_PFC_STICKY_RESTORE_3                                                                     0x0114 // duplicate
1498daad67b5SFeifei Xu #define ixRCC_PFC_STICKY_RESTORE_4                                                                     0x0118 // duplicate
1499daad67b5SFeifei Xu #define ixRCC_PFC_STICKY_RESTORE_5                                                                     0x011c // duplicate
1500daad67b5SFeifei Xu #define ixRCC_PFC_AUXPWR_CNTL                                                                          0x0120 // duplicate
1501daad67b5SFeifei Xu 
1502daad67b5SFeifei Xu 
1503daad67b5SFeifei Xu // addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC
1504daad67b5SFeifei Xu // base address: 0x10134200
1505daad67b5SFeifei Xu #define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL                                                              0x0100 // duplicate
1506daad67b5SFeifei Xu #define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE                                                           0x0104 // duplicate
1507daad67b5SFeifei Xu #define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0                                                      0x0108 // duplicate
1508daad67b5SFeifei Xu #define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1                                                      0x010c // duplicate
1509daad67b5SFeifei Xu #define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2                                                      0x0110 // duplicate
1510daad67b5SFeifei Xu #define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3                                                      0x0114 // duplicate
1511daad67b5SFeifei Xu #define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4                                                      0x0118 // duplicate
1512daad67b5SFeifei Xu #define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5                                                      0x011c // duplicate
1513daad67b5SFeifei Xu #define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL                                                           0x0120 // duplicate
1514daad67b5SFeifei Xu 
1515daad67b5SFeifei Xu 
1516daad67b5SFeifei Xu // addressBlock: pciemsix_amdgfx_MSIXTDEC
1517daad67b5SFeifei Xu // base address: 0x10170000
1518daad67b5SFeifei Xu #define ixPCIEMSIX_VECT0_ADDR_LO                                                                       0x0000
1519daad67b5SFeifei Xu #define ixPCIEMSIX_VECT0_ADDR_HI                                                                       0x0004
1520daad67b5SFeifei Xu #define ixPCIEMSIX_VECT0_MSG_DATA                                                                      0x0008
1521daad67b5SFeifei Xu #define ixPCIEMSIX_VECT0_CONTROL                                                                       0x000c
1522daad67b5SFeifei Xu #define ixPCIEMSIX_VECT1_ADDR_LO                                                                       0x0010
1523daad67b5SFeifei Xu #define ixPCIEMSIX_VECT1_ADDR_HI                                                                       0x0014
1524daad67b5SFeifei Xu #define ixPCIEMSIX_VECT1_MSG_DATA                                                                      0x0018
1525daad67b5SFeifei Xu #define ixPCIEMSIX_VECT1_CONTROL                                                                       0x001c
1526daad67b5SFeifei Xu #define ixPCIEMSIX_VECT2_ADDR_LO                                                                       0x0020
1527daad67b5SFeifei Xu #define ixPCIEMSIX_VECT2_ADDR_HI                                                                       0x0024
1528daad67b5SFeifei Xu #define ixPCIEMSIX_VECT2_MSG_DATA                                                                      0x0028
1529daad67b5SFeifei Xu #define ixPCIEMSIX_VECT2_CONTROL                                                                       0x002c
1530daad67b5SFeifei Xu #define ixPCIEMSIX_VECT3_ADDR_LO                                                                       0x0030
1531daad67b5SFeifei Xu #define ixPCIEMSIX_VECT3_ADDR_HI                                                                       0x0034
1532daad67b5SFeifei Xu #define ixPCIEMSIX_VECT3_MSG_DATA                                                                      0x0038
1533daad67b5SFeifei Xu #define ixPCIEMSIX_VECT3_CONTROL                                                                       0x003c
1534daad67b5SFeifei Xu #define ixPCIEMSIX_VECT4_ADDR_LO                                                                       0x0040
1535daad67b5SFeifei Xu #define ixPCIEMSIX_VECT4_ADDR_HI                                                                       0x0044
1536daad67b5SFeifei Xu #define ixPCIEMSIX_VECT4_MSG_DATA                                                                      0x0048
1537daad67b5SFeifei Xu #define ixPCIEMSIX_VECT4_CONTROL                                                                       0x004c
1538daad67b5SFeifei Xu #define ixPCIEMSIX_VECT5_ADDR_LO                                                                       0x0050
1539daad67b5SFeifei Xu #define ixPCIEMSIX_VECT5_ADDR_HI                                                                       0x0054
1540daad67b5SFeifei Xu #define ixPCIEMSIX_VECT5_MSG_DATA                                                                      0x0058
1541daad67b5SFeifei Xu #define ixPCIEMSIX_VECT5_CONTROL                                                                       0x005c
1542daad67b5SFeifei Xu #define ixPCIEMSIX_VECT6_ADDR_LO                                                                       0x0060
1543daad67b5SFeifei Xu #define ixPCIEMSIX_VECT6_ADDR_HI                                                                       0x0064
1544daad67b5SFeifei Xu #define ixPCIEMSIX_VECT6_MSG_DATA                                                                      0x0068
1545daad67b5SFeifei Xu #define ixPCIEMSIX_VECT6_CONTROL                                                                       0x006c
1546daad67b5SFeifei Xu #define ixPCIEMSIX_VECT7_ADDR_LO                                                                       0x0070
1547daad67b5SFeifei Xu #define ixPCIEMSIX_VECT7_ADDR_HI                                                                       0x0074
1548daad67b5SFeifei Xu #define ixPCIEMSIX_VECT7_MSG_DATA                                                                      0x0078
1549daad67b5SFeifei Xu #define ixPCIEMSIX_VECT7_CONTROL                                                                       0x007c
1550daad67b5SFeifei Xu #define ixPCIEMSIX_VECT8_ADDR_LO                                                                       0x0080
1551daad67b5SFeifei Xu #define ixPCIEMSIX_VECT8_ADDR_HI                                                                       0x0084
1552daad67b5SFeifei Xu #define ixPCIEMSIX_VECT8_MSG_DATA                                                                      0x0088
1553daad67b5SFeifei Xu #define ixPCIEMSIX_VECT8_CONTROL                                                                       0x008c
1554daad67b5SFeifei Xu #define ixPCIEMSIX_VECT9_ADDR_LO                                                                       0x0090
1555daad67b5SFeifei Xu #define ixPCIEMSIX_VECT9_ADDR_HI                                                                       0x0094
1556daad67b5SFeifei Xu #define ixPCIEMSIX_VECT9_MSG_DATA                                                                      0x0098
1557daad67b5SFeifei Xu #define ixPCIEMSIX_VECT9_CONTROL                                                                       0x009c
1558daad67b5SFeifei Xu #define ixPCIEMSIX_VECT10_ADDR_LO                                                                      0x00a0
1559daad67b5SFeifei Xu #define ixPCIEMSIX_VECT10_ADDR_HI                                                                      0x00a4
1560daad67b5SFeifei Xu #define ixPCIEMSIX_VECT10_MSG_DATA                                                                     0x00a8
1561daad67b5SFeifei Xu #define ixPCIEMSIX_VECT10_CONTROL                                                                      0x00ac
1562daad67b5SFeifei Xu #define ixPCIEMSIX_VECT11_ADDR_LO                                                                      0x00b0
1563daad67b5SFeifei Xu #define ixPCIEMSIX_VECT11_ADDR_HI                                                                      0x00b4
1564daad67b5SFeifei Xu #define ixPCIEMSIX_VECT11_MSG_DATA                                                                     0x00b8
1565daad67b5SFeifei Xu #define ixPCIEMSIX_VECT11_CONTROL                                                                      0x00bc
1566daad67b5SFeifei Xu #define ixPCIEMSIX_VECT12_ADDR_LO                                                                      0x00c0
1567daad67b5SFeifei Xu #define ixPCIEMSIX_VECT12_ADDR_HI                                                                      0x00c4
1568daad67b5SFeifei Xu #define ixPCIEMSIX_VECT12_MSG_DATA                                                                     0x00c8
1569daad67b5SFeifei Xu #define ixPCIEMSIX_VECT12_CONTROL                                                                      0x00cc
1570daad67b5SFeifei Xu #define ixPCIEMSIX_VECT13_ADDR_LO                                                                      0x00d0
1571daad67b5SFeifei Xu #define ixPCIEMSIX_VECT13_ADDR_HI                                                                      0x00d4
1572daad67b5SFeifei Xu #define ixPCIEMSIX_VECT13_MSG_DATA                                                                     0x00d8
1573daad67b5SFeifei Xu #define ixPCIEMSIX_VECT13_CONTROL                                                                      0x00dc
1574daad67b5SFeifei Xu #define ixPCIEMSIX_VECT14_ADDR_LO                                                                      0x00e0
1575daad67b5SFeifei Xu #define ixPCIEMSIX_VECT14_ADDR_HI                                                                      0x00e4
1576daad67b5SFeifei Xu #define ixPCIEMSIX_VECT14_MSG_DATA                                                                     0x00e8
1577daad67b5SFeifei Xu #define ixPCIEMSIX_VECT14_CONTROL                                                                      0x00ec
1578daad67b5SFeifei Xu #define ixPCIEMSIX_VECT15_ADDR_LO                                                                      0x00f0
1579daad67b5SFeifei Xu #define ixPCIEMSIX_VECT15_ADDR_HI                                                                      0x00f4
1580daad67b5SFeifei Xu #define ixPCIEMSIX_VECT15_MSG_DATA                                                                     0x00f8
1581daad67b5SFeifei Xu #define ixPCIEMSIX_VECT15_CONTROL                                                                      0x00fc
1582daad67b5SFeifei Xu #define ixPCIEMSIX_VECT16_ADDR_LO                                                                      0x0100
1583daad67b5SFeifei Xu #define ixPCIEMSIX_VECT16_ADDR_HI                                                                      0x0104
1584daad67b5SFeifei Xu #define ixPCIEMSIX_VECT16_MSG_DATA                                                                     0x0108
1585daad67b5SFeifei Xu #define ixPCIEMSIX_VECT16_CONTROL                                                                      0x010c
1586daad67b5SFeifei Xu #define ixPCIEMSIX_VECT17_ADDR_LO                                                                      0x0110
1587daad67b5SFeifei Xu #define ixPCIEMSIX_VECT17_ADDR_HI                                                                      0x0114
1588daad67b5SFeifei Xu #define ixPCIEMSIX_VECT17_MSG_DATA                                                                     0x0118
1589daad67b5SFeifei Xu #define ixPCIEMSIX_VECT17_CONTROL                                                                      0x011c
1590daad67b5SFeifei Xu #define ixPCIEMSIX_VECT18_ADDR_LO                                                                      0x0120
1591daad67b5SFeifei Xu #define ixPCIEMSIX_VECT18_ADDR_HI                                                                      0x0124
1592daad67b5SFeifei Xu #define ixPCIEMSIX_VECT18_MSG_DATA                                                                     0x0128
1593daad67b5SFeifei Xu #define ixPCIEMSIX_VECT18_CONTROL                                                                      0x012c
1594daad67b5SFeifei Xu #define ixPCIEMSIX_VECT19_ADDR_LO                                                                      0x0130
1595daad67b5SFeifei Xu #define ixPCIEMSIX_VECT19_ADDR_HI                                                                      0x0134
1596daad67b5SFeifei Xu #define ixPCIEMSIX_VECT19_MSG_DATA                                                                     0x0138
1597daad67b5SFeifei Xu #define ixPCIEMSIX_VECT19_CONTROL                                                                      0x013c
1598daad67b5SFeifei Xu #define ixPCIEMSIX_VECT20_ADDR_LO                                                                      0x0140
1599daad67b5SFeifei Xu #define ixPCIEMSIX_VECT20_ADDR_HI                                                                      0x0144
1600daad67b5SFeifei Xu #define ixPCIEMSIX_VECT20_MSG_DATA                                                                     0x0148
1601daad67b5SFeifei Xu #define ixPCIEMSIX_VECT20_CONTROL                                                                      0x014c
1602daad67b5SFeifei Xu #define ixPCIEMSIX_VECT21_ADDR_LO                                                                      0x0150
1603daad67b5SFeifei Xu #define ixPCIEMSIX_VECT21_ADDR_HI                                                                      0x0154
1604daad67b5SFeifei Xu #define ixPCIEMSIX_VECT21_MSG_DATA                                                                     0x0158
1605daad67b5SFeifei Xu #define ixPCIEMSIX_VECT21_CONTROL                                                                      0x015c
1606daad67b5SFeifei Xu #define ixPCIEMSIX_VECT22_ADDR_LO                                                                      0x0160
1607daad67b5SFeifei Xu #define ixPCIEMSIX_VECT22_ADDR_HI                                                                      0x0164
1608daad67b5SFeifei Xu #define ixPCIEMSIX_VECT22_MSG_DATA                                                                     0x0168
1609daad67b5SFeifei Xu #define ixPCIEMSIX_VECT22_CONTROL                                                                      0x016c
1610daad67b5SFeifei Xu #define ixPCIEMSIX_VECT23_ADDR_LO                                                                      0x0170
1611daad67b5SFeifei Xu #define ixPCIEMSIX_VECT23_ADDR_HI                                                                      0x0174
1612daad67b5SFeifei Xu #define ixPCIEMSIX_VECT23_MSG_DATA                                                                     0x0178
1613daad67b5SFeifei Xu #define ixPCIEMSIX_VECT23_CONTROL                                                                      0x017c
1614daad67b5SFeifei Xu #define ixPCIEMSIX_VECT24_ADDR_LO                                                                      0x0180
1615daad67b5SFeifei Xu #define ixPCIEMSIX_VECT24_ADDR_HI                                                                      0x0184
1616daad67b5SFeifei Xu #define ixPCIEMSIX_VECT24_MSG_DATA                                                                     0x0188
1617daad67b5SFeifei Xu #define ixPCIEMSIX_VECT24_CONTROL                                                                      0x018c
1618daad67b5SFeifei Xu #define ixPCIEMSIX_VECT25_ADDR_LO                                                                      0x0190
1619daad67b5SFeifei Xu #define ixPCIEMSIX_VECT25_ADDR_HI                                                                      0x0194
1620daad67b5SFeifei Xu #define ixPCIEMSIX_VECT25_MSG_DATA                                                                     0x0198
1621daad67b5SFeifei Xu #define ixPCIEMSIX_VECT25_CONTROL                                                                      0x019c
1622daad67b5SFeifei Xu #define ixPCIEMSIX_VECT26_ADDR_LO                                                                      0x01a0
1623daad67b5SFeifei Xu #define ixPCIEMSIX_VECT26_ADDR_HI                                                                      0x01a4
1624daad67b5SFeifei Xu #define ixPCIEMSIX_VECT26_MSG_DATA                                                                     0x01a8
1625daad67b5SFeifei Xu #define ixPCIEMSIX_VECT26_CONTROL                                                                      0x01ac
1626daad67b5SFeifei Xu #define ixPCIEMSIX_VECT27_ADDR_LO                                                                      0x01b0
1627daad67b5SFeifei Xu #define ixPCIEMSIX_VECT27_ADDR_HI                                                                      0x01b4
1628daad67b5SFeifei Xu #define ixPCIEMSIX_VECT27_MSG_DATA                                                                     0x01b8
1629daad67b5SFeifei Xu #define ixPCIEMSIX_VECT27_CONTROL                                                                      0x01bc
1630daad67b5SFeifei Xu #define ixPCIEMSIX_VECT28_ADDR_LO                                                                      0x01c0
1631daad67b5SFeifei Xu #define ixPCIEMSIX_VECT28_ADDR_HI                                                                      0x01c4
1632daad67b5SFeifei Xu #define ixPCIEMSIX_VECT28_MSG_DATA                                                                     0x01c8
1633daad67b5SFeifei Xu #define ixPCIEMSIX_VECT28_CONTROL                                                                      0x01cc
1634daad67b5SFeifei Xu #define ixPCIEMSIX_VECT29_ADDR_LO                                                                      0x01d0
1635daad67b5SFeifei Xu #define ixPCIEMSIX_VECT29_ADDR_HI                                                                      0x01d4
1636daad67b5SFeifei Xu #define ixPCIEMSIX_VECT29_MSG_DATA                                                                     0x01d8
1637daad67b5SFeifei Xu #define ixPCIEMSIX_VECT29_CONTROL                                                                      0x01dc
1638daad67b5SFeifei Xu #define ixPCIEMSIX_VECT30_ADDR_LO                                                                      0x01e0
1639daad67b5SFeifei Xu #define ixPCIEMSIX_VECT30_ADDR_HI                                                                      0x01e4
1640daad67b5SFeifei Xu #define ixPCIEMSIX_VECT30_MSG_DATA                                                                     0x01e8
1641daad67b5SFeifei Xu #define ixPCIEMSIX_VECT30_CONTROL                                                                      0x01ec
1642daad67b5SFeifei Xu #define ixPCIEMSIX_VECT31_ADDR_LO                                                                      0x01f0
1643daad67b5SFeifei Xu #define ixPCIEMSIX_VECT31_ADDR_HI                                                                      0x01f4
1644daad67b5SFeifei Xu #define ixPCIEMSIX_VECT31_MSG_DATA                                                                     0x01f8
1645daad67b5SFeifei Xu #define ixPCIEMSIX_VECT31_CONTROL                                                                      0x01fc
1646daad67b5SFeifei Xu 
1647daad67b5SFeifei Xu 
1648daad67b5SFeifei Xu // addressBlock: pciemsix_amdgfx_MSIXPDEC
1649daad67b5SFeifei Xu // base address: 0x10171000
1650daad67b5SFeifei Xu #define ixPCIEMSIX_PBA                                                                                 0x0000
1651daad67b5SFeifei Xu 
1652daad67b5SFeifei Xu 
1653daad67b5SFeifei Xu // addressBlock: syshub_mmreg_ind_syshubind
1654daad67b5SFeifei Xu // base address: 0x0
1655daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK                                                         0x10000 // duplicate
1656daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK                                                        0x10004 // duplicate
1657daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK                                      0x10008 // duplicate
1658daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK                                         0x1000c // duplicate
1659daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL                                                  0x10010 // duplicate
1660daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL                                                  0x10014 // duplicate
1661daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL                                                         0x10018 // duplicate
1662daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL                                                         0x1001c // duplicate
1663daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL                                                         0x10020 // duplicate
1664daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL                                                         0x10024 // duplicate
1665daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL                                                         0x10028 // duplicate
1666daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL                                                         0x1002c // duplicate
1667daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL                                                         0x10030 // duplicate
1668daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL                                                         0x10034 // duplicate
1669daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL                                                                0x10300 // duplicate
1670daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE                                                             0x10308 // duplicate
1671daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER                                                               0x1030c // duplicate
1672daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_SYSHUB_SCRATCH                                                                0x10f00 // duplicate
1673daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK                                                        0x11000 // duplicate
1674daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK                                                       0x11004 // duplicate
1675daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK                                     0x11008 // duplicate
1676daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK                                        0x1100c // duplicate
1677daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL                                                  0x11010 // duplicate
1678daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL                                                  0x11014 // duplicate
1679daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL                                                         0x11018 // duplicate
1680daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL                                                         0x1101c // duplicate
1681daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL                                                         0x11020 // duplicate
1682daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL                                                         0x11024 // duplicate
1683daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL                                                         0x11028 // duplicate
1684daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL                                                         0x1102c // duplicate
1685daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL                                                         0x11030 // duplicate
1686daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL                                                         0x11034 // duplicate
1687daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL                                                         0x11038 // duplicate
1688daad67b5SFeifei Xu #define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL                                                         0x1103c // duplicate
1689daad67b5SFeifei Xu 
1690daad67b5SFeifei Xu #endif
1691