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/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-ld4.c23 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ in upll_init()
25 tmp &= ~0x18000000; in upll_init()
32 tmp &= ~0x07ffffff; in upll_init()
33 tmp |= 0x0228f5c0; in upll_init()
36 tmp &= ~0x07ffffff; in upll_init()
37 tmp |= 0x02328000; in upll_init()
44 tmp |= 0x08000000; in upll_init()
51 tmp |= 0x10000000; in upll_init()
64 tmp |= 0x00000001; in vpll_init()
67 tmp |= 0x00000001; in vpll_init()
[all …]
H A Dpll-pro4.c30 tmp |= 0x00000001; in vpll_init()
33 tmp |= 0x00000001; in vpll_init()
38 tmp &= ~0x10000000; in vpll_init()
41 tmp &= ~0x10000000; in vpll_init()
44 /* Set VPLA_M and VPLB_M to 0x20 */ in vpll_init()
46 tmp &= ~0x0000007f; in vpll_init()
47 tmp |= 0x00000020; in vpll_init()
50 tmp &= ~0x0000007f; in vpll_init()
51 tmp |= 0x00000020; in vpll_init()
58 tmp &= ~0x000fffff; in vpll_init()
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dintegratorap.dts17 #size-cells = <0>;
19 cpu@0 {
28 reg = <0>;
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dt104xd4rdb.dtsi42 size = <0 0x1000000>;
43 alignment = <0 0x1000000>;
46 size = <0 0x400000>;
47 alignment = <0 0x400000>;
50 size = <0 0x2000000>;
51 alignment = <0 0x2000000>;
56 reg = <0xf 0xfe124000 0 0x2000>;
57 ranges = <0 0 0xf 0xe8000000 0x08000000
58 2 0 0xf 0xff800000 0x00010000
59 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dt104xrdb.dtsi48 size = <0 0x1000000>;
49 alignment = <0 0x1000000>;
52 size = <0 0x400000>;
53 alignment = <0 0x400000>;
56 size = <0 0x2000000>;
57 alignment = <0 0x2000000>;
62 reg = <0xf 0xfe124000 0 0x2000>;
63 ranges = <0 0 0xf 0xe8000000 0x08000000
64 2 0 0xf 0xff800000 0x00010000
65 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dt1023rdb.dts50 size = <0 0x1000000>;
51 alignment = <0 0x1000000>;
55 size = <0 0x400000>;
56 alignment = <0 0x400000>;
60 size = <0 0x2000000>;
61 alignment = <0 0x2000000>;
66 reg = <0xf 0xfe124000 0 0x2000>;
67 ranges = <0 0 0xf 0xe8000000 0x08000000
68 1 0 0xf 0xff800000 0x00010000>;
70 nor@0,0 {
[all …]
H A Dt1024rdb.dts54 size = <0 0x1000000>;
55 alignment = <0 0x1000000>;
59 size = <0 0x400000>;
60 alignment = <0 0x400000>;
64 size = <0 0x2000000>;
65 alignment = <0 0x2000000>;
70 reg = <0xf 0xfe124000 0 0x2000>;
71 ranges = <0 0 0xf 0xe8000000 0x08000000
72 2 0 0xf 0xff800000 0x00010000
73 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dkmcent2.dts27 size = <0 0x1000000>;
28 alignment = <0 0x1000000>;
31 size = <0 0x400000>;
32 alignment = <0 0x400000>;
35 size = <0 0x2000000>;
36 alignment = <0 0x2000000>;
41 reg = <0xf 0xfe124000 0 0x2000>;
42 ranges = <0 0 0xf 0xe8000000 0x04000000
43 1 0 0xf 0xfa000000 0x00010000
44 2 0 0xf 0xfb000000 0x00010000
[all …]
H A Dt1024qds.dts50 size = <0 0x1000000>;
51 alignment = <0 0x1000000>;
55 size = <0 0x400000>;
56 alignment = <0 0x400000>;
60 size = <0 0x2000000>;
61 alignment = <0 0x2000000>;
66 reg = <0xf 0xfe124000 0 0x2000>;
67 ranges = <0 0 0xf 0xe8000000 0x08000000
68 2 0 0xf 0xff800000 0x00010000
69 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dt104xqds.dtsi74 size = <0 0x1000000>;
75 alignment = <0 0x1000000>;
78 size = <0 0x400000>;
79 alignment = <0 0x400000>;
82 size = <0 0x2000000>;
83 alignment = <0 0x2000000>;
88 reg = <0xf 0xfe124000 0 0x2000>;
89 ranges = <0 0 0xf 0xe8000000 0x08000000
90 2 0 0xf 0xff800000 0x00010000
91 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Datmel,ebi.txt103 reg = <0x10000000 0x10000000
104 0x40000000 0x30000000>;
105 ranges = <0x0 0x0 0x10000000 0x10000000
106 0x1 0x0 0x40000000 0x10000000
107 0x2 0x0 0x50000000 0x10000000
108 0x3 0x0 0x60000000 0x10000000>;
112 pinctrl-0 = <&pinctrl_ebi_addr>;
114 nor: flash@0,0 {
118 reg = <0x0 0x0 0x1000000>;
124 atmel,smc-ncs-rd-setup-ns = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Datmel-nand.txt38 device (always 0)
39 3rd entry: the memory region size (always 0x800000)
75 reg = <0x70000000 0x8000000>;
80 reg = <0xffffc070 0x490>,
81 <0xffffc500 0x100>;
89 reg = <0x10000000 0x10000000
90 0x40000000 0x30000000>;
91 ranges = <0x0 0x0 0x10000000 0x10000000
92 0x1 0x0 0x40000000 0x10000000
93 0x2 0x0 0x50000000 0x10000000
[all …]
/openbmc/linux/arch/arm/boot/dts/cirrus/
H A Dep7209.dtsi28 #address-cells = <0>;
29 #size-cells = <0>;
47 reg = <0x80000000 0xc000>;
53 reg = <0x80000000 0x4000>;
60 reg = <0x80000000 0x1 0x80000040 0x1>;
67 reg = <0x80000001 0x1 0x80000041 0x1>;
74 reg = <0x80000003 0x1 0x80000043 0x1>;
81 reg = <0x80000083 0x1 0x800000c3 0x1>;
88 reg = <0x80000100 0x80>;
96 reg = <0x80000180 0x80>;
[all …]
/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/openbmc/u-boot/arch/mips/include/asm/
H A Dmalta.h10 #define MALTA_GT_BASE 0x1be00000
11 #define MALTA_GT_PCIIO_BASE 0x18000000
12 #define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8)
14 #define MALTA_MSC01_BIU_BASE 0x1bc80000
15 #define MALTA_MSC01_PCI_BASE 0x1bd00000
16 #define MALTA_MSC01_PBC_BASE 0x1bd40000
17 #define MALTA_MSC01_IP1_BASE 0x1bc00000
18 #define MALTA_MSC01_IP1_SIZE 0x00400000
19 #define MALTA_MSC01_IP2_BASE1 0x10000000
20 #define MALTA_MSC01_IP2_SIZE1 0x08000000
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dcpu.h11 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
12 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
13 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
14 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
16 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
17 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
18 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
20 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
21 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
22 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
[all …]
/openbmc/linux/arch/xtensa/include/asm/
H A Dkmem_layout.h23 #define XCHAL_PAGE_TABLE_VADDR __XTENSA_UL_CONST(0x80000000)
24 #define XCHAL_PAGE_TABLE_SIZE __XTENSA_UL_CONST(0x00400000)
28 #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000)
29 #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000)
30 #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000)
31 #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x08000000)
37 #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xb0000000)
38 #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000)
39 #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x10000000)
40 #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/stm32/
H A Dst,mlahb.yaml61 reg = <0x10000000 0x40000>;
63 dma-ranges = <0x00000000 0x38000000 0x10000>,
64 <0x10000000 0x10000000 0x60000>,
65 <0x30000000 0x30000000 0x60000>;
68 reg = <0x10000000 0x40000>;
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dexynos5422-odroidxu3.dts23 reg = <0x40000000 0x10000000
24 0x50000000 0x10000000
25 0x60000000 0x10000000
26 0x70000000 0x10000000
27 0x80000000 0x10000000
28 0x90000000 0x10000000
29 0xa0000000 0x10000000
30 0xb0000000 0xea00000>;
42 reg = <0x66>;
240 regulator-name = "vdd_1.0v_ldo";
[all …]
/openbmc/u-boot/board/freescale/mpc8555cds/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 0, 0, BOOKE_PAGESZ_4K, 0),
17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
18 MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 0, 0, BOOKE_PAGESZ_4K, 0),
20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/openbmc/u-boot/board/freescale/mpc8541cds/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 0, 0, BOOKE_PAGESZ_4K, 0),
17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
18 MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 0, 0, BOOKE_PAGESZ_4K, 0),
20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/openbmc/linux/arch/mips/boot/dts/loongson/
H A Drs780e-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000
9 0 0x40000000 0 0x40000000 0 0x40000000
10 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
18 reg = <0 0x1a000000 0 0x02000000>;
20 ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x0000c000>,
21 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
28 ranges = <1 0 0 0x18000000 0x4000>;
32 reg = <1 0x70 0x8>;
39 reg = <1 0x800 0x100>;
H A Dloongson64v_4core_virtio.dts12 #address-cells = <0>;
22 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
23 0 0x3ff00000 0 0x3ff00000 0x100000
24 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
28 reg = <0 0x3ff01400 0x64>;
37 loongson,parent_int_map = <0x00000001>, /* int0 */
38 <0xfffffffe>, /* int1 */
39 <0x00000000>, /* int2 */
40 <0x00000000>; /* int3 */
46 reg = <0 0x1fe001e0 0x8>;
[all …]
/openbmc/linux/drivers/staging/wlan-ng/
H A Dp80211metadef.h35 P80211DID_MKITEM(1) | 0x00000000)
39 P80211DID_MKITEM(2) | 0x00000000)
46 P80211DID_MKITEM(1) | 0x00000000)
50 P80211DID_MKITEM(2) | 0x00000000)
87 P80211DID_MKITEM(1) | 0x00000000)
91 P80211DID_MKITEM(2) | 0x00000000)
98 P80211DID_MKITEM(1) | 0x00000000)
102 P80211DID_MKITEM(2) | 0x00000000)
106 P80211DID_MKITEM(3) | 0x00000000)
113 P80211DID_MKITEM(1) | 0x00000000)
[all …]

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