Lines Matching +full:0 +full:x10000000

13 	/* TLB 0 - for temp stack in cache */
14 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 		      0, 0, BOOKE_PAGESZ_4K, 0),
17 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
18 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 		      0, 0, BOOKE_PAGESZ_4K, 0),
20 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 		      0, 0, BOOKE_PAGESZ_4K, 0),
23 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
24 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 		      0, 0, BOOKE_PAGESZ_4K, 0),
28 	 * TLB 0:	16M	Non-cacheable, guarded
29 	 * 0xff000000	16M	FLASH
34 		      0, 0, BOOKE_PAGESZ_16M, 1),
38 	 * 0x80000000	256M	PCI1 MEM First half
42 		      0, 1, BOOKE_PAGESZ_256M, 1),
46 	 * 0x90000000	256M	PCI1 MEM Second half
48 	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
50 		      0, 2, BOOKE_PAGESZ_256M, 1),
54 	 * 0xa0000000	256M	PCI2 MEM First half
58 		      0, 3, BOOKE_PAGESZ_256M, 1),
62 	 * 0xb0000000	256M	PCI2 MEM Second half
64 	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
66 		      0, 4, BOOKE_PAGESZ_256M, 1),
70 	 * 0xe000_0000	1M	CCSRBAR
71 	 * 0xe200_0000	16M	PCI1 IO
72 	 * 0xe300_0000	16M	PCI2 IO
76 		      0, 5, BOOKE_PAGESZ_64M, 1),
80 	 * 0xf000_0000	64M	LBC SDRAM
83 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
84 		      0, 6, BOOKE_PAGESZ_64M, 1),
88 	 * 0xf8000000	1M	CADMUS registers
92 		      0, 7, BOOKE_PAGESZ_1M, 1),