Home
last modified time | relevance | path

Searched +full:0 +full:x1 (Results 1 – 25 of 1093) sorted by relevance

12345678910>>...44

/openbmc/linux/sound/soc/codecs/
H A Dmt6359.h11 #define MT6359_TOP0_ID 0x0
12 #define MT6359_SMT_CON1 0x32
13 #define MT6359_DRV_CON2 0x3c
14 #define MT6359_DRV_CON3 0x3e
15 #define MT6359_DRV_CON4 0x40
16 #define MT6359_TOP_CKPDN_CON0 0x10c
17 #define MT6359_TOP_CKPDN_CON0_SET 0x10e
18 #define MT6359_TOP_CKPDN_CON0_CLR 0x110
19 #define MT6359_AUXADC_RQST0 0x1108
20 #define MT6359_AUXADC_CON10 0x11a0
[all …]
H A Dmt6358.h21 #define RG_VOW13M_CK_PDN_MASK 0x1
22 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
24 #define RG_VOW32K_CK_PDN_MASK 0x1
25 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
27 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
28 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
30 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
31 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
33 #define RG_AUDNCP_CK_PDN_MASK 0x1
34 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)
[all …]
H A Drt5616.h13 #define RT5616_RESET 0x00
14 #define RT5616_VERSION_ID 0xfd
15 #define RT5616_VENDOR_ID 0xfe
16 #define RT5616_DEVICE_ID 0xff
18 #define RT5616_HP_VOL 0x02
19 #define RT5616_LOUT_CTRL1 0x03
20 #define RT5616_LOUT_CTRL2 0x05
22 #define RT5616_IN1_IN2 0x0d
23 #define RT5616_INL1_INR1_VOL 0x0f
25 #define RT5616_DAC1_DIG_VOL 0x19
[all …]
H A Drt5651.h15 #define RT5651_RESET 0x00
16 #define RT5651_VERSION_ID 0xfd
17 #define RT5651_VENDOR_ID 0xfe
18 #define RT5651_DEVICE_ID 0xff
20 #define RT5651_HP_VOL 0x02
21 #define RT5651_LOUT_CTRL1 0x03
22 #define RT5651_LOUT_CTRL2 0x05
24 #define RT5651_IN1_IN2 0x0d
25 #define RT5651_IN3 0x0e
26 #define RT5651_INL1_INR1_VOL 0x0f
[all …]
H A Drt5645.h13 #define RT5645_RESET 0x00
14 #define RT5645_VENDOR_ID 0xfd
15 #define RT5645_VENDOR_ID1 0xfe
16 #define RT5645_VENDOR_ID2 0xff
18 #define RT5645_SPK_VOL 0x01
19 #define RT5645_HP_VOL 0x02
20 #define RT5645_LOUT1 0x03
21 #define RT5645_LOUT_CTRL 0x05
23 #define RT5645_IN1_CTRL1 0x0a
24 #define RT5645_IN1_CTRL2 0x0b
[all …]
H A Drt5640.h18 #define RT5640_RESET 0x00
19 #define RT5640_VENDOR_ID 0xfd
20 #define RT5640_VENDOR_ID1 0xfe
21 #define RT5640_VENDOR_ID2 0xff
23 #define RT5640_SPK_VOL 0x01
24 #define RT5640_HP_VOL 0x02
25 #define RT5640_OUTPUT 0x03
26 #define RT5640_MONO_OUT 0x04
28 #define RT5640_IN1_IN2 0x0d
29 #define RT5640_IN3_IN4 0x0e
[all …]
H A Drt5670.h13 #define RT5670_RESET 0x00
14 #define RT5670_VENDOR_ID 0xfd
15 #define RT5670_VENDOR_ID1 0xfe
16 #define RT5670_VENDOR_ID2 0xff
18 #define RT5670_HP_VOL 0x02
19 #define RT5670_LOUT1 0x03
21 #define RT5670_CJ_CTRL1 0x0a
22 #define RT5670_CJ_CTRL2 0x0b
23 #define RT5670_CJ_CTRL3 0x0c
24 #define RT5670_IN2 0x0e
[all …]
H A Drt5631.h6 #define RT5631_RESET 0x00
7 #define RT5631_SPK_OUT_VOL 0x02
8 #define RT5631_HP_OUT_VOL 0x04
9 #define RT5631_MONO_AXO_1_2_VOL 0x06
10 #define RT5631_AUX_IN_VOL 0x0A
11 #define RT5631_STEREO_DAC_VOL_1 0x0C
12 #define RT5631_MIC_CTRL_1 0x0E
13 #define RT5631_STEREO_DAC_VOL_2 0x10
14 #define RT5631_ADC_CTRL_1 0x12
15 #define RT5631_ADC_REC_MIXER 0x14
[all …]
/openbmc/linux/drivers/infiniband/hw/qib/
H A Dqib_7220_regs.h37 #define QIB_7220_Revision_OFFS 0x0
38 #define QIB_7220_Revision_R_Simulator_LSB 0x3F
39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7220_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1
42 #define QIB_7220_Revision_R_Emulation_Revcode_LSB 0x28
43 #define QIB_7220_Revision_R_Emulation_Revcode_RMASK 0x3FFFFF
44 #define QIB_7220_Revision_BoardID_LSB 0x20
45 #define QIB_7220_Revision_BoardID_RMASK 0xFF
46 #define QIB_7220_Revision_R_SW_LSB 0x18
[all …]
H A Dqib_6120_regs.h35 #define QIB_6120_Revision_OFFS 0x0
36 #define QIB_6120_Revision_R_Simulator_LSB 0x3F
37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
38 #define QIB_6120_Revision_Reserved_LSB 0x28
39 #define QIB_6120_Revision_Reserved_RMASK 0x7FFFFF
40 #define QIB_6120_Revision_BoardID_LSB 0x20
41 #define QIB_6120_Revision_BoardID_RMASK 0xFF
42 #define QIB_6120_Revision_R_SW_LSB 0x18
43 #define QIB_6120_Revision_R_SW_RMASK 0xFF
44 #define QIB_6120_Revision_R_Arch_LSB 0x10
[all …]
H A Dqib_7322_regs.h35 #define QIB_7322_Revision_OFFS 0x0
36 #define QIB_7322_Revision_DEF 0x0000000002010601
37 #define QIB_7322_Revision_R_Simulator_LSB 0x3F
38 #define QIB_7322_Revision_R_Simulator_MSB 0x3F
39 #define QIB_7322_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7322_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7322_Revision_R_Emulation_MSB 0x3E
42 #define QIB_7322_Revision_R_Emulation_RMASK 0x1
43 #define QIB_7322_Revision_R_Emulation_Revcode_LSB 0x28
44 #define QIB_7322_Revision_R_Emulation_Revcode_MSB 0x3D
[all …]
/openbmc/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-reg.h26 #define BCK_INVERSE_MASK 0x1
27 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
31 #define VUL12_ON_MASK 0x1
32 #define VUL12_ON_MASK_SFT (0x1 << 31)
34 #define MOD_DAI_ON_MASK 0x1
35 #define MOD_DAI_ON_MASK_SFT (0x1 << 30)
37 #define DAI_ON_MASK 0x1
38 #define DAI_ON_MASK_SFT (0x1 << 29)
40 #define DAI2_ON_MASK 0x1
41 #define DAI2_ON_MASK_SFT (0x1 << 28)
[all …]
/openbmc/linux/sound/soc/mediatek/mt6797/
H A Dmt6797-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x0028
[all …]
/openbmc/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x0028
[all …]
/openbmc/qemu/tests/tcg/arm/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
/openbmc/qemu/tests/tcg/loongarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
/openbmc/qemu/tests/tcg/aarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffffffff) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffffffff) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffffffff) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffffffff) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffffffff) flags=OK (1/1)
[all …]
/openbmc/qemu/tests/tcg/ppc64le/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffc00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffc00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
/openbmc/linux/drivers/soc/samsung/
H A Dexynos3250-pmu.c15 { EXYNOS3_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
16 { EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
17 { EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
18 { EXYNOS3_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
19 { EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
20 { EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
21 { EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
22 { EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
23 { EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
24 { EXYNOS3_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
[all …]
H A Dexynos4-pmu.c15 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
16 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
17 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
18 { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
19 { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
20 { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
21 { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
22 { S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } },
23 { S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } },
24 { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
[all …]
H A Dexynos5250-pmu.c15 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
16 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
17 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
18 { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
19 { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
20 { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
21 { EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
22 { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
23 { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
24 { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
[all …]
/openbmc/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_hsi.h89 LL2_OK = 0,
147 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
148 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0
149 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */
188 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
189 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
190 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
192 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
277 CORE_RX_PKT_SOURCE_NETWORK = 0,
322 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_enum.h28 CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0,
29 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
32 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0,
33 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
36 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0,
37 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
38 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2,
39 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
42 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x0,
43 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1,
[all …]
H A Ddce_11_0_enum.h28 CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0,
29 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
32 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0,
33 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
36 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0,
37 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
38 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2,
39 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
42 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x0,
43 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1,
[all …]

12345678910>>...44