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/openbmc/qemu/tests/tcg/arm/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
4 to int32: 0 (INVALID)
5 to int64: 0 (INVALID)
6 to uint32: 0 (INVALID)
7 to uint64: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
10 to int32: 0 (INVALID)
11 to int64: 0 (INVALID)
[all …]
/openbmc/qemu/tests/tcg/loongarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
4 to int32: 0 (INVALID)
5 to int64: 0 (INVALID)
6 to uint32: 0 (INVALID)
7 to uint64: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
10 to int32: 0 (INVALID)
11 to int64: 0 (INVALID)
[all …]
/openbmc/qemu/tests/tcg/aarch64/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffe00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffe00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
4 to int32: 0 (INVALID)
5 to int64: 0 (INVALID)
6 to uint32: 0 (INVALID)
7 to uint64: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
10 to int32: 0 (INVALID)
11 to int64: 0 (INVALID)
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffffffff) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffffffff) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffffffff) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffffffff) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffffffff) flags=OK (1/1)
[all …]
H A Dfloat_convd.ref2 from double: f64(nan:0x007ff4000000000000)
3 to single: f32(-nan:0xffffffff) (INVALID)
8 from double: f64(-nan:0x00fff8000000000000)
9 to single: f32(-nan:0xffffffff) (OK)
14 from double: f64(-inf:0x00fff0000000000000)
15 to single: f32(-inf:0xff800000) (OK)
18 to uint32: 0 (INVALID)
19 to uint64: 0 (INVALID)
20 from double: f64(-0x1.fffffffffffff0000000p+1023:0x00ffefffffffffffff)
21 to single: f32(-inf:0xff800000) (OVERFLOW INEXACT )
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00ffffffffffffffff) (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00ffffffffffffffff) (OK)
14 from single: f32(-inf:0xff800000)
15 to double: f64(-inf:0x00fff0000000000000) (OK)
18 to uint32: 0 (INVALID)
19 to uint64: 0 (INVALID)
20 from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
21 to double: f64(-0x1.fffffe00000000000000p+127:0x00c7efffffe0000000) (OK)
[all …]
/openbmc/qemu/tests/tcg/ppc64le/
H A Dfloat_madds.ref2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000)
3 res: f32(-nan:0xffe00000) flags=INVALID (0/0)
4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000)
5 res: f32(-nan:0xffc00000) flags=INVALID (0/1)
6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000)
7 res: f32(-nan:0xffc00000) flags=INVALID (0/2)
8 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
9 res: f32(-nan:0xffc00000) flags=OK (1/0)
10 op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000)
11 res: f32(-nan:0xffc00000) flags=OK (1/1)
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fff4000000000000) (OK)
6 to uint32: 0 (INVALID)
7 to uint64: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
12 to uint32: 0 (INVALID)
13 to uint64: 0 (INVALID)
14 from single: f32(-inf:0xff800000)
15 to double: f64(-inf:0x00fff0000000000000) (OK)
[all …]
/openbmc/u-boot/drivers/i2c/
H A Dast_i2c.h27 /* 0x00 : I2CD Function Control Register */
28 #define I2CD_BUFF_SEL_MASK (0x7 << 20)
30 #define I2CD_M_SDA_LOCK_EN (0x1 << 16)
31 #define I2CD_MULTI_MASTER_DIS (0x1 << 15)
32 #define I2CD_M_SCL_DRIVE_EN (0x1 << 14)
33 #define I2CD_MSB_STS (0x1 << 9)
34 #define I2CD_SDA_DRIVE_1T_EN (0x1 << 8)
35 #define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7)
36 #define I2CD_M_HIGH_SPEED_EN (0x1 << 6)
37 #define I2CD_DEF_ADDR_EN (0x1 << 5)
[all …]
/openbmc/qemu/tests/qtest/
H A Dfuzz-sdcard-test.c24 " -drive if=none,index=0,file=null-co://,format=raw,id=d0"); in oss_fuzz_29225()
26 qtest_outl(s, 0xcf8, 0x80001010); in oss_fuzz_29225()
27 qtest_outl(s, 0xcfc, 0xd0690); in oss_fuzz_29225()
28 qtest_outl(s, 0xcf8, 0x80001003); in oss_fuzz_29225()
29 qtest_outl(s, 0xcf8, 0x80001013); in oss_fuzz_29225()
30 qtest_outl(s, 0xcfc, 0xffffffff); in oss_fuzz_29225()
31 qtest_outl(s, 0xcf8, 0x80001003); in oss_fuzz_29225()
32 qtest_outl(s, 0xcfc, 0x3effe00); in oss_fuzz_29225()
34 qtest_bufwrite(s, 0xff0d062c, "\xff", 0x1); in oss_fuzz_29225()
35 qtest_bufwrite(s, 0xff0d060f, "\xb7", 0x1); in oss_fuzz_29225()
[all …]
/openbmc/u-boot/drivers/sound/
H A Drt5677.h19 #define RT5677_RESET 0x00
20 #define RT5677_VENDOR_ID 0xfd
21 #define RT5677_VENDOR_ID1 0xfe
22 #define RT5677_VENDOR_ID2 0xff
28 #define RT5677_LOUT1 0x01
30 #define RT5677_IN1 0x03
31 #define RT5677_MICBIAS 0x04
33 #define RT5677_SLIMBUS_PARAM 0x07
34 #define RT5677_SLIMBUS_RX 0x08
35 #define RT5677_SLIMBUS_CTRL 0x09
[all …]
/openbmc/qemu/tests/tcg/i386/
H A Dtest-i386-fpatan.c10 { -__builtin_infl(), -__builtin_infl(), -0x2.5b2f8fe6643a46ap+0L, -0x2.5b2f8fe6643a469cp+0L },
11 { -__builtin_infl(), -1.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
12 { -__builtin_infl(), -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
13 { -__builtin_infl(), 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
14 { -__builtin_infl(), 1.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
15 { -__builtin_infl(), __builtin_infl(), 0x2.5b2f8fe6643a469cp+0L, 0x2.5b2f8fe6643a46ap+0L },
16 { -1.0L, -__builtin_infl(), -0x1.921fb54442d1846ap+0L, -0x1.921fb54442d18468p+0L },
17 { -1.0L, -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
18 { -1.0L, 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
19 { -1.0L, __builtin_infl(), 0x1.921fb54442d18468p+0L, 0x1.921fb54442d1846ap+0L },
[all …]
H A Dtest-i386-fyl2x.c31 { 0x1p-16400L, 1.5L, -24600.0L, -24600.0L },
33 …{ 0x2.0a40b4bd6349d53p+14380L, -0x3.612a1cec52e70388p-14116L, -0xb.dd9637a24570d1ap-14104L, -0xb.d…
34 …{ 0xa.a3dc18b1eff7e8ap-4L, 0x7.423575b7ac0ba6a8p-7212L, -0x4.45ac6ae2f9cc1a7p-7212L, -0x4.45ac6ae2…
35 …{ 0x1.51167cab1deec25ep-9616L, 0xb.79bece734a62216p-14512L, -0x1.af0880f05109d5c8p-14496L, -0x1.af…
36 …{ 0x1.55691f3dee65eb88p+6420L, -0x2.e081398cd6691b98p-2640L, -0x4.8275aa22ebb6ebe8p-2628L, -0x4.82…
37 …{ 0x3.71cca195c06ba4d4p-6312L, -0xb.14b747fa4cc13d1p+5052L, 0x1.112301748a1cc83p+5068L, 0x1.112301…
38 …{ 0x2.0f924dde0806572p+8924L, -0x7.ece8699d62a9f76p-14464L, -0x1.144eba5c079d0fa2p-14448L, -0x1.14…
39 …{ 0x4.b875c0342c9f86b8p-5832L, 0xe.a37e0fa859e499cp+732L, -0x1.4d5bc95e2af0bb08p+748L, -0x1.4d5bc9…
40 …{ 0x7.23210d9474f0715p+364L, -0x5.baaf3a431730f158p-2436L, -0x8.35afbc04cd37fafp-2428L, -0x8.35afb…
41 …{ 0xd.2330923899aae43p+776L, 0x2.a68cc6ddbe3b3a5p+6528L, 0x8.12b3f5a7b346e37p+6536L, 0x8.12b3f5a7b…
[all …]
H A Dfloat_convs.ref2 from single: f32(-nan:0xffe00000)
3 to double: f64(-nan:0x00fffc000000000000) (OK)
6 to uint32: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
12 to uint32: 0 (INVALID)
14 from single: f32(-inf:0xff800000)
15 to double: f64(-inf:0x00fff0000000000000) (OK)
18 to uint32: 0 (INVALID)
20 from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
[all …]
/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_hpipe.h10 #define SD_EXTERNAL_CONFIG0_REG 0
16 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
19 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
31 (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
33 #define SD_EXTERNAL_CONFIG1_REG 0x4
36 (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
39 (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
42 (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
45 (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
47 #define SD_EXTERNAL_CONFIG2_REG 0x8
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dmmc.h16 u32 gctrl; /* 0x00 global control */
17 u32 clkcr; /* 0x04 clock control */
18 u32 timeout; /* 0x08 time out */
19 u32 width; /* 0x0c bus width */
20 u32 blksz; /* 0x10 block size */
21 u32 bytecnt; /* 0x14 byte count */
22 u32 cmd; /* 0x18 command */
23 u32 arg; /* 0x1c argument */
24 u32 resp0; /* 0x20 response 0 */
25 u32 resp1; /* 0x24 response 1 */
[all …]
/openbmc/u-boot/include/
H A Datmel_hlcdc.h42 #define LCDC_LCDCFG0_CLKPOL (0x1 << 0)
43 #define LCDC_LCDCFG0_CLKSEL (0x1 << 2)
44 #define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3)
45 #define LCDC_LCDCFG0_CGDISBASE (0x1 << 8)
46 #define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9)
47 #define LCDC_LCDCFG0_CGDISHEO (0x1 << 11)
48 #define LCDC_LCDCFG0_CGDISHCR (0x1 << 12)
50 #define LCDC_LCDCFG0_CLKDIV_Msk (0xff << LCDC_LCDCFG0_CLKDIV_Pos)
54 #define LCDC_LCDCFG1_HSPW_Pos 0
55 #define LCDC_LCDCFG1_HSPW_Msk (0x3f << LCDC_LCDCFG1_HSPW_Pos)
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddp.h14 unsigned char res1[0x10];
27 unsigned char res2[0x4];
68 unsigned char res3[0x288];
71 unsigned char res4[0x10];
78 unsigned char res5[0xc];
81 unsigned char res6[0x2c];
87 unsigned char res7[0x8];
90 unsigned char res8[0x1c];
92 unsigned char res9[0x200];
98 unsigned char res10[0x2c];
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx7ulp-pinfunc.h26 #define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0
27 #define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0
28 #define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0
29 #define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2
30 #define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2
31 #define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2
32 #define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2
33 #define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2
34 #define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0
35 #define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dedp_rk3288.h11 u8 res0[0x10];
13 u8 res1[0x4];
20 u8 res2[0xc];
22 u8 res3[0x4];
59 u8 res4[0x28];
63 u8 res6[0xc];
66 u8 res7[0x4];
73 u8 res8[0x224];
75 u8 res9[0x14];
77 u8 res10[0x48];
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dsc-regs.h13 #define SC_BASE_ADDR 0x61840000
15 #define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110)
16 #define SC_DPLLOSCCTRL_DPLLST (0x1 << 1)
17 #define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0)
19 #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
20 #define SC_DPLLCTRL_SSC_EN (0x1 << 31)
21 #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
22 #define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
24 #define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
25 #define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
[all …]
/openbmc/qemu/tests/tcg/x86_64/
H A Dfloat_convs.ref2 from single: f32(-nan:0xffa00000)
3 to double: f64(-nan:0x00fffc000000000000) (INVALID)
6 to uint32: 0 (INVALID)
8 from single: f32(-nan:0xffc00000)
9 to double: f64(-nan:0x00fff8000000000000) (OK)
12 to uint32: 0 (INVALID)
14 from single: f32(-inf:0xff800000)
15 to double: f64(-inf:0x00fff0000000000000) (OK)
18 to uint32: 0 (INVALID)
20 from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff)
[all …]

12345678910>>...41